| Revision | da241033ec8d27e92951c3e8a324a0eef693ff64 (tree) |
|---|---|
| Time | 2014-04-18 03:38:30 |
| Author | Masahiro Yamada <yamada.m@jp.p...> |
| Commiter | Tom Rini |
board: samsung: delete unused source files
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Mateusz Zalega <m.zalega@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Acked-by: Mateusz Zalega <m.zalega@samsung.com>
board/samsung/goni/mem_setup.S board/samsung/smdkc100/mem_setup.S| @@ -1,249 +0,0 @@ | ||
| 1 | -/* | |
| 2 | - * Copyright (C) 2009 Samsung Electrnoics | |
| 3 | - * Minkyu Kang <mk7.kang@samsung.com> | |
| 4 | - * Kyungmin Park <kyungmin.park@samsung.com> | |
| 5 | - * | |
| 6 | - * SPDX-License-Identifier: GPL-2.0+ | |
| 7 | - */ | |
| 8 | - | |
| 9 | -#include <config.h> | |
| 10 | - | |
| 11 | - .globl mem_ctrl_asm_init | |
| 12 | -mem_ctrl_asm_init: | |
| 13 | - cmp r7, r8 | |
| 14 | - | |
| 15 | - ldreq r0, =S5PC100_DMC_BASE @ 0xE6000000 | |
| 16 | - ldrne r0, =S5PC110_DMC0_BASE @ 0xF0000000 | |
| 17 | - ldrne r6, =S5PC110_DMC1_BASE @ 0xF1400000 | |
| 18 | - | |
| 19 | - /* DLL parameter setting */ | |
| 20 | - ldr r1, =0x50101000 | |
| 21 | - str r1, [r0, #0x018] @ PHYCONTROL0_OFFSET | |
| 22 | - strne r1, [r6, #0x018] @ PHYCONTROL0_OFFSET | |
| 23 | - ldr r1, =0x000000f4 | |
| 24 | - str r1, [r0, #0x01C] @ PHYCONTROL1_OFFSET | |
| 25 | - strne r1, [r6, #0x01C] @ PHYCONTROL1_OFFSET | |
| 26 | - ldreq r1, =0x0 | |
| 27 | - streq r1, [r0, #0x020] @ PHYCONTROL2_OFFSET | |
| 28 | - | |
| 29 | - /* DLL on */ | |
| 30 | - ldr r1, =0x50101002 | |
| 31 | - str r1, [r0, #0x018] @ PHYCONTROL0_OFFSET | |
| 32 | - strne r1, [r6, #0x018] @ PHYCONTROL0_OFFSET | |
| 33 | - | |
| 34 | - /* DLL start */ | |
| 35 | - ldr r1, =0x50101003 | |
| 36 | - str r1, [r0, #0x018] @ PHYCONTROL0_OFFSET | |
| 37 | - strne r1, [r6, #0x018] @ PHYCONTROL0_OFFSET | |
| 38 | - | |
| 39 | - mov r2, #0x4000 | |
| 40 | -wait: subs r2, r2, #0x1 | |
| 41 | - cmp r2, #0x0 | |
| 42 | - bne wait | |
| 43 | - | |
| 44 | - cmp r7, r8 | |
| 45 | - /* Force value locking for DLL off */ | |
| 46 | - str r1, [r0, #0x018] @ PHYCONTROL0_OFFSET | |
| 47 | - strne r1, [r6, #0x018] @ PHYCONTROL0_OFFSET | |
| 48 | - | |
| 49 | - /* DLL off */ | |
| 50 | - ldr r1, =0x50101009 | |
| 51 | - str r1, [r0, #0x018] @ PHYCONTROL0_OFFSET | |
| 52 | - strne r1, [r6, #0x018] @ PHYCONTROL0_OFFSET | |
| 53 | - | |
| 54 | - /* auto refresh off */ | |
| 55 | - ldr r1, =0xff001010 | (1 << 7) | |
| 56 | - ldr r2, =0xff001010 | (1 << 7) | |
| 57 | - str r1, [r0, #0x000] @ CONCONTROL_OFFSET | |
| 58 | - strne r2, [r6, #0x000] @ CONCONTROL_OFFSET | |
| 59 | - | |
| 60 | - /* | |
| 61 | - * Burst Length 4, 2 chips, 32-bit, LPDDR | |
| 62 | - * OFF: dynamic self refresh, force precharge, dynamic power down off | |
| 63 | - */ | |
| 64 | - ldr r1, =0x00212100 | |
| 65 | - ldr r2, =0x00212100 | |
| 66 | - str r1, [r0, #0x004] @ MEMCONTROL_OFFSET | |
| 67 | - strne r2, [r6, #0x004] @ MEMCONTROL_OFFSET | |
| 68 | - | |
| 69 | - /* | |
| 70 | - * Note: | |
| 71 | - * If Bank0 has Mobile RAM we place it at 0x3800'0000 (s5pc100 only) | |
| 72 | - * So finally Bank1 OneDRAM should address start at at 0x3000'0000 | |
| 73 | - */ | |
| 74 | - | |
| 75 | - /* | |
| 76 | - * DMC0: CS0 : S5PC100/S5PC110 | |
| 77 | - * 0x30 -> 0x30000000 | |
| 78 | - * 0xf8 -> 0x37FFFFFF | |
| 79 | - * [15:12] 0: Linear | |
| 80 | - * [11:8 ] 2: 9 bits | |
| 81 | - * [ 7:4 ] 2: 14 bits | |
| 82 | - * [ 3:0 ] 2: 4 banks | |
| 83 | - */ | |
| 84 | - ldr r3, =0x30f80222 | |
| 85 | - ldr r4, =0x40f00222 | |
| 86 | -swap_memory: | |
| 87 | - str r3, [r0, #0x008] @ MEMCONFIG0_OFFSET | |
| 88 | - str r4, [r0, #0x00C] @ dummy write | |
| 89 | - | |
| 90 | - /* | |
| 91 | - * DMC1: CS0 : S5PC110 | |
| 92 | - * 0x40 -> 0x40000000 | |
| 93 | - * 0xf8 -> 0x47FFFFFF (1Gib) | |
| 94 | - * 0x40 -> 0x40000000 | |
| 95 | - * 0xf0 -> 0x4FFFFFFF (2Gib) | |
| 96 | - * [15:12] 0: Linear | |
| 97 | - * [11:8 ] 2: 9 bits - Col (1Gib) | |
| 98 | - * [11:8 ] 3: 10 bits - Col (2Gib) | |
| 99 | - * [ 7:4 ] 2: 14 bits - Row | |
| 100 | - * [ 3:0 ] 2: 4 banks | |
| 101 | - */ | |
| 102 | - /* Default : 2GiB */ | |
| 103 | - ldr r4, =0x40f01322 @ 2Gib: MCP B | |
| 104 | - ldr r5, =0x50f81312 @ dummy: MCP D | |
| 105 | - cmp r9, #1 | |
| 106 | - ldreq r4, =0x40f81222 @ 1Gib: MCP A | |
| 107 | - cmp r9, #3 | |
| 108 | - ldreq r5, =0x50f81312 @ 2Gib + 1Gib: MCP D | |
| 109 | - cmp r9, #4 | |
| 110 | - ldreq r5, =0x50f01312 @ 2Gib + 2Gib: MCP E | |
| 111 | - | |
| 112 | - cmp r7, r8 | |
| 113 | - strne r4, [r6, #0x008] @ MEMCONFIG0_OFFSET | |
| 114 | - strne r5, [r6, #0x00C] @ MEMCONFIG1_OFFSET | |
| 115 | - | |
| 116 | - /* | |
| 117 | - * DMC0: CS1: S5PC100 | |
| 118 | - * 0x38 -> 0x38000000 | |
| 119 | - * 0xf8 -> 0x3fFFFFFF | |
| 120 | - * [15:12] 0: Linear | |
| 121 | - * [11:8 ] 2: 9 bits | |
| 122 | - * [ 7:4 ] 2: 14 bits | |
| 123 | - * [ 3:0 ] 2: 4 banks | |
| 124 | - */ | |
| 125 | - eoreq r3, r3, #0x08000000 | |
| 126 | - streq r3, [r0, #0xc] @ MEMCONFIG1_OFFSET | |
| 127 | - | |
| 128 | - ldr r1, =0x20000000 | |
| 129 | - str r1, [r0, #0x014] @ PRECHCONFIG_OFFSET | |
| 130 | - strne r1, [r0, #0x014] @ PRECHCONFIG_OFFSET | |
| 131 | - strne r1, [r6, #0x014] @ PRECHCONFIG_OFFSET | |
| 132 | - | |
| 133 | - /* | |
| 134 | - * S5PC100: | |
| 135 | - * DMC: CS0: 166MHz | |
| 136 | - * CS1: 166MHz | |
| 137 | - * S5PC110: | |
| 138 | - * DMC0: CS0: 166MHz | |
| 139 | - * DMC1: CS0: 200MHz | |
| 140 | - * | |
| 141 | - * 7.8us * 200MHz %LE %LONG1560(0x618) | |
| 142 | - * 7.8us * 166MHz %LE %LONG1294(0x50E) | |
| 143 | - * 7.8us * 133MHz %LE %LONG1038(0x40E), | |
| 144 | - * 7.8us * 100MHz %LE %LONG780(0x30C), | |
| 145 | - */ | |
| 146 | - ldr r1, =0x0000050E | |
| 147 | - str r1, [r0, #0x030] @ TIMINGAREF_OFFSET | |
| 148 | - ldrne r1, =0x00000618 | |
| 149 | - strne r1, [r6, #0x030] @ TIMINGAREF_OFFSET | |
| 150 | - | |
| 151 | - ldr r1, =0x14233287 | |
| 152 | - str r1, [r0, #0x034] @ TIMINGROW_OFFSET | |
| 153 | - ldrne r1, =0x182332c8 | |
| 154 | - strne r1, [r6, #0x034] @ TIMINGROW_OFFSET | |
| 155 | - | |
| 156 | - ldr r1, =0x12130005 | |
| 157 | - str r1, [r0, #0x038] @ TIMINGDATA_OFFSET | |
| 158 | - ldrne r1, =0x13130005 | |
| 159 | - strne r1, [r6, #0x038] @ TIMINGDATA_OFFSET | |
| 160 | - | |
| 161 | - ldr r1, =0x0E140222 | |
| 162 | - str r1, [r0, #0x03C] @ TIMINGPOWER_OFFSET | |
| 163 | - ldrne r1, =0x0E180222 | |
| 164 | - strne r1, [r6, #0x03C] @ TIMINGPOWER_OFFSET | |
| 165 | - | |
| 166 | - /* chip0 Deselect */ | |
| 167 | - ldr r1, =0x07000000 | |
| 168 | - str r1, [r0, #0x010] @ DIRECTCMD_OFFSET | |
| 169 | - strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET | |
| 170 | - | |
| 171 | - /* chip0 PALL */ | |
| 172 | - ldr r1, =0x01000000 | |
| 173 | - str r1, [r0, #0x010] @ DIRECTCMD_OFFSET | |
| 174 | - strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET | |
| 175 | - | |
| 176 | - /* chip0 REFA */ | |
| 177 | - ldr r1, =0x05000000 | |
| 178 | - str r1, [r0, #0x010] @ DIRECTCMD_OFFSET | |
| 179 | - strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET | |
| 180 | - /* chip0 REFA */ | |
| 181 | - str r1, [r0, #0x010] @ DIRECTCMD_OFFSET | |
| 182 | - strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET | |
| 183 | - | |
| 184 | - /* chip0 MRS */ | |
| 185 | - ldr r1, =0x00000032 | |
| 186 | - str r1, [r0, #0x010] @ DIRECTCMD_OFFSET | |
| 187 | - strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET | |
| 188 | - | |
| 189 | - /* chip0 EMRS */ | |
| 190 | - ldr r1, =0x00020020 | |
| 191 | - str r1, [r0, #0x010] @ DIRECTCMD_OFFSET | |
| 192 | - strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET | |
| 193 | - | |
| 194 | - /* chip1 Deselect */ | |
| 195 | - ldr r1, =0x07100000 | |
| 196 | - str r1, [r0, #0x010] @ DIRECTCMD_OFFSET | |
| 197 | - strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET | |
| 198 | - | |
| 199 | - /* chip1 PALL */ | |
| 200 | - ldr r1, =0x01100000 | |
| 201 | - str r1, [r0, #0x010] @ DIRECTCMD_OFFSET | |
| 202 | - strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET | |
| 203 | - | |
| 204 | - /* chip1 REFA */ | |
| 205 | - ldr r1, =0x05100000 | |
| 206 | - str r1, [r0, #0x010] @ DIRECTCMD_OFFSET | |
| 207 | - strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET | |
| 208 | - /* chip1 REFA */ | |
| 209 | - str r1, [r0, #0x010] @ DIRECTCMD_OFFSET | |
| 210 | - strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET | |
| 211 | - | |
| 212 | - /* chip1 MRS */ | |
| 213 | - ldr r1, =0x00100032 | |
| 214 | - str r1, [r0, #0x010] @ DIRECTCMD_OFFSET | |
| 215 | - strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET | |
| 216 | - | |
| 217 | - /* chip1 EMRS */ | |
| 218 | - ldr r1, =0x00120020 | |
| 219 | - str r1, [r0, #0x010] @ DIRECTCMD_OFFSET | |
| 220 | - strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET | |
| 221 | - | |
| 222 | - /* auto refresh on */ | |
| 223 | - ldr r1, =0xFF002030 | (1 << 7) | |
| 224 | - str r1, [r0, #0x000] @ CONCONTROL_OFFSET | |
| 225 | - strne r1, [r6, #0x000] @ CONCONTROL_OFFSET | |
| 226 | - | |
| 227 | - /* PwrdnConfig */ | |
| 228 | - ldr r1, =0x00100002 | |
| 229 | - str r1, [r0, #0x028] @ PWRDNCONFIG_OFFSET | |
| 230 | - strne r1, [r6, #0x028] @ PWRDNCONFIG_OFFSET | |
| 231 | - | |
| 232 | - ldr r1, =0x00212113 | |
| 233 | - str r1, [r0, #0x004] @ MEMCONTROL_OFFSET | |
| 234 | - strne r1, [r6, #0x004] @ MEMCONTROL_OFFSET | |
| 235 | - | |
| 236 | - /* Skip when S5PC110 */ | |
| 237 | - bne 1f | |
| 238 | - | |
| 239 | - /* Check OneDRAM access area at s5pc100 */ | |
| 240 | - ldreq r3, =0x38f80222 | |
| 241 | - ldreq r1, =0x37ffff00 | |
| 242 | - str r3, [r1] | |
| 243 | - ldr r2, [r1] | |
| 244 | - cmp r2, r3 | |
| 245 | - beq swap_memory | |
| 246 | -1: | |
| 247 | - mov pc, lr | |
| 248 | - | |
| 249 | - .ltorg |
| @@ -1,181 +0,0 @@ | ||
| 1 | -/* | |
| 2 | - * Originates from Samsung's u-boot 1.1.6 port to S5PC1xx | |
| 3 | - * | |
| 4 | - * Copyright (C) 2009 Samsung Electrnoics | |
| 5 | - * Inki Dae <inki.dae@samsung.com> | |
| 6 | - * Heungjun Kim <riverful.kim@samsung.com> | |
| 7 | - * Minkyu Kang <mk7.kang@samsung.com> | |
| 8 | - * Kyungmin Park <kyungmin.park@samsung.com> | |
| 9 | - * | |
| 10 | - * SPDX-License-Identifier: GPL-2.0+ | |
| 11 | - */ | |
| 12 | - | |
| 13 | -#include <config.h> | |
| 14 | - | |
| 15 | - .globl mem_ctrl_asm_init | |
| 16 | -mem_ctrl_asm_init: | |
| 17 | - ldr r6, =S5PC100_DMC_BASE @ 0xE6000000 | |
| 18 | - | |
| 19 | - /* DLL parameter setting */ | |
| 20 | - ldr r1, =0x50101000 | |
| 21 | - str r1, [r6, #0x018] @ PHYCONTROL0 | |
| 22 | - ldr r1, =0xf4 | |
| 23 | - str r1, [r6, #0x01C] @ PHYCONTROL1 | |
| 24 | - ldr r1, =0x0 | |
| 25 | - str r1, [r6, #0x020] @ PHYCONTROL2 | |
| 26 | - | |
| 27 | - /* DLL on */ | |
| 28 | - ldr r1, =0x50101002 | |
| 29 | - str r1, [r6, #0x018] @ PHYCONTROL0 | |
| 30 | - | |
| 31 | - /* DLL start */ | |
| 32 | - ldr r1, =0x50101003 | |
| 33 | - str r1, [r6, #0x018] @ PHYCONTROL0 | |
| 34 | - | |
| 35 | - /* Force value locking for DLL off */ | |
| 36 | - str r1, [r6, #0x018] @ PHYCONTROL0 | |
| 37 | - | |
| 38 | - /* DLL off */ | |
| 39 | - ldr r1, =0x50101001 | |
| 40 | - str r1, [r6, #0x018] @ PHYCONTROL0 | |
| 41 | - | |
| 42 | - /* auto refresh off */ | |
| 43 | - ldr r1, =0xff001010 | |
| 44 | - str r1, [r6, #0x000] @ CONCONTROL | |
| 45 | - | |
| 46 | - /* | |
| 47 | - * Burst Length 4, 2 chips, 32-bit, LPDDR | |
| 48 | - * OFF: dynamic self refresh, force precharge, dynamic power down off | |
| 49 | - */ | |
| 50 | - ldr r1, =0x00212100 | |
| 51 | - str r1, [r6, #0x004] @ MEMCONTROL | |
| 52 | - | |
| 53 | - /* | |
| 54 | - * Note: | |
| 55 | - * If Bank0 has OneDRAM we place it at 0x2800'0000 | |
| 56 | - * So finally Bank1 should address start at at 0x2000'0000 | |
| 57 | - */ | |
| 58 | - mov r4, #0x0 | |
| 59 | - | |
| 60 | -swap_memory: | |
| 61 | - /* | |
| 62 | - * Bank0 | |
| 63 | - * 0x30 -> 0x30000000 | |
| 64 | - * 0xf8 -> 0x37FFFFFF | |
| 65 | - * [15:12] 0: Linear | |
| 66 | - * [11:8 ] 2: 9 bits | |
| 67 | - * [ 7:4 ] 2: 14 bits | |
| 68 | - * [ 3:0 ] 2: 4 banks | |
| 69 | - */ | |
| 70 | - ldr r1, =0x30f80222 | |
| 71 | - /* if r4 is 1, swap the bank */ | |
| 72 | - cmp r4, #0x1 | |
| 73 | - orreq r1, r1, #0x08000000 | |
| 74 | - str r1, [r6, #0x008] @ MEMCONFIG0 | |
| 75 | - | |
| 76 | - /* | |
| 77 | - * Bank1 | |
| 78 | - * 0x38 -> 0x38000000 | |
| 79 | - * 0xf8 -> 0x3fFFFFFF | |
| 80 | - * [15:12] 0: Linear | |
| 81 | - * [11:8 ] 2: 9 bits | |
| 82 | - * [ 7:4 ] 2: 14 bits | |
| 83 | - * [ 3:0 ] 2: 4 banks | |
| 84 | - */ | |
| 85 | - ldr r1, =0x38f80222 | |
| 86 | - /* if r4 is 1, swap the bank */ | |
| 87 | - cmp r4, #0x1 | |
| 88 | - biceq r1, r1, #0x08000000 | |
| 89 | - str r1, [r6, #0x00c] @ MEMCONFIG1 | |
| 90 | - | |
| 91 | - ldr r1, =0x20000000 | |
| 92 | - str r1, [r6, #0x014] @ PRECHCONFIG | |
| 93 | - | |
| 94 | - /* | |
| 95 | - * FIXME: Please verify these values | |
| 96 | - * 7.8us * 166MHz %LE %LONG1294(0x50E) | |
| 97 | - * 7.8us * 133MHz %LE %LONG1038(0x40E), | |
| 98 | - * 7.8us * 100MHz %LE %LONG780(0x30C), | |
| 99 | - * 7.8us * 20MHz %LE %LONG156(0x9C), | |
| 100 | - * 7.8us * 10MHz %LE %LONG78(0x4E) | |
| 101 | - */ | |
| 102 | - ldr r1, =0x0000050e | |
| 103 | - str r1, [r6, #0x030] @ TIMINGAREF | |
| 104 | - | |
| 105 | - /* 166 MHz */ | |
| 106 | - ldr r1, =0x0c233287 | |
| 107 | - str r1, [r6, #0x034] @ TIMINGROW | |
| 108 | - | |
| 109 | - /* twtr=3 twr=2 trtp=3 cl=3 wl=3 rl=3 */ | |
| 110 | - ldr r1, =0x32330303 | |
| 111 | - str r1, [r6, #0x038] @ TIMINGDATA | |
| 112 | - | |
| 113 | - /* tfaw=4 sxsr=0x14 txp=0x14 tcke=3 tmrd=3 */ | |
| 114 | - ldr r1, =0x04141433 | |
| 115 | - str r1, [r6, #0x03C] @ TIMINGPOWER | |
| 116 | - | |
| 117 | - /* chip0 Deselect */ | |
| 118 | - ldr r1, =0x07000000 | |
| 119 | - str r1, [r6, #0x010] @ DIRECTCMD | |
| 120 | - | |
| 121 | - /* chip0 PALL */ | |
| 122 | - ldr r1, =0x01000000 | |
| 123 | - str r1, [r6, #0x010] @ DIRECTCMD | |
| 124 | - | |
| 125 | - /* chip0 REFA */ | |
| 126 | - ldr r1, =0x05000000 | |
| 127 | - str r1, [r6, #0x010] @ DIRECTCMD | |
| 128 | - /* chip0 REFA */ | |
| 129 | - str r1, [r6, #0x010] @ DIRECTCMD | |
| 130 | - | |
| 131 | - /* chip0 MRS, CL%LE %LONG3, BL%LE %LONG4 */ | |
| 132 | - ldr r1, =0x00000032 | |
| 133 | - str r1, [r6, #0x010] @ DIRECTCMD | |
| 134 | - | |
| 135 | - /* chip1 Deselect */ | |
| 136 | - ldr r1, =0x07100000 | |
| 137 | - str r1, [r6, #0x010] @ DIRECTCMD | |
| 138 | - | |
| 139 | - /* chip1 PALL */ | |
| 140 | - ldr r1, =0x01100000 | |
| 141 | - str r1, [r6, #0x010] @ DIRECTCMD | |
| 142 | - | |
| 143 | - /* chip1 REFA */ | |
| 144 | - ldr r1, =0x05100000 | |
| 145 | - str r1, [r6, #0x010] @ DIRECTCMD | |
| 146 | - /* chip1 REFA */ | |
| 147 | - str r1, [r6, #0x010] @ DIRECTCMD | |
| 148 | - | |
| 149 | - /* chip1 MRS, CL%LE %LONG3, BL%LE %LONG4 */ | |
| 150 | - ldr r1, =0x00100032 | |
| 151 | - str r1, [r6, #0x010] @ DIRECTCMD | |
| 152 | - | |
| 153 | - /* auto refresh on */ | |
| 154 | - ldr r1, =0xff002030 | |
| 155 | - str r1, [r6, #0x000] @ CONCONTROL | |
| 156 | - | |
| 157 | - /* PwrdnConfig */ | |
| 158 | - ldr r1, =0x00100002 | |
| 159 | - str r1, [r6, #0x028] @ PWRDNCONFIG | |
| 160 | - | |
| 161 | - /* BL%LE %LONG */ | |
| 162 | - ldr r1, =0xff212100 | |
| 163 | - str r1, [r6, #0x004] @ MEMCONTROL | |
| 164 | - | |
| 165 | - | |
| 166 | - /* Try to test memory area */ | |
| 167 | - cmp r4, #0x1 | |
| 168 | - beq 1f | |
| 169 | - | |
| 170 | - mov r4, #0x1 | |
| 171 | - ldr r1, =0x37ffff00 | |
| 172 | - str r4, [r1] | |
| 173 | - str r4, [r1, #0x4] @ dummy write | |
| 174 | - ldr r0, [r1] | |
| 175 | - cmp r0, r4 | |
| 176 | - bne swap_memory | |
| 177 | - | |
| 178 | -1: | |
| 179 | - mov pc, lr | |
| 180 | - | |
| 181 | - .ltorg |
Fork