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Revisionbb50533839e32f1fe97c0c609ddbca3ef8e7ad1f (tree)
Time2019-08-29 22:58:04
AuthorYoshinori Sato <ysato@user...>
CommiterYoshinori Sato

Log Message

ms7619se fix

Change Summary

Incremental Difference

--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -121,6 +121,8 @@ config SANDBOX
121121 config SH
122122 bool "SuperH architecture"
123123 select HAVE_PRIVATE_LIBGCC
124+ select SUPPORT_OF_CONTROL
125+ select CLK
124126
125127 config X86
126128 bool "x86 architecture"
--- a/arch/sh/Kconfig
+++ b/arch/sh/Kconfig
@@ -18,6 +18,10 @@ config CPU_SH4A
1818 bool
1919 select CPU_SH4
2020
21+config CPU_SH7619
22+ bool
23+ select CPU_SH2
24+
2125 config SH_32BIT
2226 bool "32bit mode"
2327 depends on CPU_SH4A
@@ -59,6 +63,10 @@ config TARGET_ESPT
5963 bool "Data Technology ESPT-GIGA board"
6064 select CPU_SH4
6165
66+config TARGET_MS7619SE
67+ bool "SolutionEngine 7619"
68+ select CPU_SH7619
69+
6270 config TARGET_MS7722SE
6371 bool "SolutionEngine 7722"
6472 select CPU_SH4
@@ -147,6 +155,7 @@ source "board/renesas/sh7753evb/Kconfig"
147155 source "board/renesas/sh7757lcr/Kconfig"
148156 source "board/renesas/sh7763rdp/Kconfig"
149157 source "board/renesas/sh7785lcr/Kconfig"
158+source "board/renesas/ms7619se/Kconfig"
150159 source "board/shmin/Kconfig"
151160
152161 endmenu
--- a/arch/sh/cpu/sh2/cpu.c
+++ b/arch/sh/cpu/sh2/cpu.c
@@ -62,7 +62,7 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
6262 return 0;
6363 }
6464
65-#if defined(CONFIG_CPU_SH7619)
65+#if defined(CONFIG_CPU_SH7619) && defined(CONFIG_SH_ETHER)
6666 static void phy_init(void)
6767 {
6868 int i;
@@ -75,12 +75,10 @@ static void phy_init(void)
7575 udelay(200000);
7676 }
7777 #endif
78+
7879 int cpu_eth_init(bd_t *bis)
7980 {
80-#ifdef CONFIG_CPU_SH7619
81+#if defined(CONFIG_CPU_SH7619) && defined(CONFIG_SH_ETHER)
8182 phy_init();
8283 #endif
83-#ifdef CONFIG_SH_ETHER
84- sh_eth_initialize(bis);
85-#endif
8684 }
--- a/arch/sh/cpu/u-boot.lds
+++ b/arch/sh/cpu/u-boot.lds
@@ -25,6 +25,7 @@ ENTRY(_start)
2525
2626 SECTIONS
2727 {
28+ . = CONFIG_SYS_TEXT_BASE;
2829 reloc_dst = .;
2930
3031 PROVIDE (_ftext = .);
@@ -85,4 +86,5 @@ SECTIONS
8586 } >ram
8687 PROVIDE (bss_end = .);
8788 PROVIDE (__bss_end = .);
89+ PROVIDE (_end = .);
8890 }
--- /dev/null
+++ b/arch/sh/dts/Makefile
@@ -0,0 +1,16 @@
1+#
2+# SPDX-License-Identifier: GPL-2.0+
3+#
4+
5+dtb-$(CONFIG_TARGET_MS7619SE) += ms7619se.dtb
6+
7+targets += $(dtb-y)
8+
9+# Add any required device tree compiler flags here
10+DTC_FLAGS +=
11+
12+PHONY += dtbs
13+dtbs: $(addprefix $(obj)/, $(dtb-y))
14+ @:
15+
16+clean-files := *.dtb
--- /dev/null
+++ b/arch/sh/dts/ms7619se.dts
@@ -0,0 +1,91 @@
1+ /dts-v1/;
2+ / {
3+ compatible = "renesas,se7619";
4+ #address-cells = <1>;
5+ #size-cells = <1>;
6+ interrupt-parent = <&shintc>;
7+
8+ chosen {
9+ bootargs = "console=ttySC2,38400";
10+ stdout-path = &sci0;
11+ };
12+ aliases {
13+ serial0 = &sci0;
14+ serial1 = &sci1;
15+ serial2 = &sci2;
16+ };
17+
18+ oclk: oscillator {
19+ #clock-cells = <0>;
20+ compatible = "fixed-clock";
21+ clock-frequency = <31250000>;
22+ clock-output-names = "osc";
23+ };
24+ pllclk: pllclk {
25+ compatible = "renesas,sh7619-pll-clock";
26+ clocks = <&oclk>;
27+ #clock-cells = <0>;
28+ reg = <0xf815ff80 2>, <0xf815ff84 4>;
29+ };
30+ iclk: iclk {
31+ compatible = "fixed-factor-clock";
32+ clocks = <&pllclk>;
33+ #clock-cells = <0>;
34+ clock-div = <1>;
35+ clock-mult = <1>;
36+ };
37+ pclk: pclk {
38+ compatible = "renesas,sh7619-div-clock";
39+ clocks = <&pllclk>;
40+ #clock-cells = <0>;
41+ reg = <0xf815ff80 2>;
42+ };
43+ memory@0c000000 {
44+ device_type = "memory";
45+ reg = <0x0c000000 0x2000000>;
46+ };
47+
48+ cpus {
49+ cpu@0 {
50+ compatible = "renesas,superh";
51+ clock-frequency = <125000000>;
52+ };
53+ };
54+
55+ shintc: interrupt-controller@0 {
56+ compatible = "renesas,sh-intc";
57+ #interrupt-cells = <2>;
58+ interrupt-controller;
59+ };
60+
61+ cmt0: timer@f84a0070 {
62+ compatible = "renesas,cmt-16";
63+ reg = <0xf84a0070 16>;
64+ interrupts = <86 0>, <87 0>;
65+ clocks = <&pclk>;
66+ clock-names = "fck";
67+ renesas,channels-mask = <0x03>;
68+ };
69+
70+ sci0: serial@f8400000 {
71+ compatible = "renesas,scif";
72+ reg = <0xf8400000 0x100>;
73+ interrupts = <88 0>;
74+ clocks = <&pclk>;
75+ clock-names = "sci_ick";
76+ };
77+ sci1: serial@f8410000 {
78+ compatible = "renesas,scif";
79+ reg = <0xf8410000 0x100>;
80+ interrupts = <92 0>;
81+ clocks = <&pclk>;
82+ clock-names = "sci_ick";
83+ };
84+ sci2: serial@f8420000 {
85+ compatible = "renesas,scif";
86+ reg = <0xf8420000 0x100>;
87+ interrupts = <96 0>;
88+ clocks = <&pclk>;
89+ clock-names = "sci_ick";
90+ };
91+ };
\ No newline at end of file
--- /dev/null
+++ b/arch/sh/include/asm/gpio.h
@@ -0,0 +1 @@
1+#include <asm-generic/gpio.h>
--- a/arch/sh/lib/start.S
+++ b/arch/sh/lib/start.S
@@ -13,9 +13,9 @@
1313 .global _start
1414 _start:
1515 #ifdef CONFIG_CPU_SH2
16- .long 0x00000010 /* Ppower ON reset PC*/
16+ .long 0xA0000010 /* Ppower ON reset PC*/
1717 .long 0x00000000
18- .long 0x00000010 /* Manual reset PC */
18+ .long 0xA0000010 /* Manual reset PC */
1919 .long 0x00000000
2020 #endif
2121 mov.l ._lowlevel_init, r0
@@ -35,19 +35,35 @@ _start:
3535 cmp/hs r6, r4
3636 bf 2b
3737
38+ mov.l ._end, r4
39+ mov.l @(4, r5), r6
40+ add r4, r6
41+
42+3: mov.l @r5+, r1
43+ mov.l r1, @r4
44+ add #4, r4
45+ cmp/hs r6, r4
46+ bf 3b
47+
3848 mov.l ._bss_start, r4
3949 mov.l ._bss_end, r5
4050 mov #0, r1
4151
42-3: mov.l r1, @r4 /* bss clear */
52+4: mov.l r1, @r4 /* bss clear */
4353 add #4, r4
4454 cmp/hs r5, r4
45- bf 3b
55+ bf 4b
4656
47- mov.l ._gd_init, r13 /* global data */
48- mov.l ._stack_init, r15 /* stack */
57+ mov.l .board_init_f_alloc_reserve ,r0
58+ jsr @r0
59+ mov.l .base, r4
60+
61+ mov r0, r15
62+ mov.l .board_init_f_init_reserve ,r0
63+ jsr @r0
64+ mov r15, r4
4965
50- mov.l ._sh_generic_init, r0
66+ mov.l .board_init_f, r0
5167 jsr @r0
5268 mov #0, r4
5369
@@ -59,8 +75,10 @@ loop:
5975 ._lowlevel_init: .long (lowlevel_init - (100b + 4))
6076 ._reloc_dst: .long _start
6177 ._reloc_dst_end: .long reloc_dst_end
78+._end: .long _end
6279 ._bss_start: .long bss_start
6380 ._bss_end: .long bss_end
64-._gd_init: .long (_start - GENERATED_GBL_DATA_SIZE)
65-._stack_init: .long (_start - GENERATED_GBL_DATA_SIZE - CONFIG_SYS_MALLOC_LEN - 16)
66-._sh_generic_init: .long board_init_f
81+.base: .long _start - 0x1000
82+.board_init_f: .long board_init_f
83+.board_init_f_alloc_reserve: .long board_init_f_alloc_reserve
84+.board_init_f_init_reserve: .long board_init_f_init_reserve
--- a/arch/sh/lib/time_sh2.c
+++ b/arch/sh/lib/time_sh2.c
@@ -58,10 +58,7 @@ static unsigned long get_usec (void)
5858 else
5959 cmcnt = (CMT_TIMER_RESET - cmcnt) + data;
6060
61- if ((cmt0_timer + cmcnt) > CMT_MAX_COUNTER)
62- cmt0_timer = ((cmt0_timer + cmcnt) - CMT_MAX_COUNTER);
63- else
64- cmt0_timer += cmcnt;
61+ cmt0_timer += cmcnt;
6562
6663 cmcnt = data;
6764 return cmt0_timer;
--- /dev/null
+++ b/board/renesas/ms7619se/Kconfig
@@ -0,0 +1,12 @@
1+if TARGET_MS7619SE
2+
3+config SYS_BOARD
4+ default "ms7619se"
5+
6+config SYS_VENDOR
7+ default "renesas"
8+
9+config SYS_CONFIG_NAME
10+ default "ms7619se"
11+
12+endif
--- a/board/renesas/ms7619se/Makefile
+++ b/board/renesas/ms7619se/Makefile
@@ -7,4 +7,4 @@
77 #
88
99 obj-y := ms7619se.o
10-obj-y += lowlevel_init.o
10+extra-y += lowlevel_init.o
--- a/board/renesas/ms7619se/ms7619se.c
+++ b/board/renesas/ms7619se/ms7619se.c
@@ -110,14 +110,6 @@ int board_init(void)
110110 return 0;
111111 }
112112
113-int dram_init(void)
114-{
115- gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
116- gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
117- printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
118- return 0;
119-}
120-
121113 void led_set_state(unsigned short value)
122114 {
123115 }
--- a/config.mk
+++ b/config.mk
@@ -4,79 +4,8 @@
44 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
55 #########################################################################
66
7-<<<<<<< HEAD
8-# Set shell to bash if possible, otherwise fall back to sh
9-SHELL := $(shell if [ -x "$$BASH" ]; then echo $$BASH; \
10- else if [ -x /bin/bash ]; then echo /bin/bash; \
11- else echo sh; fi; fi)
12-
13-export SHELL
14-
15-ifeq ($(CURDIR),$(SRCTREE))
16-dir :=
17-else
18-dir := $(subst $(SRCTREE)/,,$(CURDIR))
19-endif
20-ifeq ($(CPU),sh2a)
21-CONFIG_STANDALONE_LOAD_ADDR += -m2a-nofpu
22-endif
23-
24-ifneq ($(OBJTREE),$(SRCTREE))
25-# Create object files for SPL in a separate directory
26-ifeq ($(CONFIG_SPL_BUILD),y)
27-ifeq ($(CONFIG_TPL_BUILD),y)
28-obj := $(if $(dir),$(TPLTREE)/$(dir)/,$(TPLTREE)/)
29-else
30-obj := $(if $(dir),$(SPLTREE)/$(dir)/,$(SPLTREE)/)
31-endif
32-else
33-obj := $(if $(dir),$(OBJTREE)/$(dir)/,$(OBJTREE)/)
34-endif
35-src := $(if $(dir),$(SRCTREE)/$(dir)/,$(SRCTREE)/)
36-
37-$(shell mkdir -p $(obj))
38-else
39-# Create object files for SPL in a separate directory
40-ifeq ($(CONFIG_SPL_BUILD),y)
41-ifeq ($(CONFIG_TPL_BUILD),y)
42-obj := $(if $(dir),$(TPLTREE)/$(dir)/,$(TPLTREE)/)
43-else
44-obj := $(if $(dir),$(SPLTREE)/$(dir)/,$(SPLTREE)/)
45-
46-endif
47-$(shell mkdir -p $(obj))
48-else
49-obj :=
50-endif
51-src :=
52-endif
53-
54-# clean the slate ...
55-PLATFORM_RELFLAGS =
56-PLATFORM_CPPFLAGS =
57-PLATFORM_LDFLAGS =
58-
59-#########################################################################
60-
61-HOSTCFLAGS = -Wall -Wstrict-prototypes -O2 -fomit-frame-pointer \
62- $(HOSTCPPFLAGS)
63-HOSTSTRIP = strip
64-
65-#
66-# Mac OS X / Darwin's C preprocessor is Apple specific. It
67-# generates numerous errors and warnings. We want to bypass it
68-# and use GNU C's cpp. To do this we pass the -traditional-cpp
69-# option to the compiler. Note that the -traditional-cpp flag
70-# DOES NOT have the same semantics as GNU C's flag, all it does
71-# is invoke the GNU preprocessor in stock ANSI/ISO C fashion.
72-#
73-# Apple's linker is similar, thanks to the new 2 stage linking
74-# multiple symbol definitions are treated as errors, hence the
75-# -multiply_defined suppress option to turn off this error.
76-=======
777 # This file is included from ./Makefile and spl/Makefile.
788 # Clean the state to avoid the same flags added twice.
79->>>>>>> v2019.01
809 #
8110 # (Tegra needs different flags for SPL.
8211 # That's the reason why this file must be included from spl/Makefile too.
--- a/drivers/net/sh_eth.c
+++ b/drivers/net/sh_eth.c
@@ -376,7 +376,7 @@ static void sh_eth_mac_regs_config(struct sh_eth_dev *eth, unsigned char *mac)
376376
377377 /* Configure e-dmac registers */
378378 #if defined(CONFIG_CPU_SH7619)
379- sh_eth_write(port_info, (sh_eth_read(port)info, EDMR) & ~EMDR_DESC_R) |
379+ sh_eth_write(port_info, (sh_eth_read(port_info, EDMR) & ~EMDR_DESC_R) |
380380 EMDR_DESC, EDMR);
381381 #else
382382 sh_eth_write(port_info, (sh_eth_read(port_info, EDMR) & ~EMDR_DESC_R) |
--- a/drivers/net/sh_eth.h
+++ b/drivers/net/sh_eth.h
@@ -59,7 +59,7 @@ struct tx_desc_s {
5959 u32 td1;
6060 u32 td2; /* Buffer start */
6161 u8 padding[TX_DESC_PADDING]; /* aligned cache line size */
62-} __attribute__((packed));
62+};
6363
6464 /* There is no limitation in the number of rx descriptors */
6565 #define NUM_RX_DESC 8
@@ -76,7 +76,7 @@ struct rx_desc_s {
7676 volatile u32 rd1;
7777 u32 rd2; /* Buffer start */
7878 u8 padding[TX_DESC_PADDING]; /* aligned cache line size */
79-} __attribute__((packed));
79+};
8080
8181 struct sh_eth_info {
8282 struct tx_desc_s *tx_desc_alloc;
@@ -228,6 +228,60 @@ static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
228228 [RMII_MII] = 0x0790,
229229 };
230230
231+static const u16 sh_eth_offset_rz[SH_ETH_MAX_REGISTER_OFFSET] = {
232+ [EDSR] = 0x0000,
233+ [EDMR] = 0x0400,
234+ [EDTRR] = 0x0408,
235+ [EDRRR] = 0x0410,
236+ [EESR] = 0x0428,
237+ [EESIPR] = 0x0430,
238+ [TDLAR] = 0x0010,
239+ [TDFAR] = 0x0014,
240+ [TDFXR] = 0x0018,
241+ [TDFFR] = 0x001c,
242+ [RDLAR] = 0x0030,
243+ [RDFAR] = 0x0034,
244+ [RDFXR] = 0x0038,
245+ [RDFFR] = 0x003c,
246+ [TRSCER] = 0x0438,
247+ [RMFCR] = 0x0440,
248+ [TFTR] = 0x0448,
249+ [FDR] = 0x0450,
250+ [RMCR] = 0x0458,
251+ [RPADIR] = 0x0460,
252+ [FCFTR] = 0x0468,
253+ [CSMR] = 0x04E4,
254+
255+ [ECMR] = 0x0500,
256+ [ECSR] = 0x0510,
257+ [ECSIPR] = 0x0518,
258+ [PIR] = 0x0520,
259+ [PSR] = 0x0528,
260+ [PIPR] = 0x052c,
261+ [RFLR] = 0x0508,
262+ [APR] = 0x0554,
263+ [MPR] = 0x0558,
264+ [PFTCR] = 0x055c,
265+ [PFRCR] = 0x0560,
266+ [TPAUSER] = 0x0564,
267+ [GECMR] = 0x05b0,
268+ [BCULR] = 0x05b4,
269+ [MAHR] = 0x05c0,
270+ [MALR] = 0x05c8,
271+ [TROCR] = 0x0700,
272+ [CDCR] = 0x0708,
273+ [LCCR] = 0x0710,
274+ [CEFCR] = 0x0740,
275+ [FRECR] = 0x0748,
276+ [TSFRCR] = 0x0750,
277+ [TLFRCR] = 0x0758,
278+ [RFCR] = 0x0760,
279+ [CERCR] = 0x0768,
280+ [CEECR] = 0x0770,
281+ [MAFCR] = 0x0778,
282+ [RMII_MII] = 0x0790,
283+};
284+
231285 static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
232286 [ECMR] = 0x0100,
233287 [RFLR] = 0x0108,
@@ -281,50 +335,6 @@ static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
281335 [TDFAR] = 0x00d8,
282336 };
283337
284-static const u16 sh_eth_offset_7619[SH_ETH_MAX_REGISTER_OFFSET] = {
285- [ECMR] = 0x0160,
286- [RFLR] = 0x0178,
287- [ECSR] = 0x0164,
288- [ECSIPR] = 0x0168,
289- [PIR] = 0x016C,
290- [PSR] = 0x017C,
291- [IPGR] = 0x01B4,
292- [APR] = 0x01B8,
293- [MPR] = 0x01BC,
294- [TPAUSER] = 0x01C4,
295- [MAHR] = 0x0170,
296- [MALR] = 0x0174,
297- [TROCR] = 0x01B0,
298- [CDCR] = 0x01B4,
299- [LCCR] = 0x01B8,
300- [CNDCR] = 0x01BC,
301- [CEFCR] = 0x0194,
302- [FRECR] = 0x0198,
303- [TSFRCR] = 0x019C,
304- [TLFRCR] = 0x01A0,
305- [RFCR] = 0x01A4,
306- [MAFCR] = 0x01A8,
307-
308- [EDMR] = 0x0000,
309- [EDTRR] = 0x0004,
310- [EDRRR] = 0x0008,
311- [TDLAR] = 0x000C,
312- [RDLAR] = 0x0010,
313- [EESR] = 0x0014,
314- [EESIPR] = 0x0018,
315- [TRSCER] = 0x001C,
316- [RMFCR] = 0x0020,
317- [TFTR] = 0x0024,
318- [FDR] = 0x0028,
319- [RMCR] = 0x002C,
320- [FCFTR] = 0x0034,
321- [TRIMD] = 0x003C,
322- [RBWAR] = 0x0040,
323- [RDFAR] = 0x0044,
324- [TBRAR] = 0x004C,
325- [TDFAR] = 0x0050,
326-};
327-
328338 /* Register Address */
329339 #if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
330340 #define SH_ETH_TYPE_GETHER
@@ -339,9 +349,6 @@ static const u16 sh_eth_offset_7619[SH_ETH_MAX_REGISTER_OFFSET] = {
339349 #define SH_ETH_TYPE_ETHER
340350 #define BASE_IO_ADDR 0xfef00000
341351 #endif
342-#elif defined(CONFIG_CPU_SH7724)
343-#define SH_ETH_TYPE_ETHER
344-#define BASE_IO_ADDR 0xA4600000
345352 #elif defined(CONFIG_R8A7740)
346353 #define SH_ETH_TYPE_GETHER
347354 #define BASE_IO_ADDR 0xE9A00000
@@ -351,9 +358,6 @@ static const u16 sh_eth_offset_7619[SH_ETH_MAX_REGISTER_OFFSET] = {
351358 #elif defined(CONFIG_R7S72100)
352359 #define SH_ETH_TYPE_RZ
353360 #define BASE_IO_ADDR 0xE8203000
354-#elif defined(CONFIG_CPU_SH7619)
355-#define SH_ETH_TYPE_ETHER
356-#define BASE_IO_ADDR 0xFB000000
357361 #endif
358362
359363 /*
@@ -643,11 +647,7 @@ enum RPADIR_BIT {
643647
644648 /* FDR */
645649 enum FIFO_SIZE_BIT {
646-#if defined(CONFIG_CPU_SH7619)
647- FIFO_SIZE_T = 0x00000100, FIFO_SIZE_R = 0x00000001,
648-#else
649650 FIFO_SIZE_T = 0x00000700, FIFO_SIZE_R = 0x00000007,
650-#endif
651651 };
652652
653653 static inline unsigned long sh_eth_reg_addr(struct sh_eth_info *port,
@@ -655,10 +655,10 @@ static inline unsigned long sh_eth_reg_addr(struct sh_eth_info *port,
655655 {
656656 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
657657 const u16 *reg_offset = sh_eth_offset_gigabit;
658-#elif defined(CONFIG_CPU_SH7619)
659- const u16 *reg_offset = sh_eth_offset_7619;
660658 #elif defined(SH_ETH_TYPE_ETHER)
661659 const u16 *reg_offset = sh_eth_offset_fast_sh4;
660+#elif defined(SH_ETH_TYPE_RZ)
661+ const u16 *reg_offset = sh_eth_offset_rz;
662662 #else
663663 #error
664664 #endif
@@ -668,19 +668,11 @@ static inline unsigned long sh_eth_reg_addr(struct sh_eth_info *port,
668668 static inline void sh_eth_write(struct sh_eth_info *port, unsigned long data,
669669 int enum_index)
670670 {
671-<<<<<<< HEAD
672- __raw_writel(data, sh_eth_reg_addr(eth, enum_index));
673-=======
674671 outl(data, sh_eth_reg_addr(port, enum_index));
675->>>>>>> v2019.01
676672 }
677673
678674 static inline unsigned long sh_eth_read(struct sh_eth_info *port,
679675 int enum_index)
680676 {
681-<<<<<<< HEAD
682- return __raw_readl(sh_eth_reg_addr(eth, enum_index));
683-=======
684677 return inl(sh_eth_reg_addr(port, enum_index));
685->>>>>>> v2019.01
686678 }
--- a/include/configs/ms7619se.h
+++ b/include/configs/ms7619se.h
@@ -1,5 +1,5 @@
11 /*
2- * Configuation settings for the Renesas Technology MS7206SE01
2+ * Configuation settings for the Renesas Technology MS7619SE
33 *
44 * Copyright (C) 2013 Yoshinori Sato <ysato@users.sourceforge.jp>
55 *
@@ -27,20 +27,6 @@
2727
2828 /*#define DEBUG*/
2929 #define CONFIG_SH 1
30-#define CONFIG_SH2 1
31-#define CONFIG_CPU_SH7619 1
32-#define CONFIG_MS7619SE 1
33-
34-#define CONFIG_CMD_FLASH
35-#define CONFIG_CMD_SAVEENV
36-#define CONFIG_CMD_SDRAM
37-#define CONFIG_CMD_MEMORY
38-#define CONFIG_CMD_CACHE
39-#define CONFIG_CMD_LOADS
40-#define CONFIG_CMD_LOADB
41-#define CONFIG_CMD_NET
42-#define CONFIG_CMD_MEMTEST
43-
4430 #define CONFIG_BAUDRATE 38400
4531 #define CONFIG_BOOTARGS "console=ttySC2,38400"
4632 #define CONFIG_LOADADDR 0x0C800000
@@ -49,14 +35,13 @@
4935 #undef CONFIG_SHOW_BOOT_PROGRESS
5036
5137 #define CONFIG_BOARD_LATE_INIT
38+#define CONFIG_LMB
5239
5340 /* MEMORY */
5441 #define MS7619SE_SDRAM_BASE 0x0C000000
5542 #define MS7619SE_FLASH_BASE_1 0xA0000000 /* Non cache */
5643 #define MS7619SE_FLASH_BANK_SIZE (16 * 1024 * 1024)
5744
58-#define CONFIG_SYS_TEXT_BASE 0x0C7C0000
59-#define CONFIG_SYS_LONGHELP /* undef to save memory */
6045 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
6146 #define CONFIG_SYS_CBSIZE 256 /* Buffer size for input from the Console */
6247 #define CONFIG_SYS_PBSIZE 256 /* Buffer size for Console output */
@@ -83,7 +68,6 @@
8368 #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
8469
8570 /* FLASH */
86-#define CONFIG_FLASH_CFI_DRIVER
8771 #define CONFIG_SYS_FLASH_CFI
8872 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
8973 #undef CONFIG_SYS_FLASH_QUIET_TEST
@@ -102,11 +86,11 @@
10286
10387 /* Board Clock */
10488 #define CONFIG_SYS_CLK_FREQ 31250000
105-#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
10689 #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
10790 #define CMT_CLK_DIVIDER 32 /* 8 (default), 32, 128 or 512 */
10891 #define CONFIG_SH_CMT_CLK_FREQ (CONFIG_SYS_CLK_FREQ / CMT_CLK_DIVIDER)
10992
93+#if 0
11094 #define CONFIG_SH_ETHER 1
11195 #define CONFIG_SH_ETHER_USE_PORT 0
11296 #define CONFIG_SH_ETHER_PHY_ADDR 1
@@ -116,6 +100,5 @@
116100 #define CONFIG_BITBANGMII
117101 #define CONFIG_BITBANGMII_MULTI
118102 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII
119-#define CONFIG_PHY_BROKEN_ERCAP
120-
103+#endif
121104 #endif /* __MS7619SE_H */