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Revision86a179703c3b514fffa13aef191f2b86cfc11f8e (tree)
Time2022-07-26 18:29:01
AuthorPeng Fan <peng.fan@nxp....>
CommiterStefano Babic

Log Message

imx: imx93_evk: Add basic board support

Add basic board codes and defconfig for i.MX93 11x11 EVK board.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>

Change Summary

Incremental Difference

--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -971,6 +971,9 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
971971 imx8mq-pico-pi.dtb \
972972 imx8mq-kontron-pitx-imx8m.dtb
973973
974+dtb-$(CONFIG_ARCH_IMX9) += \
975+ imx93-11x11-evk.dtb
976+
974977 dtb-$(CONFIG_ARCH_IMXRT) += imxrt1050-evk.dtb \
975978 imxrt1020-evk.dtb
976979
--- /dev/null
+++ b/arch/arm/dts/imx93-11x11-evk-u-boot.dtsi
@@ -0,0 +1,157 @@
1+// SPDX-License-Identifier: GPL-2.0+
2+/*
3+ * Copyright 2022 NXP
4+ */
5+
6+/ {
7+ wdt-reboot {
8+ compatible = "wdt-reboot";
9+ wdt = <&wdog3>;
10+ u-boot,dm-spl;
11+ };
12+
13+ aliases {
14+ usbgadget0 = &usbg1;
15+ usbgadget1 = &usbg2;
16+ };
17+
18+ usbg1: usbg1 {
19+ compatible = "fsl,imx27-usb-gadget";
20+ dr_mode = "peripheral";
21+ chipidea,usb = <&usbotg1>;
22+ status = "okay";
23+ };
24+
25+ usbg2: usbg2 {
26+ compatible = "fsl,imx27-usb-gadget";
27+ dr_mode = "peripheral";
28+ chipidea,usb = <&usbotg2>;
29+ status = "okay";
30+ };
31+
32+ firmware {
33+ optee {
34+ compatible = "linaro,optee-tz";
35+ method = "smc";
36+ };
37+ };
38+};
39+
40+&{/soc@0} {
41+ u-boot,dm-pre-reloc;
42+ u-boot,dm-spl;
43+};
44+
45+&aips1 {
46+ u-boot,dm-spl;
47+ u-boot,dm-pre-reloc;
48+};
49+
50+&aips2 {
51+ u-boot,dm-spl;
52+};
53+
54+&aips3 {
55+ u-boot,dm-spl;
56+};
57+
58+&iomuxc {
59+ u-boot,dm-spl;
60+};
61+
62+&reg_usdhc2_vmmc {
63+ u-boot,off-on-delay-us = <20000>;
64+ u-boot,dm-spl;
65+};
66+
67+&pinctrl_reg_usdhc2_vmmc {
68+ u-boot,dm-spl;
69+};
70+
71+&pinctrl_uart1 {
72+ u-boot,dm-spl;
73+};
74+
75+&pinctrl_usdhc2_gpio {
76+ u-boot,dm-spl;
77+};
78+
79+&pinctrl_usdhc2 {
80+ u-boot,dm-spl;
81+};
82+
83+&gpio1 {
84+ u-boot,dm-spl;
85+};
86+
87+&gpio2 {
88+ u-boot,dm-spl;
89+};
90+
91+&gpio3 {
92+ u-boot,dm-spl;
93+};
94+
95+&gpio4 {
96+ u-boot,dm-spl;
97+};
98+
99+&lpuart1 {
100+ u-boot,dm-spl;
101+};
102+
103+&usdhc1 {
104+ u-boot,dm-spl;
105+};
106+
107+&usdhc2 {
108+ u-boot,dm-spl;
109+ fsl,signal-voltage-switch-extra-delay-ms = <8>;
110+};
111+
112+&lpi2c2 {
113+ u-boot,dm-spl;
114+};
115+
116+&{/soc@0/bus@44000000/i2c@44350000/pmic@25} {
117+ u-boot,dm-spl;
118+};
119+
120+&{/soc@0/bus@44000000/i2c@44350000/pmic@25/regulators} {
121+ u-boot,dm-spl;
122+};
123+
124+&pinctrl_lpi2c2 {
125+ u-boot,dm-spl;
126+};
127+
128+&fec {
129+ phy-reset-gpios = <&pcal6524 16 GPIO_ACTIVE_LOW>;
130+ phy-reset-duration = <15>;
131+ phy-reset-post-delay = <100>;
132+};
133+
134+&eqos {
135+ compatible = "fsl,imx-eqos";
136+};
137+
138+&ethphy1 {
139+ reset-gpios = <&pcal6524 15 GPIO_ACTIVE_LOW>;
140+ reset-assert-us = <15000>;
141+ reset-deassert-us = <100000>;
142+};
143+
144+&usbotg1 {
145+ status = "okay";
146+ extcon = <&ptn5110>;
147+};
148+
149+&usbotg2 {
150+ status = "okay";
151+ extcon = <&ptn5110_2>;
152+};
153+
154+&s4muap {
155+ u-boot,dm-spl;
156+ status = "okay";
157+};
--- /dev/null
+++ b/arch/arm/dts/imx93-11x11-evk.dts
@@ -0,0 +1,527 @@
1+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2+/*
3+ * Copyright 2021 NXP
4+ */
5+
6+/dts-v1/;
7+
8+#include "imx93.dtsi"
9+
10+/{
11+ chosen {
12+ stdout-path = &lpuart1;
13+ };
14+
15+ reserved-memory {
16+ #address-cells = <2>;
17+ #size-cells = <2>;
18+ ranges;
19+
20+ audio: audio@a4120000 {
21+ compatible = "shared-dma-pool";
22+ reg = <0 0xa4120000 0 0x100000>;
23+ no-map;
24+ };
25+ };
26+
27+ reg_can2_stby: regulator-can2-stby {
28+ compatible = "regulator-fixed";
29+ regulator-name = "can2-stby";
30+ regulator-min-microvolt = <3300000>;
31+ regulator-max-microvolt = <3300000>;
32+ gpio = <&adp5585gpio 5 GPIO_ACTIVE_LOW>;
33+ enable-active-low;
34+ };
35+
36+ reg_usdhc2_vmmc: regulator-usdhc2 {
37+ compatible = "regulator-fixed";
38+ pinctrl-names = "default";
39+ pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
40+ regulator-name = "VSD_3V3";
41+ regulator-min-microvolt = <3300000>;
42+ regulator-max-microvolt = <3300000>;
43+ gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>;
44+ enable-active-high;
45+ };
46+
47+ usdhc3_pwrseq: usdhc3_pwrseq {
48+ compatible = "mmc-pwrseq-simple";
49+ reset-gpios = <&pcal6524 20 GPIO_ACTIVE_LOW>;
50+ };
51+
52+ reg_vref_1v8: regulator-adc-vref {
53+ compatible = "regulator-fixed";
54+ regulator-name = "vref_1v8";
55+ regulator-min-microvolt = <1800000>;
56+ regulator-max-microvolt = <1800000>;
57+ };
58+
59+};
60+
61+&lpi2c1 {
62+ #address-cells = <1>;
63+ #size-cells = <0>;
64+ clock-frequency = <400000>;
65+ pinctrl-names = "default", "sleep";
66+ pinctrl-0 = <&pinctrl_lpi2c1>;
67+ pinctrl-1 = <&pinctrl_lpi2c1>;
68+ status = "okay";
69+
70+ ptn5110: tcpc@50 {
71+ compatible = "nxp,ptn5110";
72+ reg = <0x50>;
73+ interrupt-parent = <&pcal6524>;
74+ interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
75+ status = "okay";
76+
77+ port {
78+ typec1_dr_sw: endpoint {
79+ remote-endpoint = <&usb1_drd_sw>;
80+ };
81+ };
82+
83+ typec1_con: connector {
84+ compatible = "usb-c-connector";
85+ label = "USB-C";
86+ power-role = "dual";
87+ data-role = "dual";
88+ try-power-role = "sink";
89+ source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
90+ sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
91+ PDO_VAR(5000, 20000, 3000)>;
92+ op-sink-microwatt = <15000000>;
93+ self-powered;
94+ };
95+ };
96+
97+ ptn5110_2: tcpc@51 {
98+ compatible = "nxp,ptn5110";
99+ reg = <0x51>;
100+ interrupt-parent = <&pcal6524>;
101+ interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
102+ status = "okay";
103+
104+ port {
105+ typec2_dr_sw: endpoint {
106+ remote-endpoint = <&usb2_drd_sw>;
107+ };
108+ };
109+
110+ typec2_con: connector {
111+ compatible = "usb-c-connector";
112+ label = "USB-C";
113+ power-role = "dual";
114+ data-role = "dual";
115+ try-power-role = "sink";
116+ source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
117+ sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
118+ PDO_VAR(5000, 20000, 3000)>;
119+ op-sink-microwatt = <15000000>;
120+ self-powered;
121+ };
122+ };
123+};
124+
125+&lpi2c2 {
126+ #address-cells = <1>;
127+ #size-cells = <0>;
128+ clock-frequency = <400000>;
129+ pinctrl-names = "default", "sleep";
130+ pinctrl-0 = <&pinctrl_lpi2c2>;
131+ pinctrl-1 = <&pinctrl_lpi2c2>;
132+ status = "okay";
133+
134+ pmic@25 {
135+ compatible = "nxp,pca9451a";
136+ reg = <0x25>;
137+ pinctrl-names = "default";
138+ interrupt-parent = <&pcal6524>;
139+ interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
140+
141+ regulators {
142+ buck1: BUCK1 {
143+ regulator-name = "BUCK1";
144+ regulator-min-microvolt = <600000>;
145+ regulator-max-microvolt = <2187500>;
146+ regulator-boot-on;
147+ regulator-always-on;
148+ regulator-ramp-delay = <3125>;
149+ };
150+
151+ buck2: BUCK2 {
152+ regulator-name = "BUCK2";
153+ regulator-min-microvolt = <600000>;
154+ regulator-max-microvolt = <2187500>;
155+ regulator-boot-on;
156+ regulator-always-on;
157+ regulator-ramp-delay = <3125>;
158+ };
159+
160+ buck4: BUCK4{
161+ regulator-name = "BUCK4";
162+ regulator-min-microvolt = <600000>;
163+ regulator-max-microvolt = <3400000>;
164+ regulator-boot-on;
165+ regulator-always-on;
166+ };
167+
168+ buck5: BUCK5{
169+ regulator-name = "BUCK5";
170+ regulator-min-microvolt = <600000>;
171+ regulator-max-microvolt = <3400000>;
172+ regulator-boot-on;
173+ regulator-always-on;
174+ };
175+
176+ buck6: BUCK6 {
177+ regulator-name = "BUCK6";
178+ regulator-min-microvolt = <600000>;
179+ regulator-max-microvolt = <3400000>;
180+ regulator-boot-on;
181+ regulator-always-on;
182+ };
183+
184+ ldo1: LDO1 {
185+ regulator-name = "LDO1";
186+ regulator-min-microvolt = <1600000>;
187+ regulator-max-microvolt = <3300000>;
188+ regulator-boot-on;
189+ regulator-always-on;
190+ };
191+
192+ ldo2: LDO2 {
193+ regulator-name = "LDO2";
194+ regulator-min-microvolt = <800000>;
195+ regulator-max-microvolt = <1150000>;
196+ regulator-boot-on;
197+ regulator-always-on;
198+ };
199+
200+ ldo3: LDO3 {
201+ regulator-name = "LDO3";
202+ regulator-min-microvolt = <800000>;
203+ regulator-max-microvolt = <3300000>;
204+ regulator-boot-on;
205+ regulator-always-on;
206+ };
207+
208+ ldo4: LDO4 {
209+ regulator-name = "LDO4";
210+ regulator-min-microvolt = <800000>;
211+ regulator-max-microvolt = <3300000>;
212+ regulator-boot-on;
213+ regulator-always-on;
214+ };
215+
216+ ldo5: LDO5 {
217+ regulator-name = "LDO5";
218+ regulator-min-microvolt = <1800000>;
219+ regulator-max-microvolt = <3300000>;
220+ regulator-boot-on;
221+ regulator-always-on;
222+ };
223+ };
224+ };
225+
226+ pcal6524: gpio@22 {
227+ compatible = "nxp,pcal6524";
228+ pinctrl-names = "default";
229+ pinctrl-0 = <&pinctrl_pcal6524>;
230+ reg = <0x22>;
231+ gpio-controller;
232+ #gpio-cells = <2>;
233+ interrupt-controller;
234+ #interrupt-cells = <2>;
235+ interrupt-parent = <&gpio3>;
236+ interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
237+ };
238+
239+ adp5585gpio: gpio@34 {
240+ compatible = "adp5585";
241+ reg = <0x34>;
242+ gpio-controller;
243+ #gpio-cells = <2>;
244+ };
245+};
246+
247+&lpuart1 { /* console */
248+ pinctrl-names = "default";
249+ pinctrl-0 = <&pinctrl_uart1>;
250+ status = "okay";
251+};
252+
253+&lpuart2 {
254+ pinctrl-names = "default";
255+ pinctrl-0 = <&pinctrl_uart2>;
256+ status = "disabled";
257+};
258+
259+&usbotg1 {
260+ dr_mode = "otg";
261+ hnp-disable;
262+ srp-disable;
263+ adp-disable;
264+ usb-role-switch;
265+ disable-over-current;
266+ samsung,picophy-pre-emp-curr-control = <3>;
267+ samsung,picophy-dc-vol-level-adjust = <7>;
268+ status = "okay";
269+
270+ port {
271+ usb1_drd_sw: endpoint {
272+ remote-endpoint = <&typec1_dr_sw>;
273+ };
274+ };
275+};
276+
277+&usbotg2 {
278+ dr_mode = "otg";
279+ hnp-disable;
280+ srp-disable;
281+ adp-disable;
282+ usb-role-switch;
283+ disable-over-current;
284+ samsung,picophy-pre-emp-curr-control = <3>;
285+ samsung,picophy-dc-vol-level-adjust = <7>;
286+ status = "okay";
287+
288+ port {
289+ usb2_drd_sw: endpoint {
290+ remote-endpoint = <&typec2_dr_sw>;
291+ };
292+ };
293+};
294+
295+&usdhc1 {
296+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
297+ pinctrl-0 = <&pinctrl_usdhc1>;
298+ pinctrl-1 = <&pinctrl_usdhc1>;
299+ pinctrl-2 = <&pinctrl_usdhc1>;
300+ bus-width = <8>;
301+ non-removable;
302+ status = "okay";
303+};
304+
305+&usdhc2 {
306+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
307+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
308+ pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
309+ pinctrl-2 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
310+ cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>;
311+ vmmc-supply = <&reg_usdhc2_vmmc>;
312+ bus-width = <4>;
313+ status = "okay";
314+ no-sdio;
315+ no-mmc;
316+};
317+
318+&usdhc3 {
319+ status = "disabled";
320+};
321+
322+&fec {
323+ pinctrl-names = "default";
324+ pinctrl-0 = <&pinctrl_fec>;
325+ phy-mode = "rgmii-id";
326+ phy-handle = <&ethphy2>;
327+ fsl,magic-packet;
328+ status = "okay";
329+
330+ mdio {
331+ #address-cells = <1>;
332+ #size-cells = <0>;
333+ clock-frequency = <5000000>;
334+
335+ ethphy2: ethernet-phy@2 {
336+ compatible = "ethernet-phy-ieee802.3-c22";
337+ reg = <2>;
338+ eee-broken-1000t;
339+ rtl821x,aldps-disable;
340+ rtl821x,clkout-disable;
341+ };
342+ };
343+};
344+
345+&eqos {
346+ pinctrl-names = "default";
347+ pinctrl-0 = <&pinctrl_eqos>;
348+ phy-mode = "rgmii-id";
349+ phy-handle = <&ethphy1>;
350+ status = "okay";
351+
352+ mdio {
353+ compatible = "snps,dwmac-mdio";
354+ #address-cells = <1>;
355+ #size-cells = <0>;
356+ clock-frequency = <5000000>;
357+
358+ ethphy1: ethernet-phy@1 {
359+ compatible = "ethernet-phy-ieee802.3-c22";
360+ reg = <1>;
361+ eee-broken-1000t;
362+ rtl821x,aldps-disable;
363+ rtl821x,clkout-disable;
364+ };
365+ };
366+};
367+
368+&flexspi {
369+ pinctrl-names = "default";
370+ pinctrl-0 = <&pinctrl_flexspi>;
371+ status = "disabled";
372+
373+ flash0: flash@0 {
374+ reg = <0>;
375+ #address-cells = <1>;
376+ #size-cells = <1>;
377+ compatible = "jedec,spi-nor";
378+ spi-max-frequency = <80000000>;
379+ spi-tx-bus-width = <1>;
380+ spi-rx-bus-width = <1>;
381+ };
382+};
383+
384+&iomuxc {
385+ pinctrl-names = "default";
386+ status = "okay";
387+
388+ pinctrl_flexcan2: flexcan2grp {
389+ fsl,pins = <
390+ MX93_PAD_GPIO_IO25__CAN2_TX 0x139e
391+ MX93_PAD_GPIO_IO27__CAN2_RX 0x139e
392+ >;
393+ };
394+
395+ pinctrl_flexspi: flexspigrp {
396+ fsl,pins = <
397+ MX93_PAD_SD3_CMD__FLEXSPI1_A_SS0_B 0x42
398+ MX93_PAD_SD1_DATA3__FLEXSPI1_A_SS1_B 0x42
399+ MX93_PAD_SD3_CLK__FLEXSPI1_A_SCLK 0x42
400+ MX93_PAD_SD1_STROBE__FLEXSPI1_A_DQS 0x42
401+ MX93_PAD_SD3_DATA0__FLEXSPI1_A_DATA00 0x42
402+ MX93_PAD_SD3_DATA1__FLEXSPI1_A_DATA01 0x42
403+ MX93_PAD_SD3_DATA2__FLEXSPI1_A_DATA02 0x42
404+ MX93_PAD_SD3_DATA3__FLEXSPI1_A_DATA03 0x42
405+ MX93_PAD_SD1_DATA4__FLEXSPI1_A_DATA04 0x42
406+ MX93_PAD_SD1_DATA5__FLEXSPI1_A_DATA05 0x42
407+ MX93_PAD_SD1_DATA6__FLEXSPI1_A_DATA06 0x42
408+ MX93_PAD_SD1_DATA7__FLEXSPI1_A_DATA07 0x42
409+ >;
410+ };
411+
412+ pinctrl_fec: fecgrp {
413+ fsl,pins = <
414+ MX93_PAD_ENET2_MDC__ENET1_MDC 0x57e
415+ MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x57e
416+ MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x57e
417+ MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x57e
418+ MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2 0x57e
419+ MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3 0x57e
420+ MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC 0x5fe
421+ MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x57e
422+ MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x57e
423+ MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x57e
424+ MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2 0x57e
425+ MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3 0x57e
426+ MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC 0x5fe
427+ MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x57e
428+ >;
429+ };
430+
431+ pinctrl_eqos: eqosgrp {
432+ fsl,pins = <
433+ MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x57e
434+ MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e
435+ MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e
436+ MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e
437+ MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e
438+ MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e
439+ MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x5fe
440+ MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e
441+ MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e
442+ MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x57e
443+ MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x57e
444+ MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x57e
445+ MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x5fe
446+ MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e
447+ >;
448+ };
449+
450+ pinctrl_lpi2c1: lpi2c1grp {
451+ fsl,pins = <
452+ MX93_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e
453+ MX93_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e
454+ >;
455+ };
456+
457+ pinctrl_lpi2c2: lpi2c2grp {
458+ fsl,pins = <
459+ MX93_PAD_I2C2_SCL__LPI2C2_SCL 0x40000b9e
460+ MX93_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e
461+ >;
462+ };
463+
464+ pinctrl_pcal6524: pcal6524grp {
465+ fsl,pins = <
466+ MX93_PAD_CCM_CLKO2__GPIO3_IO27 0x31e
467+ >;
468+ };
469+
470+ pinctrl_uart1: uart1grp {
471+ fsl,pins = <
472+ MX93_PAD_UART1_RXD__LPUART1_RX 0x31e
473+ MX93_PAD_UART1_TXD__LPUART1_TX 0x31e
474+ >;
475+ };
476+
477+ pinctrl_uart2: uart2grp {
478+ fsl,pins = <
479+ MX93_PAD_UART2_TXD__LPUART2_TX 0x31e
480+ MX93_PAD_UART2_RXD__LPUART2_RX 0x31e
481+ >;
482+ };
483+
484+ pinctrl_usdhc1: usdhc1grp {
485+ fsl,pins = <
486+ MX93_PAD_SD1_CLK__USDHC1_CLK 0x17fe
487+ MX93_PAD_SD1_CMD__USDHC1_CMD 0x13fe
488+ MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe
489+ MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe
490+ MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe
491+ MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe
492+ MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe
493+ MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe
494+ MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe
495+ MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe
496+ MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x17fe
497+ >;
498+ };
499+
500+ pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
501+ fsl,pins = <
502+ MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x31e
503+ >;
504+ };
505+
506+ pinctrl_usdhc2_gpio: usdhc2gpiogrp {
507+ fsl,pins = <
508+ MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e
509+ >;
510+ };
511+
512+ pinctrl_usdhc2: usdhc2grp {
513+ fsl,pins = <
514+ MX93_PAD_SD2_CLK__USDHC2_CLK 0x17fe
515+ MX93_PAD_SD2_CMD__USDHC2_CMD 0x13fe
516+ MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe
517+ MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe
518+ MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe
519+ MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe
520+ MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
521+ >;
522+ };
523+};
524+
525+&wdog3 {
526+ status = "okay";
527+};
--- a/arch/arm/mach-imx/imx9/Kconfig
+++ b/arch/arm/mach-imx/imx9/Kconfig
@@ -18,4 +18,17 @@ config IMX93
1818 config SYS_SOC
1919 default "imx9"
2020
21+choice
22+ prompt "NXP i.MX9 board select"
23+ optional
24+
25+config TARGET_IMX93_11X11_EVK
26+ bool "imx93_11x11_evk"
27+ select IMX93
28+
29+endchoice
30+
31+source "board/freescale/imx93_evk/Kconfig"
32+
2133 endif
34+
--- a/board/freescale/common/Makefile
+++ b/board/freescale/common/Makefile
@@ -65,7 +65,7 @@ obj-$(CONFIG_ZM7300) += zm7300.o
6565 obj-$(CONFIG_POWER_PFUZE100) += pfuze.o
6666 obj-$(CONFIG_DM_PMIC_PFUZE100) += pfuze.o
6767 obj-$(CONFIG_POWER_MC34VR500) += mc34vr500.o
68-ifneq (,$(filter $(SOC), imx8ulp))
68+ifneq (,$(filter $(SOC), imx8ulp imx9))
6969 obj-y += mmc.o
7070 endif
7171
--- /dev/null
+++ b/board/freescale/imx93_evk/Kconfig
@@ -0,0 +1,19 @@
1+if TARGET_IMX93_11X11_EVK
2+
3+config SYS_BOARD
4+ default "imx93_evk"
5+
6+config SYS_VENDOR
7+ default "freescale"
8+
9+config SYS_CONFIG_NAME
10+ default "imx93_evk"
11+
12+config IMX93_EVK_LPDDR4X
13+ bool "Using LPDDR4X Timing and PMIC voltage"
14+ default y
15+ select IMX9_LPDDR4X
16+ help
17+ Select the LPDDR4X timing and 0.6V VDDQ
18+
19+endif
--- /dev/null
+++ b/board/freescale/imx93_evk/MAINTAINERS
@@ -0,0 +1,6 @@
1+i.MX93 MEK BOARD
2+M: Peng Fan <peng.fan@nxp.com>
3+S: Maintained
4+F: board/freescale/imx93_evk/
5+F: include/configs/imx93_evk.h
6+F: configs/imx93_11x11_evk_defconfig
--- /dev/null
+++ b/board/freescale/imx93_evk/Makefile
@@ -0,0 +1,12 @@
1+#
2+# Copyright 2022 NXP
3+#
4+# SPDX-License-Identifier: GPL-2.0+
5+#
6+
7+obj-y += imx93_evk.o
8+
9+ifdef CONFIG_SPL_BUILD
10+obj-y += spl.o
11+obj-$(CONFIG_IMX93_EVK_LPDDR4X) += lpddr4x_timing.o
12+endif
--- /dev/null
+++ b/board/freescale/imx93_evk/imx93_evk.c
@@ -0,0 +1,57 @@
1+// SPDX-License-Identifier: GPL-2.0+
2+/*
3+ * Copyright 2022 NXP
4+ */
5+
6+#include <common.h>
7+#include <env.h>
8+#include <init.h>
9+#include <miiphy.h>
10+#include <netdev.h>
11+#include <asm/global_data.h>
12+#include <asm/arch-imx9/ccm_regs.h>
13+#include <asm/arch/sys_proto.h>
14+#include <asm/arch-imx9/imx93_pins.h>
15+#include <asm/arch/clock.h>
16+#include <power/pmic.h>
17+#include <dm/device.h>
18+#include <dm/uclass.h>
19+#include <usb.h>
20+#include <dwc3-uboot.h>
21+
22+DECLARE_GLOBAL_DATA_PTR;
23+
24+#define UART_PAD_CTRL (PAD_CTL_DSE(6) | PAD_CTL_FSEL2)
25+#define WDOG_PAD_CTRL (PAD_CTL_DSE(6) | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
26+
27+static iomux_v3_cfg_t const uart_pads[] = {
28+ MX93_PAD_UART1_RXD__LPUART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
29+ MX93_PAD_UART1_TXD__LPUART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
30+};
31+
32+int board_early_init_f(void)
33+{
34+ imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
35+
36+ init_uart_clk(LPUART1_CLK_ROOT);
37+
38+ return 0;
39+}
40+
41+int board_init(void)
42+{
43+ return 0;
44+}
45+
46+int board_late_init(void)
47+{
48+#ifdef CONFIG_ENV_IS_IN_MMC
49+ board_late_mmc_env_init();
50+#endif
51+
52+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
53+ env_set("board_name", "11X11_EVK");
54+ env_set("board_rev", "iMX93");
55+#endif
56+ return 0;
57+}
--- /dev/null
+++ b/board/freescale/imx93_evk/lpddr4x_timing.c
@@ -0,0 +1,1485 @@
1+// SPDX-License-Identifier: GPL-2.0+
2+/*
3+ * Copyright 2022 NXP
4+ *
5+ * Generated code from NXP_DDR_tool
6+ *
7+ * Align with uboot version:
8+ * imx_v2019.04_5.4.x and above version
9+ */
10+
11+#include <linux/kernel.h>
12+#include <asm/arch/ddr.h>
13+
14+struct dram_cfg_param ddr_ddrc_cfg[] = {
15+ /** Initialize DDRC registers **/
16+ { 0x4e300110, 0x44140001 },
17+ { 0x4e300000, 0x8000ff },
18+ { 0x4e300008, 0x0 },
19+ { 0x4e300080, 0x80000512 },
20+ { 0x4e300084, 0x0 },
21+ { 0x4e300114, 0x2 },
22+ { 0x4e300260, 0x0 },
23+ { 0x4e30017c, 0x0 },
24+ { 0x4e300104, 0xaaee001b },
25+ { 0x4e300108, 0x626ee273 },
26+ { 0x4e30010c, 0x5c18b },
27+ { 0x4e300100, 0x25ab321b },
28+ { 0x4e300160, 0x9002 },
29+ { 0x4e30016c, 0x35f00000 },
30+ { 0x4e300250, 0x2b },
31+ { 0x4e300254, 0x0 },
32+ { 0x4e30025c, 0x400 },
33+ { 0x4e300300, 0x16291314 },
34+ { 0x4e300304, 0x163110c },
35+ { 0x4e300308, 0xa200e3c },
36+ { 0x4e300170, 0x8b0b0608 },
37+ { 0x4e300124, 0x1c77071d },
38+ { 0x4e300f04, 0x80 },
39+};
40+
41+/* PHY Initialize Configuration */
42+struct dram_cfg_param ddr_ddrphy_cfg[] = {
43+ { 0x100a0, 0x4 },
44+ { 0x100a1, 0x5 },
45+ { 0x100a2, 0x6 },
46+ { 0x100a3, 0x7 },
47+ { 0x100a4, 0x0 },
48+ { 0x100a5, 0x1 },
49+ { 0x100a6, 0x2 },
50+ { 0x100a7, 0x3 },
51+ { 0x110a0, 0x3 },
52+ { 0x110a1, 0x2 },
53+ { 0x110a2, 0x0 },
54+ { 0x110a3, 0x1 },
55+ { 0x110a4, 0x7 },
56+ { 0x110a5, 0x6 },
57+ { 0x110a6, 0x4 },
58+ { 0x110a7, 0x5 },
59+ { 0x1005f, 0x5ff },
60+ { 0x1015f, 0x5ff },
61+ { 0x1105f, 0x5ff },
62+ { 0x1115f, 0x5ff },
63+ { 0x55, 0x1ff },
64+ { 0x1055, 0x1ff },
65+ { 0x2055, 0x1ff },
66+ { 0x200c5, 0x19 },
67+ { 0x2002e, 0x2 },
68+ { 0x90204, 0x0 },
69+ { 0x20024, 0x1e3 },
70+ { 0x2003a, 0x2 },
71+ { 0x2007d, 0x212 },
72+ { 0x2007c, 0x61 },
73+ { 0x20056, 0x3 },
74+ { 0x1004d, 0xe00 },
75+ { 0x1014d, 0xe00 },
76+ { 0x1104d, 0xe00 },
77+ { 0x1114d, 0xe00 },
78+ { 0x10049, 0xe00 },
79+ { 0x10149, 0xe00 },
80+ { 0x11049, 0xe00 },
81+ { 0x11149, 0xe00 },
82+ { 0x43, 0x60 },
83+ { 0x1043, 0x60 },
84+ { 0x2043, 0x60 },
85+ { 0x20018, 0x1 },
86+ { 0x20075, 0x4 },
87+ { 0x20050, 0x0 },
88+ { 0x2009b, 0x2 },
89+ { 0x20008, 0x3a5 },
90+ { 0x20088, 0x9 },
91+ { 0x200b2, 0x10c },
92+ { 0x10043, 0x5a1 },
93+ { 0x10143, 0x5a1 },
94+ { 0x11043, 0x5a1 },
95+ { 0x11143, 0x5a1 },
96+ { 0x200fa, 0x2 },
97+ { 0x20019, 0x1 },
98+ { 0x200f0, 0x0 },
99+ { 0x200f1, 0x0 },
100+ { 0x200f2, 0x4444 },
101+ { 0x200f3, 0x8888 },
102+ { 0x200f4, 0x5555 },
103+ { 0x200f5, 0x0 },
104+ { 0x200f6, 0x0 },
105+ { 0x200f7, 0xf000 },
106+ { 0x1004a, 0x500 },
107+ { 0x1104a, 0x500 },
108+ { 0x20025, 0x0 },
109+ { 0x2002d, 0x0 },
110+ { 0x20021, 0x0 },
111+ { 0x2002c, 0x0 },
112+};
113+
114+/* ddr phy trained csr */
115+struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
116+ { 0x200b2, 0x0 },
117+ { 0x1200b2, 0x0 },
118+ { 0x2200b2, 0x0 },
119+ { 0x200cb, 0x0 },
120+ { 0x10043, 0x0 },
121+ { 0x110043, 0x0 },
122+ { 0x210043, 0x0 },
123+ { 0x10143, 0x0 },
124+ { 0x110143, 0x0 },
125+ { 0x210143, 0x0 },
126+ { 0x11043, 0x0 },
127+ { 0x111043, 0x0 },
128+ { 0x211043, 0x0 },
129+ { 0x11143, 0x0 },
130+ { 0x111143, 0x0 },
131+ { 0x211143, 0x0 },
132+ { 0x12043, 0x0 },
133+ { 0x112043, 0x0 },
134+ { 0x212043, 0x0 },
135+ { 0x12143, 0x0 },
136+ { 0x112143, 0x0 },
137+ { 0x212143, 0x0 },
138+ { 0x13043, 0x0 },
139+ { 0x113043, 0x0 },
140+ { 0x213043, 0x0 },
141+ { 0x13143, 0x0 },
142+ { 0x113143, 0x0 },
143+ { 0x213143, 0x0 },
144+ { 0x80, 0x0 },
145+ { 0x100080, 0x0 },
146+ { 0x200080, 0x0 },
147+ { 0x1080, 0x0 },
148+ { 0x101080, 0x0 },
149+ { 0x201080, 0x0 },
150+ { 0x2080, 0x0 },
151+ { 0x102080, 0x0 },
152+ { 0x202080, 0x0 },
153+ { 0x3080, 0x0 },
154+ { 0x103080, 0x0 },
155+ { 0x203080, 0x0 },
156+ { 0x4080, 0x0 },
157+ { 0x104080, 0x0 },
158+ { 0x204080, 0x0 },
159+ { 0x5080, 0x0 },
160+ { 0x105080, 0x0 },
161+ { 0x205080, 0x0 },
162+ { 0x6080, 0x0 },
163+ { 0x106080, 0x0 },
164+ { 0x206080, 0x0 },
165+ { 0x7080, 0x0 },
166+ { 0x107080, 0x0 },
167+ { 0x207080, 0x0 },
168+ { 0x8080, 0x0 },
169+ { 0x108080, 0x0 },
170+ { 0x208080, 0x0 },
171+ { 0x9080, 0x0 },
172+ { 0x109080, 0x0 },
173+ { 0x209080, 0x0 },
174+ { 0x10080, 0x0 },
175+ { 0x110080, 0x0 },
176+ { 0x210080, 0x0 },
177+ { 0x10180, 0x0 },
178+ { 0x110180, 0x0 },
179+ { 0x210180, 0x0 },
180+ { 0x11080, 0x0 },
181+ { 0x111080, 0x0 },
182+ { 0x211080, 0x0 },
183+ { 0x11180, 0x0 },
184+ { 0x111180, 0x0 },
185+ { 0x211180, 0x0 },
186+ { 0x12080, 0x0 },
187+ { 0x112080, 0x0 },
188+ { 0x212080, 0x0 },
189+ { 0x12180, 0x0 },
190+ { 0x112180, 0x0 },
191+ { 0x212180, 0x0 },
192+ { 0x13080, 0x0 },
193+ { 0x113080, 0x0 },
194+ { 0x213080, 0x0 },
195+ { 0x13180, 0x0 },
196+ { 0x113180, 0x0 },
197+ { 0x213180, 0x0 },
198+ { 0x10081, 0x0 },
199+ { 0x110081, 0x0 },
200+ { 0x210081, 0x0 },
201+ { 0x10181, 0x0 },
202+ { 0x110181, 0x0 },
203+ { 0x210181, 0x0 },
204+ { 0x11081, 0x0 },
205+ { 0x111081, 0x0 },
206+ { 0x211081, 0x0 },
207+ { 0x11181, 0x0 },
208+ { 0x111181, 0x0 },
209+ { 0x211181, 0x0 },
210+ { 0x12081, 0x0 },
211+ { 0x112081, 0x0 },
212+ { 0x212081, 0x0 },
213+ { 0x12181, 0x0 },
214+ { 0x112181, 0x0 },
215+ { 0x212181, 0x0 },
216+ { 0x13081, 0x0 },
217+ { 0x113081, 0x0 },
218+ { 0x213081, 0x0 },
219+ { 0x13181, 0x0 },
220+ { 0x113181, 0x0 },
221+ { 0x213181, 0x0 },
222+ { 0x100d0, 0x0 },
223+ { 0x1100d0, 0x0 },
224+ { 0x2100d0, 0x0 },
225+ { 0x101d0, 0x0 },
226+ { 0x1101d0, 0x0 },
227+ { 0x2101d0, 0x0 },
228+ { 0x110d0, 0x0 },
229+ { 0x1110d0, 0x0 },
230+ { 0x2110d0, 0x0 },
231+ { 0x111d0, 0x0 },
232+ { 0x1111d0, 0x0 },
233+ { 0x2111d0, 0x0 },
234+ { 0x120d0, 0x0 },
235+ { 0x1120d0, 0x0 },
236+ { 0x2120d0, 0x0 },
237+ { 0x121d0, 0x0 },
238+ { 0x1121d0, 0x0 },
239+ { 0x2121d0, 0x0 },
240+ { 0x130d0, 0x0 },
241+ { 0x1130d0, 0x0 },
242+ { 0x2130d0, 0x0 },
243+ { 0x131d0, 0x0 },
244+ { 0x1131d0, 0x0 },
245+ { 0x2131d0, 0x0 },
246+ { 0x100d1, 0x0 },
247+ { 0x1100d1, 0x0 },
248+ { 0x2100d1, 0x0 },
249+ { 0x101d1, 0x0 },
250+ { 0x1101d1, 0x0 },
251+ { 0x2101d1, 0x0 },
252+ { 0x110d1, 0x0 },
253+ { 0x1110d1, 0x0 },
254+ { 0x2110d1, 0x0 },
255+ { 0x111d1, 0x0 },
256+ { 0x1111d1, 0x0 },
257+ { 0x2111d1, 0x0 },
258+ { 0x120d1, 0x0 },
259+ { 0x1120d1, 0x0 },
260+ { 0x2120d1, 0x0 },
261+ { 0x121d1, 0x0 },
262+ { 0x1121d1, 0x0 },
263+ { 0x2121d1, 0x0 },
264+ { 0x130d1, 0x0 },
265+ { 0x1130d1, 0x0 },
266+ { 0x2130d1, 0x0 },
267+ { 0x131d1, 0x0 },
268+ { 0x1131d1, 0x0 },
269+ { 0x2131d1, 0x0 },
270+ { 0x10068, 0x0 },
271+ { 0x10168, 0x0 },
272+ { 0x10268, 0x0 },
273+ { 0x10368, 0x0 },
274+ { 0x10468, 0x0 },
275+ { 0x10568, 0x0 },
276+ { 0x10668, 0x0 },
277+ { 0x10768, 0x0 },
278+ { 0x10868, 0x0 },
279+ { 0x11068, 0x0 },
280+ { 0x11168, 0x0 },
281+ { 0x11268, 0x0 },
282+ { 0x11368, 0x0 },
283+ { 0x11468, 0x0 },
284+ { 0x11568, 0x0 },
285+ { 0x11668, 0x0 },
286+ { 0x11768, 0x0 },
287+ { 0x11868, 0x0 },
288+ { 0x12068, 0x0 },
289+ { 0x12168, 0x0 },
290+ { 0x12268, 0x0 },
291+ { 0x12368, 0x0 },
292+ { 0x12468, 0x0 },
293+ { 0x12568, 0x0 },
294+ { 0x12668, 0x0 },
295+ { 0x12768, 0x0 },
296+ { 0x12868, 0x0 },
297+ { 0x13068, 0x0 },
298+ { 0x13168, 0x0 },
299+ { 0x13268, 0x0 },
300+ { 0x13368, 0x0 },
301+ { 0x13468, 0x0 },
302+ { 0x13568, 0x0 },
303+ { 0x13668, 0x0 },
304+ { 0x13768, 0x0 },
305+ { 0x13868, 0x0 },
306+ { 0x10069, 0x0 },
307+ { 0x10169, 0x0 },
308+ { 0x10269, 0x0 },
309+ { 0x10369, 0x0 },
310+ { 0x10469, 0x0 },
311+ { 0x10569, 0x0 },
312+ { 0x10669, 0x0 },
313+ { 0x10769, 0x0 },
314+ { 0x10869, 0x0 },
315+ { 0x11069, 0x0 },
316+ { 0x11169, 0x0 },
317+ { 0x11269, 0x0 },
318+ { 0x11369, 0x0 },
319+ { 0x11469, 0x0 },
320+ { 0x11569, 0x0 },
321+ { 0x11669, 0x0 },
322+ { 0x11769, 0x0 },
323+ { 0x11869, 0x0 },
324+ { 0x12069, 0x0 },
325+ { 0x12169, 0x0 },
326+ { 0x12269, 0x0 },
327+ { 0x12369, 0x0 },
328+ { 0x12469, 0x0 },
329+ { 0x12569, 0x0 },
330+ { 0x12669, 0x0 },
331+ { 0x12769, 0x0 },
332+ { 0x12869, 0x0 },
333+ { 0x13069, 0x0 },
334+ { 0x13169, 0x0 },
335+ { 0x13269, 0x0 },
336+ { 0x13369, 0x0 },
337+ { 0x13469, 0x0 },
338+ { 0x13569, 0x0 },
339+ { 0x13669, 0x0 },
340+ { 0x13769, 0x0 },
341+ { 0x13869, 0x0 },
342+ { 0x1008c, 0x0 },
343+ { 0x11008c, 0x0 },
344+ { 0x21008c, 0x0 },
345+ { 0x1018c, 0x0 },
346+ { 0x11018c, 0x0 },
347+ { 0x21018c, 0x0 },
348+ { 0x1108c, 0x0 },
349+ { 0x11108c, 0x0 },
350+ { 0x21108c, 0x0 },
351+ { 0x1118c, 0x0 },
352+ { 0x11118c, 0x0 },
353+ { 0x21118c, 0x0 },
354+ { 0x1208c, 0x0 },
355+ { 0x11208c, 0x0 },
356+ { 0x21208c, 0x0 },
357+ { 0x1218c, 0x0 },
358+ { 0x11218c, 0x0 },
359+ { 0x21218c, 0x0 },
360+ { 0x1308c, 0x0 },
361+ { 0x11308c, 0x0 },
362+ { 0x21308c, 0x0 },
363+ { 0x1318c, 0x0 },
364+ { 0x11318c, 0x0 },
365+ { 0x21318c, 0x0 },
366+ { 0x1008d, 0x0 },
367+ { 0x11008d, 0x0 },
368+ { 0x21008d, 0x0 },
369+ { 0x1018d, 0x0 },
370+ { 0x11018d, 0x0 },
371+ { 0x21018d, 0x0 },
372+ { 0x1108d, 0x0 },
373+ { 0x11108d, 0x0 },
374+ { 0x21108d, 0x0 },
375+ { 0x1118d, 0x0 },
376+ { 0x11118d, 0x0 },
377+ { 0x21118d, 0x0 },
378+ { 0x1208d, 0x0 },
379+ { 0x11208d, 0x0 },
380+ { 0x21208d, 0x0 },
381+ { 0x1218d, 0x0 },
382+ { 0x11218d, 0x0 },
383+ { 0x21218d, 0x0 },
384+ { 0x1308d, 0x0 },
385+ { 0x11308d, 0x0 },
386+ { 0x21308d, 0x0 },
387+ { 0x1318d, 0x0 },
388+ { 0x11318d, 0x0 },
389+ { 0x21318d, 0x0 },
390+ { 0x100c0, 0x0 },
391+ { 0x1100c0, 0x0 },
392+ { 0x2100c0, 0x0 },
393+ { 0x101c0, 0x0 },
394+ { 0x1101c0, 0x0 },
395+ { 0x2101c0, 0x0 },
396+ { 0x102c0, 0x0 },
397+ { 0x1102c0, 0x0 },
398+ { 0x2102c0, 0x0 },
399+ { 0x103c0, 0x0 },
400+ { 0x1103c0, 0x0 },
401+ { 0x2103c0, 0x0 },
402+ { 0x104c0, 0x0 },
403+ { 0x1104c0, 0x0 },
404+ { 0x2104c0, 0x0 },
405+ { 0x105c0, 0x0 },
406+ { 0x1105c0, 0x0 },
407+ { 0x2105c0, 0x0 },
408+ { 0x106c0, 0x0 },
409+ { 0x1106c0, 0x0 },
410+ { 0x2106c0, 0x0 },
411+ { 0x107c0, 0x0 },
412+ { 0x1107c0, 0x0 },
413+ { 0x2107c0, 0x0 },
414+ { 0x108c0, 0x0 },
415+ { 0x1108c0, 0x0 },
416+ { 0x2108c0, 0x0 },
417+ { 0x110c0, 0x0 },
418+ { 0x1110c0, 0x0 },
419+ { 0x2110c0, 0x0 },
420+ { 0x111c0, 0x0 },
421+ { 0x1111c0, 0x0 },
422+ { 0x2111c0, 0x0 },
423+ { 0x112c0, 0x0 },
424+ { 0x1112c0, 0x0 },
425+ { 0x2112c0, 0x0 },
426+ { 0x113c0, 0x0 },
427+ { 0x1113c0, 0x0 },
428+ { 0x2113c0, 0x0 },
429+ { 0x114c0, 0x0 },
430+ { 0x1114c0, 0x0 },
431+ { 0x2114c0, 0x0 },
432+ { 0x115c0, 0x0 },
433+ { 0x1115c0, 0x0 },
434+ { 0x2115c0, 0x0 },
435+ { 0x116c0, 0x0 },
436+ { 0x1116c0, 0x0 },
437+ { 0x2116c0, 0x0 },
438+ { 0x117c0, 0x0 },
439+ { 0x1117c0, 0x0 },
440+ { 0x2117c0, 0x0 },
441+ { 0x118c0, 0x0 },
442+ { 0x1118c0, 0x0 },
443+ { 0x2118c0, 0x0 },
444+ { 0x120c0, 0x0 },
445+ { 0x1120c0, 0x0 },
446+ { 0x2120c0, 0x0 },
447+ { 0x121c0, 0x0 },
448+ { 0x1121c0, 0x0 },
449+ { 0x2121c0, 0x0 },
450+ { 0x122c0, 0x0 },
451+ { 0x1122c0, 0x0 },
452+ { 0x2122c0, 0x0 },
453+ { 0x123c0, 0x0 },
454+ { 0x1123c0, 0x0 },
455+ { 0x2123c0, 0x0 },
456+ { 0x124c0, 0x0 },
457+ { 0x1124c0, 0x0 },
458+ { 0x2124c0, 0x0 },
459+ { 0x125c0, 0x0 },
460+ { 0x1125c0, 0x0 },
461+ { 0x2125c0, 0x0 },
462+ { 0x126c0, 0x0 },
463+ { 0x1126c0, 0x0 },
464+ { 0x2126c0, 0x0 },
465+ { 0x127c0, 0x0 },
466+ { 0x1127c0, 0x0 },
467+ { 0x2127c0, 0x0 },
468+ { 0x128c0, 0x0 },
469+ { 0x1128c0, 0x0 },
470+ { 0x2128c0, 0x0 },
471+ { 0x130c0, 0x0 },
472+ { 0x1130c0, 0x0 },
473+ { 0x2130c0, 0x0 },
474+ { 0x131c0, 0x0 },
475+ { 0x1131c0, 0x0 },
476+ { 0x2131c0, 0x0 },
477+ { 0x132c0, 0x0 },
478+ { 0x1132c0, 0x0 },
479+ { 0x2132c0, 0x0 },
480+ { 0x133c0, 0x0 },
481+ { 0x1133c0, 0x0 },
482+ { 0x2133c0, 0x0 },
483+ { 0x134c0, 0x0 },
484+ { 0x1134c0, 0x0 },
485+ { 0x2134c0, 0x0 },
486+ { 0x135c0, 0x0 },
487+ { 0x1135c0, 0x0 },
488+ { 0x2135c0, 0x0 },
489+ { 0x136c0, 0x0 },
490+ { 0x1136c0, 0x0 },
491+ { 0x2136c0, 0x0 },
492+ { 0x137c0, 0x0 },
493+ { 0x1137c0, 0x0 },
494+ { 0x2137c0, 0x0 },
495+ { 0x138c0, 0x0 },
496+ { 0x1138c0, 0x0 },
497+ { 0x2138c0, 0x0 },
498+ { 0x100c1, 0x0 },
499+ { 0x1100c1, 0x0 },
500+ { 0x2100c1, 0x0 },
501+ { 0x101c1, 0x0 },
502+ { 0x1101c1, 0x0 },
503+ { 0x2101c1, 0x0 },
504+ { 0x102c1, 0x0 },
505+ { 0x1102c1, 0x0 },
506+ { 0x2102c1, 0x0 },
507+ { 0x103c1, 0x0 },
508+ { 0x1103c1, 0x0 },
509+ { 0x2103c1, 0x0 },
510+ { 0x104c1, 0x0 },
511+ { 0x1104c1, 0x0 },
512+ { 0x2104c1, 0x0 },
513+ { 0x105c1, 0x0 },
514+ { 0x1105c1, 0x0 },
515+ { 0x2105c1, 0x0 },
516+ { 0x106c1, 0x0 },
517+ { 0x1106c1, 0x0 },
518+ { 0x2106c1, 0x0 },
519+ { 0x107c1, 0x0 },
520+ { 0x1107c1, 0x0 },
521+ { 0x2107c1, 0x0 },
522+ { 0x108c1, 0x0 },
523+ { 0x1108c1, 0x0 },
524+ { 0x2108c1, 0x0 },
525+ { 0x110c1, 0x0 },
526+ { 0x1110c1, 0x0 },
527+ { 0x2110c1, 0x0 },
528+ { 0x111c1, 0x0 },
529+ { 0x1111c1, 0x0 },
530+ { 0x2111c1, 0x0 },
531+ { 0x112c1, 0x0 },
532+ { 0x1112c1, 0x0 },
533+ { 0x2112c1, 0x0 },
534+ { 0x113c1, 0x0 },
535+ { 0x1113c1, 0x0 },
536+ { 0x2113c1, 0x0 },
537+ { 0x114c1, 0x0 },
538+ { 0x1114c1, 0x0 },
539+ { 0x2114c1, 0x0 },
540+ { 0x115c1, 0x0 },
541+ { 0x1115c1, 0x0 },
542+ { 0x2115c1, 0x0 },
543+ { 0x116c1, 0x0 },
544+ { 0x1116c1, 0x0 },
545+ { 0x2116c1, 0x0 },
546+ { 0x117c1, 0x0 },
547+ { 0x1117c1, 0x0 },
548+ { 0x2117c1, 0x0 },
549+ { 0x118c1, 0x0 },
550+ { 0x1118c1, 0x0 },
551+ { 0x2118c1, 0x0 },
552+ { 0x120c1, 0x0 },
553+ { 0x1120c1, 0x0 },
554+ { 0x2120c1, 0x0 },
555+ { 0x121c1, 0x0 },
556+ { 0x1121c1, 0x0 },
557+ { 0x2121c1, 0x0 },
558+ { 0x122c1, 0x0 },
559+ { 0x1122c1, 0x0 },
560+ { 0x2122c1, 0x0 },
561+ { 0x123c1, 0x0 },
562+ { 0x1123c1, 0x0 },
563+ { 0x2123c1, 0x0 },
564+ { 0x124c1, 0x0 },
565+ { 0x1124c1, 0x0 },
566+ { 0x2124c1, 0x0 },
567+ { 0x125c1, 0x0 },
568+ { 0x1125c1, 0x0 },
569+ { 0x2125c1, 0x0 },
570+ { 0x126c1, 0x0 },
571+ { 0x1126c1, 0x0 },
572+ { 0x2126c1, 0x0 },
573+ { 0x127c1, 0x0 },
574+ { 0x1127c1, 0x0 },
575+ { 0x2127c1, 0x0 },
576+ { 0x128c1, 0x0 },
577+ { 0x1128c1, 0x0 },
578+ { 0x2128c1, 0x0 },
579+ { 0x130c1, 0x0 },
580+ { 0x1130c1, 0x0 },
581+ { 0x2130c1, 0x0 },
582+ { 0x131c1, 0x0 },
583+ { 0x1131c1, 0x0 },
584+ { 0x2131c1, 0x0 },
585+ { 0x132c1, 0x0 },
586+ { 0x1132c1, 0x0 },
587+ { 0x2132c1, 0x0 },
588+ { 0x133c1, 0x0 },
589+ { 0x1133c1, 0x0 },
590+ { 0x2133c1, 0x0 },
591+ { 0x134c1, 0x0 },
592+ { 0x1134c1, 0x0 },
593+ { 0x2134c1, 0x0 },
594+ { 0x135c1, 0x0 },
595+ { 0x1135c1, 0x0 },
596+ { 0x2135c1, 0x0 },
597+ { 0x136c1, 0x0 },
598+ { 0x1136c1, 0x0 },
599+ { 0x2136c1, 0x0 },
600+ { 0x137c1, 0x0 },
601+ { 0x1137c1, 0x0 },
602+ { 0x2137c1, 0x0 },
603+ { 0x138c1, 0x0 },
604+ { 0x1138c1, 0x0 },
605+ { 0x2138c1, 0x0 },
606+ { 0x10020, 0x0 },
607+ { 0x110020, 0x0 },
608+ { 0x210020, 0x0 },
609+ { 0x11020, 0x0 },
610+ { 0x111020, 0x0 },
611+ { 0x211020, 0x0 },
612+ { 0x12020, 0x0 },
613+ { 0x112020, 0x0 },
614+ { 0x212020, 0x0 },
615+ { 0x13020, 0x0 },
616+ { 0x113020, 0x0 },
617+ { 0x213020, 0x0 },
618+ { 0x20072, 0x0 },
619+ { 0x20073, 0x0 },
620+ { 0x20074, 0x0 },
621+ { 0x100aa, 0x0 },
622+ { 0x110aa, 0x0 },
623+ { 0x120aa, 0x0 },
624+ { 0x130aa, 0x0 },
625+ { 0x20010, 0x0 },
626+ { 0x120010, 0x0 },
627+ { 0x220010, 0x0 },
628+ { 0x20011, 0x0 },
629+ { 0x120011, 0x0 },
630+ { 0x220011, 0x0 },
631+ { 0x100ae, 0x0 },
632+ { 0x1100ae, 0x0 },
633+ { 0x2100ae, 0x0 },
634+ { 0x100af, 0x0 },
635+ { 0x1100af, 0x0 },
636+ { 0x2100af, 0x0 },
637+ { 0x110ae, 0x0 },
638+ { 0x1110ae, 0x0 },
639+ { 0x2110ae, 0x0 },
640+ { 0x110af, 0x0 },
641+ { 0x1110af, 0x0 },
642+ { 0x2110af, 0x0 },
643+ { 0x120ae, 0x0 },
644+ { 0x1120ae, 0x0 },
645+ { 0x2120ae, 0x0 },
646+ { 0x120af, 0x0 },
647+ { 0x1120af, 0x0 },
648+ { 0x2120af, 0x0 },
649+ { 0x130ae, 0x0 },
650+ { 0x1130ae, 0x0 },
651+ { 0x2130ae, 0x0 },
652+ { 0x130af, 0x0 },
653+ { 0x1130af, 0x0 },
654+ { 0x2130af, 0x0 },
655+ { 0x20020, 0x0 },
656+ { 0x120020, 0x0 },
657+ { 0x220020, 0x0 },
658+ { 0x100a0, 0x0 },
659+ { 0x100a1, 0x0 },
660+ { 0x100a2, 0x0 },
661+ { 0x100a3, 0x0 },
662+ { 0x100a4, 0x0 },
663+ { 0x100a5, 0x0 },
664+ { 0x100a6, 0x0 },
665+ { 0x100a7, 0x0 },
666+ { 0x110a0, 0x0 },
667+ { 0x110a1, 0x0 },
668+ { 0x110a2, 0x0 },
669+ { 0x110a3, 0x0 },
670+ { 0x110a4, 0x0 },
671+ { 0x110a5, 0x0 },
672+ { 0x110a6, 0x0 },
673+ { 0x110a7, 0x0 },
674+ { 0x120a0, 0x0 },
675+ { 0x120a1, 0x0 },
676+ { 0x120a2, 0x0 },
677+ { 0x120a3, 0x0 },
678+ { 0x120a4, 0x0 },
679+ { 0x120a5, 0x0 },
680+ { 0x120a6, 0x0 },
681+ { 0x120a7, 0x0 },
682+ { 0x130a0, 0x0 },
683+ { 0x130a1, 0x0 },
684+ { 0x130a2, 0x0 },
685+ { 0x130a3, 0x0 },
686+ { 0x130a4, 0x0 },
687+ { 0x130a5, 0x0 },
688+ { 0x130a6, 0x0 },
689+ { 0x130a7, 0x0 },
690+ { 0x2007c, 0x0 },
691+ { 0x12007c, 0x0 },
692+ { 0x22007c, 0x0 },
693+ { 0x2007d, 0x0 },
694+ { 0x12007d, 0x0 },
695+ { 0x22007d, 0x0 },
696+ { 0x400fd, 0x0 },
697+ { 0x400c0, 0x0 },
698+ { 0x90201, 0x0 },
699+ { 0x190201, 0x0 },
700+ { 0x290201, 0x0 },
701+ { 0x90202, 0x0 },
702+ { 0x190202, 0x0 },
703+ { 0x290202, 0x0 },
704+ { 0x90203, 0x0 },
705+ { 0x190203, 0x0 },
706+ { 0x290203, 0x0 },
707+ { 0x90204, 0x0 },
708+ { 0x190204, 0x0 },
709+ { 0x290204, 0x0 },
710+ { 0x90205, 0x0 },
711+ { 0x190205, 0x0 },
712+ { 0x290205, 0x0 },
713+ { 0x90206, 0x0 },
714+ { 0x190206, 0x0 },
715+ { 0x290206, 0x0 },
716+ { 0x90207, 0x0 },
717+ { 0x190207, 0x0 },
718+ { 0x290207, 0x0 },
719+ { 0x90208, 0x0 },
720+ { 0x190208, 0x0 },
721+ { 0x290208, 0x0 },
722+ { 0x10062, 0x0 },
723+ { 0x10162, 0x0 },
724+ { 0x10262, 0x0 },
725+ { 0x10362, 0x0 },
726+ { 0x10462, 0x0 },
727+ { 0x10562, 0x0 },
728+ { 0x10662, 0x0 },
729+ { 0x10762, 0x0 },
730+ { 0x10862, 0x0 },
731+ { 0x11062, 0x0 },
732+ { 0x11162, 0x0 },
733+ { 0x11262, 0x0 },
734+ { 0x11362, 0x0 },
735+ { 0x11462, 0x0 },
736+ { 0x11562, 0x0 },
737+ { 0x11662, 0x0 },
738+ { 0x11762, 0x0 },
739+ { 0x11862, 0x0 },
740+ { 0x12062, 0x0 },
741+ { 0x12162, 0x0 },
742+ { 0x12262, 0x0 },
743+ { 0x12362, 0x0 },
744+ { 0x12462, 0x0 },
745+ { 0x12562, 0x0 },
746+ { 0x12662, 0x0 },
747+ { 0x12762, 0x0 },
748+ { 0x12862, 0x0 },
749+ { 0x13062, 0x0 },
750+ { 0x13162, 0x0 },
751+ { 0x13262, 0x0 },
752+ { 0x13362, 0x0 },
753+ { 0x13462, 0x0 },
754+ { 0x13562, 0x0 },
755+ { 0x13662, 0x0 },
756+ { 0x13762, 0x0 },
757+ { 0x13862, 0x0 },
758+ { 0x20077, 0x0 },
759+ { 0x10001, 0x0 },
760+ { 0x11001, 0x0 },
761+ { 0x12001, 0x0 },
762+ { 0x13001, 0x0 },
763+ { 0x10040, 0x0 },
764+ { 0x10140, 0x0 },
765+ { 0x10240, 0x0 },
766+ { 0x10340, 0x0 },
767+ { 0x10440, 0x0 },
768+ { 0x10540, 0x0 },
769+ { 0x10640, 0x0 },
770+ { 0x10740, 0x0 },
771+ { 0x10840, 0x0 },
772+ { 0x10030, 0x0 },
773+ { 0x10130, 0x0 },
774+ { 0x10230, 0x0 },
775+ { 0x10330, 0x0 },
776+ { 0x10430, 0x0 },
777+ { 0x10530, 0x0 },
778+ { 0x10630, 0x0 },
779+ { 0x10730, 0x0 },
780+ { 0x10830, 0x0 },
781+ { 0x11040, 0x0 },
782+ { 0x11140, 0x0 },
783+ { 0x11240, 0x0 },
784+ { 0x11340, 0x0 },
785+ { 0x11440, 0x0 },
786+ { 0x11540, 0x0 },
787+ { 0x11640, 0x0 },
788+ { 0x11740, 0x0 },
789+ { 0x11840, 0x0 },
790+ { 0x11030, 0x0 },
791+ { 0x11130, 0x0 },
792+ { 0x11230, 0x0 },
793+ { 0x11330, 0x0 },
794+ { 0x11430, 0x0 },
795+ { 0x11530, 0x0 },
796+ { 0x11630, 0x0 },
797+ { 0x11730, 0x0 },
798+ { 0x11830, 0x0 },
799+ { 0x12040, 0x0 },
800+ { 0x12140, 0x0 },
801+ { 0x12240, 0x0 },
802+ { 0x12340, 0x0 },
803+ { 0x12440, 0x0 },
804+ { 0x12540, 0x0 },
805+ { 0x12640, 0x0 },
806+ { 0x12740, 0x0 },
807+ { 0x12840, 0x0 },
808+ { 0x12030, 0x0 },
809+ { 0x12130, 0x0 },
810+ { 0x12230, 0x0 },
811+ { 0x12330, 0x0 },
812+ { 0x12430, 0x0 },
813+ { 0x12530, 0x0 },
814+ { 0x12630, 0x0 },
815+ { 0x12730, 0x0 },
816+ { 0x12830, 0x0 },
817+ { 0x13040, 0x0 },
818+ { 0x13140, 0x0 },
819+ { 0x13240, 0x0 },
820+ { 0x13340, 0x0 },
821+ { 0x13440, 0x0 },
822+ { 0x13540, 0x0 },
823+ { 0x13640, 0x0 },
824+ { 0x13740, 0x0 },
825+ { 0x13840, 0x0 },
826+ { 0x13030, 0x0 },
827+ { 0x13130, 0x0 },
828+ { 0x13230, 0x0 },
829+ { 0x13330, 0x0 },
830+ { 0x13430, 0x0 },
831+ { 0x13530, 0x0 },
832+ { 0x13630, 0x0 },
833+ { 0x13730, 0x0 },
834+ { 0x13830, 0x0 },
835+};
836+
837+/* P0 message block paremeter for training firmware */
838+struct dram_cfg_param ddr_fsp0_cfg[] = {
839+ { 0xd0000, 0x0 },
840+ { 0x54003, 0xe94 },
841+ { 0x54004, 0x4 },
842+ { 0x54006, 0x15 },
843+ { 0x54008, 0x131f },
844+ { 0x54009, 0xff },
845+ { 0x5400b, 0x4 },
846+ { 0x5400c, 0x1 },
847+ { 0x5400d, 0x100 },
848+ { 0x5400f, 0x100 },
849+ { 0x54012, 0x110 },
850+ { 0x54019, 0x36e4 },
851+ { 0x5401a, 0x32 },
852+ { 0x5401b, 0x1146 },
853+ { 0x5401c, 0x1108 },
854+ { 0x5401e, 0x4 },
855+ { 0x5401f, 0x36e4 },
856+ { 0x54020, 0x32 },
857+ { 0x54021, 0x1146 },
858+ { 0x54022, 0x1108 },
859+ { 0x54024, 0x4 },
860+ { 0x54032, 0xe400 },
861+ { 0x54033, 0x3236 },
862+ { 0x54034, 0x4600 },
863+ { 0x54035, 0x811 },
864+ { 0x54036, 0x11 },
865+ { 0x54037, 0x400 },
866+ { 0x54038, 0xe400 },
867+ { 0x54039, 0x3236 },
868+ { 0x5403a, 0x4600 },
869+ { 0x5403b, 0x811 },
870+ { 0x5403c, 0x11 },
871+ { 0x5403d, 0x400 },
872+ { 0xd0000, 0x1 },
873+};
874+
875+/* P0 2D message block paremeter for training firmware */
876+struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
877+ { 0xd0000, 0x0 },
878+ { 0x54003, 0xe94 },
879+ { 0x54004, 0x4 },
880+ { 0x54006, 0x15 },
881+ { 0x54008, 0x61 },
882+ { 0x54009, 0xff },
883+ { 0x5400b, 0x4 },
884+ { 0x5400c, 0x1 },
885+ { 0x5400d, 0x100 },
886+ { 0x5400f, 0x100 },
887+ { 0x54010, 0x2080 },
888+ { 0x54012, 0x110 },
889+ { 0x54019, 0x36e4 },
890+ { 0x5401a, 0x32 },
891+ { 0x5401b, 0x1146 },
892+ { 0x5401c, 0x1108 },
893+ { 0x5401e, 0x4 },
894+ { 0x5401f, 0x36e4 },
895+ { 0x54020, 0x32 },
896+ { 0x54021, 0x1146 },
897+ { 0x54022, 0x1108 },
898+ { 0x54024, 0x4 },
899+ { 0x54032, 0xe400 },
900+ { 0x54033, 0x3236 },
901+ { 0x54034, 0x4600 },
902+ { 0x54035, 0x811 },
903+ { 0x54036, 0x11 },
904+ { 0x54037, 0x400 },
905+ { 0x54038, 0xe400 },
906+ { 0x54039, 0x3236 },
907+ { 0x5403a, 0x4600 },
908+ { 0x5403b, 0x811 },
909+ { 0x5403c, 0x11 },
910+ { 0x5403d, 0x400 },
911+ { 0xd0000, 0x1 },
912+};
913+
914+/* DRAM PHY init engine image */
915+struct dram_cfg_param ddr_phy_pie[] = {
916+ { 0xd0000, 0x0 },
917+ { 0x90000, 0x10 },
918+ { 0x90001, 0x400 },
919+ { 0x90002, 0x10e },
920+ { 0x90003, 0x0 },
921+ { 0x90004, 0x0 },
922+ { 0x90005, 0x8 },
923+ { 0x90029, 0xb },
924+ { 0x9002a, 0x480 },
925+ { 0x9002b, 0x109 },
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1355+ { 0x9016d, 0x47 },
1356+ { 0x9016e, 0x630 },
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1358+ { 0x90170, 0x8 },
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1369+ { 0x9017b, 0x10c },
1370+ { 0x9017c, 0x0 },
1371+ { 0x9017d, 0x478 },
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1374+ { 0x90180, 0x1 },
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1376+ { 0x90182, 0x8 },
1377+ { 0x90183, 0x4 },
1378+ { 0x90184, 0x0 },
1379+ { 0x90006, 0x8 },
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1382+ { 0x90009, 0x0 },
1383+ { 0x9000a, 0x400 },
1384+ { 0x9000b, 0x106 },
1385+ { 0xd00e7, 0x400 },
1386+ { 0x90017, 0x0 },
1387+ { 0x9001f, 0x2b },
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1389+ { 0x400d0, 0x0 },
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1391+ { 0x400d2, 0x105 },
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1396+ { 0x400d7, 0x20b },
1397+ { 0x2003a, 0x2 },
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1399+ { 0x2000b, 0x419 },
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1401+ { 0x2000d, 0x91c },
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1405+ { 0x9000e, 0x60 },
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1407+ { 0x90010, 0x2152 },
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1435+ { 0x11011, 0x1 },
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1438+ { 0x11018, 0x1 },
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1447+ { 0x117b4, 0x1 },
1448+ { 0x118b4, 0x1 },
1449+ { 0x20089, 0x1 },
1450+ { 0x20088, 0x19 },
1451+ { 0xc0080, 0x0 },
1452+ { 0xd0000, 0x1 }
1453+};
1454+
1455+struct dram_fsp_msg ddr_dram_fsp_msg[] = {
1456+ {
1457+ /* P0 3733mts 1D */
1458+ .drate = 3733,
1459+ .fw_type = FW_1D_IMAGE,
1460+ .fsp_cfg = ddr_fsp0_cfg,
1461+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
1462+ },
1463+ {
1464+ /* P0 3733mts 1D */
1465+ .drate = 3733,
1466+ .fw_type = FW_2D_IMAGE,
1467+ .fsp_cfg = ddr_fsp0_2d_cfg,
1468+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
1469+ },
1470+};
1471+
1472+/* ddr timing config params */
1473+struct dram_timing_info dram_timing = {
1474+ .ddrc_cfg = ddr_ddrc_cfg,
1475+ .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
1476+ .ddrphy_cfg = ddr_ddrphy_cfg,
1477+ .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
1478+ .fsp_msg = ddr_dram_fsp_msg,
1479+ .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
1480+ .ddrphy_trained_csr = ddr_ddrphy_trained_csr,
1481+ .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
1482+ .ddrphy_pie = ddr_phy_pie,
1483+ .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
1484+ .fsp_table = { 3733, },
1485+};
--- /dev/null
+++ b/board/freescale/imx93_evk/spl.c
@@ -0,0 +1,126 @@
1+// SPDX-License-Identifier: GPL-2.0+
2+/*
3+ * Copyright 2022 NXP
4+ */
5+
6+#include <common.h>
7+#include <command.h>
8+#include <cpu_func.h>
9+#include <hang.h>
10+#include <image.h>
11+#include <init.h>
12+#include <log.h>
13+#include <spl.h>
14+#include <asm/global_data.h>
15+#include <asm/io.h>
16+#include <asm/arch/imx93_pins.h>
17+#include <asm/arch/clock.h>
18+#include <asm/arch/sys_proto.h>
19+#include <asm/mach-imx/boot_mode.h>
20+#include <asm/mach-imx/mxc_i2c.h>
21+#include <asm/arch-mx7ulp/gpio.h>
22+#include <asm/mach-imx/syscounter.h>
23+#include <asm/mach-imx/s400_api.h>
24+#include <dm/uclass.h>
25+#include <dm/device.h>
26+#include <dm/uclass-internal.h>
27+#include <dm/device-internal.h>
28+#include <linux/delay.h>
29+#include <asm/arch/clock.h>
30+#include <asm/arch/ccm_regs.h>
31+#include <asm/arch/ddr.h>
32+#include <power/pmic.h>
33+#include <power/pca9450.h>
34+#include <asm/arch/trdc.h>
35+
36+DECLARE_GLOBAL_DATA_PTR;
37+
38+int spl_board_boot_device(enum boot_device boot_dev_spl)
39+{
40+ return BOOT_DEVICE_BOOTROM;
41+}
42+
43+void spl_board_init(void)
44+{
45+ puts("Normal Boot\n");
46+}
47+
48+void spl_dram_init(void)
49+{
50+ ddr_init(&dram_timing);
51+}
52+
53+#if CONFIG_IS_ENABLED(DM_PMIC_PCA9450)
54+int power_init_board(void)
55+{
56+ struct udevice *dev;
57+ int ret;
58+
59+ ret = pmic_get("pmic@25", &dev);
60+ if (ret == -ENODEV) {
61+ puts("No pca9450@25\n");
62+ return 0;
63+ }
64+ if (ret != 0)
65+ return ret;
66+
67+ /* BUCKxOUT_DVS0/1 control BUCK123 output */
68+ pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29);
69+
70+ /* 0.9v
71+ */
72+ pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x18);
73+ pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, 0x18);
74+
75+ /* I2C_LT_EN*/
76+ pmic_reg_write(dev, 0xa, 0x3);
77+
78+ /* set WDOG_B_CFG to cold reset */
79+ pmic_reg_write(dev, PCA9450_RESET_CTRL, 0xA1);
80+ return 0;
81+}
82+#endif
83+
84+extern int imx9_probe_mu(void *ctx, struct event *event);
85+void board_init_f(ulong dummy)
86+{
87+ int ret;
88+
89+ /* Clear the BSS. */
90+ memset(__bss_start, 0, __bss_end - __bss_start);
91+
92+ timer_init();
93+
94+ arch_cpu_init();
95+
96+ board_early_init_f();
97+
98+ spl_early_init();
99+
100+ preloader_console_init();
101+
102+ ret = imx9_probe_mu(NULL, NULL);
103+ if (ret) {
104+ printf("Fail to init Sentinel API\n");
105+ } else {
106+ printf("SOC: 0x%x\n", gd->arch.soc_rev);
107+ printf("LC: 0x%x\n", gd->arch.lifecycle);
108+ }
109+ power_init_board();
110+
111+ /* Init power of mix */
112+ soc_power_init();
113+
114+ /* Setup TRDC for DDR access */
115+ trdc_init();
116+
117+ /* DDR initialization */
118+ spl_dram_init();
119+
120+ /* Put M33 into CPUWAIT for following kick */
121+ ret = m33_prepare();
122+ if (!ret)
123+ printf("M33 prepare ok\n");
124+
125+ board_init_r(NULL, 0);
126+}
--- /dev/null
+++ b/configs/imx93_11x11_evk_defconfig
@@ -0,0 +1,108 @@
1+CONFIG_ARM=y
2+CONFIG_ARCH_IMX9=y
3+CONFIG_SYS_TEXT_BASE=0x80200000
4+CONFIG_SYS_MALLOC_LEN=0x2000000
5+CONFIG_SYS_MALLOC_F_LEN=0x18000
6+CONFIG_SPL_LIBCOMMON_SUPPORT=y
7+CONFIG_SPL_LIBGENERIC_SUPPORT=y
8+CONFIG_NR_DRAM_BANKS=2
9+CONFIG_ENV_SIZE=0x4000
10+CONFIG_ENV_OFFSET=0x400000
11+CONFIG_DM_GPIO=y
12+CONFIG_DEFAULT_DEVICE_TREE="imx93-11x11-evk"
13+CONFIG_SPL_TEXT_BASE=0x2049A000
14+CONFIG_TARGET_IMX93_11X11_EVK=y
15+CONFIG_SPL_SERIAL=y
16+CONFIG_SPL_DRIVERS_MISC=y
17+CONFIG_SPL=y
18+CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x88000000
19+CONFIG_SPL_LOAD_IMX_CONTAINER=y
20+CONFIG_SYS_LOAD_ADDR=0x80400000
21+CONFIG_SYS_MEMTEST_START=0x80000000
22+CONFIG_SYS_MEMTEST_END=0x90000000
23+CONFIG_DISTRO_DEFAULTS=y
24+CONFIG_REMAKE_ELF=y
25+CONFIG_DEFAULT_FDT_FILE="imx93-11x11-evk.dtb"
26+CONFIG_ARCH_MISC_INIT=y
27+CONFIG_BOARD_EARLY_INIT_F=y
28+CONFIG_BOARD_LATE_INIT=y
29+CONFIG_SPL_MAX_SIZE=0x26000
30+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
31+CONFIG_SPL_BSS_START_ADDR=0x2051e000
32+CONFIG_SPL_BSS_MAX_SIZE=0x2000
33+CONFIG_SPL_BOARD_INIT=y
34+CONFIG_SPL_BOOTROM_SUPPORT=y
35+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
36+CONFIG_SPL_STACK=0x2051ddd0
37+CONFIG_SYS_SPL_MALLOC=y
38+CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
39+CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x83200000
40+CONFIG_SYS_SPL_MALLOC_SIZE=0x80000
41+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
42+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1040
43+CONFIG_SPL_I2C=y
44+CONFIG_SPL_POWER=y
45+CONFIG_SPL_WATCHDOG=y
46+CONFIG_SYS_PROMPT="u-boot=> "
47+CONFIG_SYS_MAXARGS=64
48+CONFIG_SYS_CBSIZE=2048
49+CONFIG_SYS_PBSIZE=2074
50+CONFIG_CMD_ERASEENV=y
51+# CONFIG_CMD_CRC32 is not set
52+CONFIG_CMD_MEMTEST=y
53+CONFIG_CMD_CLK=y
54+CONFIG_CMD_DFU=y
55+CONFIG_CMD_FUSE=y
56+CONFIG_CMD_GPIO=y
57+CONFIG_CMD_GPT=y
58+CONFIG_CMD_I2C=y
59+CONFIG_CMD_MMC=y
60+CONFIG_CMD_POWEROFF=y
61+CONFIG_CMD_SNTP=y
62+CONFIG_CMD_CACHE=y
63+CONFIG_CMD_RTC=y
64+CONFIG_CMD_TIME=y
65+CONFIG_CMD_GETTIME=y
66+CONFIG_CMD_TIMER=y
67+CONFIG_CMD_REGULATOR=y
68+CONFIG_CMD_HASH=y
69+CONFIG_CMD_EXT4_WRITE=y
70+CONFIG_OF_CONTROL=y
71+CONFIG_SPL_OF_CONTROL=y
72+CONFIG_ENV_OVERWRITE=y
73+CONFIG_ENV_IS_NOWHERE=y
74+CONFIG_ENV_IS_IN_MMC=y
75+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
76+CONFIG_SYS_MMC_ENV_DEV=1
77+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
78+CONFIG_SPL_DM=y
79+CONFIG_REGMAP=y
80+CONFIG_SYSCON=y
81+CONFIG_IMX_RGPIO2P=y
82+CONFIG_DM_PCA953X=y
83+CONFIG_DM_I2C=y
84+CONFIG_SYS_I2C_IMX_LPI2C=y
85+CONFIG_SYS_I2C_SPEED=100000
86+CONFIG_SUPPORT_EMMC_BOOT=y
87+CONFIG_MMC_IO_VOLTAGE=y
88+CONFIG_MMC_UHS_SUPPORT=y
89+CONFIG_MMC_HS400_ES_SUPPORT=y
90+CONFIG_MMC_HS400_SUPPORT=y
91+CONFIG_FSL_USDHC=y
92+CONFIG_PINCTRL=y
93+CONFIG_SPL_PINCTRL=y
94+CONFIG_PINCTRL_IMX93=y
95+CONFIG_DM_PMIC=y
96+CONFIG_SPL_DM_PMIC_PCA9450=y
97+CONFIG_DM_REGULATOR=y
98+CONFIG_DM_REGULATOR_FIXED=y
99+CONFIG_DM_REGULATOR_GPIO=y
100+CONFIG_DM_RTC=y
101+CONFIG_RTC_EMULATION=y
102+CONFIG_DM_SERIAL=y
103+CONFIG_FSL_LPUART=y
104+CONFIG_ULP_WATCHDOG=y
105+CONFIG_LZO=y
106+CONFIG_BZIP2=y
107+CONFIG_USE_ETHPRIME=y
108+CONFIG_ETHPRIME="eth0"
--- /dev/null
+++ b/include/configs/imx93_evk.h
@@ -0,0 +1,145 @@
1+/* SPDX-License-Identifier: GPL-2.0+ */
2+/*
3+ * Copyright 2022 NXP
4+ */
5+
6+#ifndef __IMX93_EVK_H
7+#define __IMX93_EVK_H
8+
9+#include <linux/sizes.h>
10+#include <linux/stringify.h>
11+#include <asm/arch/imx-regs.h>
12+
13+#define CONFIG_SYS_MONITOR_LEN SZ_512K
14+#define CONFIG_SYS_UBOOT_BASE \
15+ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
16+
17+#ifdef CONFIG_SPL_BUILD
18+#define CONFIG_MALLOC_F_ADDR 0x204D0000
19+#endif
20+
21+#ifdef CONFIG_DISTRO_DEFAULTS
22+#define BOOT_TARGET_DEVICES(func) \
23+ func(MMC, mmc, 0) \
24+ func(MMC, mmc, 1) \
25+
26+#include <config_distro_bootcmd.h>
27+#else
28+#define BOOTENV
29+#endif
30+
31+/* Initial environment variables */
32+#define CONFIG_EXTRA_ENV_SETTINGS \
33+ BOOTENV \
34+ "scriptaddr=0x83500000\0" \
35+ "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
36+ "image=Image\0" \
37+ "splashimage=0x90000000\0" \
38+ "console=ttyLP0,115200 earlycon\0" \
39+ "fdt_addr_r=0x83000000\0" \
40+ "fdt_addr=0x83000000\0" \
41+ "cntr_addr=0x98000000\0" \
42+ "cntr_file=os_cntr_signed.bin\0" \
43+ "boot_fit=no\0" \
44+ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
45+ "bootm_size=0x10000000\0" \
46+ "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
47+ "mmcpart=1\0" \
48+ "mmcroot=/dev/mmcblk1p2 rootwait rw\0" \
49+ "mmcautodetect=yes\0" \
50+ "mmcargs=setenv bootargs ${jh_clk} console=${console} root=${mmcroot}\0 " \
51+ "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
52+ "bootscript=echo Running bootscript from mmc ...; " \
53+ "source\0" \
54+ "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
55+ "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile}\0" \
56+ "loadcntr=fatload mmc ${mmcdev}:${mmcpart} ${cntr_addr} ${cntr_file}\0" \
57+ "auth_os=auth_cntr ${cntr_addr}\0" \
58+ "boot_os=booti ${loadaddr} - ${fdt_addr_r};\0" \
59+ "mmcboot=echo Booting from mmc ...; " \
60+ "run mmcargs; " \
61+ "if test ${sec_boot} = yes; then " \
62+ "if run auth_os; then " \
63+ "run boot_os; " \
64+ "else " \
65+ "echo ERR: failed to authenticate; " \
66+ "fi; " \
67+ "else " \
68+ "if test ${boot_fit} = yes || test ${boot_fit} = try; then " \
69+ "bootm ${loadaddr}; " \
70+ "else " \
71+ "if run loadfdt; then " \
72+ "run boot_os; " \
73+ "else " \
74+ "echo WARN: Cannot load the DT; " \
75+ "fi; " \
76+ "fi;" \
77+ "fi;\0" \
78+ "netargs=setenv bootargs ${jh_clk} console=${console} " \
79+ "root=/dev/nfs " \
80+ "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
81+ "netboot=echo Booting from net ...; " \
82+ "run netargs; " \
83+ "if test ${ip_dyn} = yes; then " \
84+ "setenv get_cmd dhcp; " \
85+ "else " \
86+ "setenv get_cmd tftp; " \
87+ "fi; " \
88+ "if test ${sec_boot} = yes; then " \
89+ "${get_cmd} ${cntr_addr} ${cntr_file}; " \
90+ "if run auth_os; then " \
91+ "run boot_os; " \
92+ "else " \
93+ "echo ERR: failed to authenticate; " \
94+ "fi; " \
95+ "else " \
96+ "${get_cmd} ${loadaddr} ${image}; " \
97+ "if test ${boot_fit} = yes || test ${boot_fit} = try; then " \
98+ "bootm ${loadaddr}; " \
99+ "else " \
100+ "if ${get_cmd} ${fdt_addr_r} ${fdtfile}; then " \
101+ "run boot_os; " \
102+ "else " \
103+ "echo WARN: Cannot load the DT; " \
104+ "fi; " \
105+ "fi;" \
106+ "fi;\0" \
107+ "bsp_bootcmd=echo Running BSP bootcmd ...; " \
108+ "mmc dev ${mmcdev}; if mmc rescan; then " \
109+ "if run loadbootscript; then " \
110+ "run bootscript; " \
111+ "else " \
112+ "if test ${sec_boot} = yes; then " \
113+ "if run loadcntr; then " \
114+ "run mmcboot; " \
115+ "else run netboot; " \
116+ "fi; " \
117+ "else " \
118+ "if run loadimage; then " \
119+ "run mmcboot; " \
120+ "else run netboot; " \
121+ "fi; " \
122+ "fi; " \
123+ "fi; " \
124+ "fi;"
125+
126+/* Link Definitions */
127+
128+#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
129+#define CONFIG_SYS_INIT_RAM_SIZE 0x200000
130+
131+#define CONFIG_SYS_SDRAM_BASE 0x80000000
132+#define PHYS_SDRAM 0x80000000
133+#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */
134+
135+#define CONFIG_SYS_FSL_USDHC_NUM 2
136+
137+/* Using ULP WDOG for reset */
138+#define WDOG_BASE_ADDR WDG3_BASE_ADDR
139+
140+#if defined(CONFIG_CMD_NET)
141+#define DWC_NET_PHYADDR 1
142+#define PHY_ANEG_TIMEOUT 20000
143+#endif
144+
145+#endif