Commit: 1e8f1aff3cea72639bd50be54fb8b501ec0d2376 - uboot (git)

Commit MetaInfo

• Revision: 1e8f1aff3cea72639bd50be54fb8b501ec0d2376 (tree)
• Time: 2020-07-26 18:21:27
• Author: Yoshinori Sato <ysato@user...>
• Commiter: Yoshinori Sato

Log Message

Add ap-rx72m-0a

Change Summary

• add: arch/rx/dts/ap_rx72m_0a.dts
• add: board/alphaproject/ap_rx72m_0a/Kconfig
• add: board/alphaproject/ap_rx72m_0a/Makefile
• add: board/alphaproject/ap_rx72m_0a/ap_rx72m_0a.c
• add: board/alphaproject/ap_rx72m_0a/lowlevel_init.S
• add: board/alphaproject/ap_rx72m_0a/u-boot.lds
• add: configs/ap_rx72m_0a_defconfig
• add: include/configs/ap_rx72m_0a.h

Incremental Difference

--- /dev/null
+++ b/arch/rx/dts/ap_rx72m_0a.dts
@@ -0,0 +1,80 @@
+/dts-v1/;
+/ {
+	model = "Alphaproject AP-RX72M-0A";
+	compatible = "alphaproject,ap-rx72m-0a";
+        #address-cells = <1>;
+        #size-cells = <1>;
+	interrupt-parent = <&rxicu>;
+
+	chosen {
+		stdout-path = "serial0:38400";
+	};
+	aliases {
+		serial0 = &sci2;
+	};
+
+	xclk: oscillator {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <24000000>;
+		clock-output-names = "xtal";
+	};
+	iclk: iclk {
+		compatible = "renesas,rx-mul-clock";
+		clocks = <&xclk>;
+		#clock-cells = <0>;
+		reg = <0x00080020 4>;
+		renesas,offset = <24>;
+		renesas,maxfreq = <100000000>;
+	};
+	pclk: pclk {
+		compatible = "renesas,rx-mul-clock";
+		clocks = <&xclk>;
+		#clock-cells = <0>;
+		reg = <0x00080020 4>;
+		renesas,offset = <8>;
+		renesas,maxfreq = <50000000>;
+	};
+	bclk: bclk {
+		compatible = "renesas,rx-mul-clock";
+		clocks = <&xclk>;
+		#clock-cells = <0>;
+		reg = <0x00080020 4>;
+		renesas,offset = <16>;
+		renesas,maxfreq = <50000000>;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		cpu@0 {
+			compatible = "renesas,rx";
+			clock-frequency = <240000000>;
+			mem-cycle = <2>;
+		};
+	};
+	memory@08000000 {
+		device_type = "memory";
+		reg = <0x08000000 0x01000000>;
+	};
+
+	rxicu: interrupt-controller@87000 {
+		compatible = "renesas,rx-icu";
+		#interrupt-cells = <2>;
+		interrupt-controller;
+		reg = <0x00087000 0x600>;
+	};
+	
+	mtu: timer@00088600 {
+		compatible = "renesas,rx-mtu2";
+		reg = <0x00088600 0x600>;
+		clock-frequency = <46875>;
+	};
+		
+	sci2: serial@0008a040 {
+		compatible = "renesas,scif";
+		reg = <0x0008a040 8>;
+		interrupts = <214 0>, <215 0>, <216 0>, <217 0>;
+		clock = <60000000>;
+	};
+};

--- /dev/null
+++ b/board/alphaproject/ap_rx72m_0a/Kconfig
@@ -0,0 +1,9 @@
+if TARGET_AP_RX72M
+
+config SYS_BOARD
+	default "alphaproject/ap_rx72m_0a"
+
+config SYS_CONFIG_NAME
+	default "ap_rx72m_0a"
+
+endif

--- /dev/null
+++ b/board/alphaproject/ap_rx72m_0a/Makefile
@@ -0,0 +1,21 @@
+#
+# Copyright (C) 2014 Yoshinori Sato
+#
+# u-boot/board/hokuto/HSBRX63NC/Makefile
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+
+obj-y	:= ap_rx72m_0a.o lowlevel_init.o

--- /dev/null
+++ b/board/alphaproject/ap_rx72m_0a/ap_rx72m_0a.c
@@ -0,0 +1,94 @@
+/*
+ * Copyright (C) 2015 Yoshinori Sato
+ * (C) Copyright 2000-2003
+ *     Wolfgang Denk, DENX Software Engineering, [e-mail].
+ *
+ * board/hokuto/HSBRX63N/hsbrx63n.c
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mmc.h>
+#include <spi.h>
+#include <netdev.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+#include <asm/sections.h>
+#include <linux/usb/r8a66597.h>
+
+#define PRCR *(volatile unsigned short *)0x000803fe
+#define PFAOE0 *(volatile unsigned char *)0x0008c104
+#define PFBCR0 *(volatile unsigned char *)0x0008c106
+#define PFBCR1 *(volatile unsigned char *)0x0008c107
+#define PFBCR2 *(volatile unsigned char *)0x0008c108
+#define PFBCR3 *(volatile unsigned char *)0x0008c100
+#define PORTA_DSCR *(volatile unsigned char *)0x0008c0ea
+#define PORTB_DSCR *(volatile unsigned char *)0x0008c0eb
+#define PORTD_DSCR *(volatile unsigned char *)0x0008c0ed
+#define PORTE_DSCR *(volatile unsigned char *)0x0008c0ee
+#define SYSCR0 *(volatile unsigned short *)0x00080006
+#define SDIR *(volatile unsigned short *)0x00083c24
+#define SDSR *(volatile unsigned char *)0x00083c50
+#define SDMOD *(volatile unsigned short *)0x00083c48
+#define SDTR *(volatile unsigned long *)0x00083c44
+#define SDADR *(volatile unsigned char *)0x00083c40
+#define SDRFCR *(volatile unsigned short *)0x00083c14
+#define SDRFEN *(volatile unsigned char *)0x00083c16
+#define SDCR *(volatile unsigned char *)0x00083c00
+
+static void sdram_init(void)
+{
+	int w;
+
+	PRCR = 0xa503;
+	PFAOE0 = 0xff;
+	PFBCR0 = 0x11;
+	PFBCR1 = 0xd0;
+	PFBCR2 = 0x00;
+	PFBCR3 = 0xc0;
+
+	PORTA_DSCR = 0xff;
+	PORTB_DSCR = 0xff;
+	PORTD_DSCR = 0xff;
+	PORTE_DSCR = 0xff;
+	SYSCR0 = 0x5a03;
+	for (w = 0; w < 0x10000; w++);
+
+	SDIR = 0x0020;
+	while (SDSR != 0);
+	SDIR |= 0x0001;
+	while (SDSR != 0);
+	SDMOD = 0x230;
+	SDTR= 0x0031303;
+	SDADR = 0x01;
+	SDRFCR = 0x74e1;
+	SDRFEN |= 0x01;
+	SDCR |= 0x01;
+
+	memset(__bss_start, 0, (void *)&__bss_end - (void *)__bss_start);
+}
+
+#define P12PFS *(volatile unsigned char *)0x0008c14a
+#define P13PFS *(volatile unsigned char *)0x0008c14b
+
+int board_early_init_f(void)
+{
+	P12PFS = 0x0a;
+	P13PFS = 0x0a;
+	sdram_init();
+	return 0;
+}

--- /dev/null
+++ b/board/alphaproject/ap_rx72m_0a/lowlevel_init.S
@@ -0,0 +1,92 @@
+/*
+ * (C) Copyright 2020 Yoshinori Sato
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+
+#include <asm/processor.h>
+
+#define PRCR 	0x3fe
+#define CKOCR	0x3e
+#define HOCOCR	0x36
+#define HOCOPCR	0xc294
+#define MOFCR 	0x8c293	
+#define MOSCWTCR 0xa2
+#define MOSCCR	0x32	
+#define OSCOVFSR 0x3c
+#define PLLCR	0x28
+#define PLLCR2	0x2a
+#define SCKCR 	0x20
+#define SCKCR2	0x24
+#define SCKCR3	0x26
+#define MEMWAIT	0x101c
+/* PLL out:x10 PLL source:osc in: 24MHz = 240MHz */
+#define PLLCR_VAL (0x13 << 8) | (0x00 << 4) | (0x00 << 0)
+/* ICK=1 / PCKA = 2 / PCKB-D = 4 / FCK = 4 / BCK = 3 / UCK = 5 */
+#define SCKCR_VAL \
+	(2 << 28) | (0 << 24) | (1 << 22) | (9 << 16) | \
+	(1 << 12) | (2 << 8) | (2 << 4) | (2 << 4)
+
+	.global	lowlevel_init
+
+	.text
+	.align	2
+
+lowlevel_init:
+	mov.l	#0x00080000, r1
+	/* clock register unlock */
+	add	#PRCR, r1, r2
+	mov.w	#0xa50b, [r2]
+	/* CLKOUT - main clock / output disable */
+	mov.w	#(1 << 15) | (2 << 8), CKOCR[r1]
+	/* HOCO off */
+	mov.b	#0x01, HOCOCR[r1]
+	add	#HOCOPCR, r1, r2
+	mov.b	#0x01, [r2]
+	/* Main OSC enable */
+	add	#MOFCR, r1, r2
+	mov.b	#0, [r2]
+	add	#MOSCWTCR, r1, r2
+	mov.b	#0x53, [r2]
+	add	#MOSCCR, r1, r2
+	mov.b	#0, [r2]
+1:	mov.b	[r2], r3
+	cmp	#0, r3
+	bne	1b
+	/* Wait for main OSC stable */
+2:	btst	#0, OSCOVFSR[r1].b
+	beq	2b
+	mov.w	#PLLCR_VAL, PLLCR[r1]
+	mov.b	#0x00, PLLCR2[r1]
+	/* Wait for PLL stable */
+3:	btst	#2, OSCOVFSR[r1].b
+	beq	3b
+	mov.l	#SCKCR_VAL, SCKCR[r1]
+	mov.w	#(4 << 4) | 0x0001, SCKCR2[r1]
+	/* 1 wait */
+	add	#MEMWAIT, r1, r2
+	mov.b	#0x01, [r2]
+4:	mov.b	[r2], r3
+	cmp	#1,r3
+	bne	4b
+	/* Source PLL */
+	mov.w	#(4 << 8), SCKCR3[r1]
+	rts
+
+	.end

--- /dev/null
+++ b/board/alphaproject/ap_rx72m_0a/u-boot.lds
@@ -0,0 +1,94 @@
+/*
+ * Copyright (C) 2015 Yoshinori Sato
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+OUTPUT_FORMAT("elf32-rx-linux")
+OUTPUT_ARCH(rx)
+ENTRY(_start)
+
+MEMORY {
+	iram : ORIGIN = 0x0000100, LENGTH = 512K - 256
+	sdram : ORIGIN = 0x08000000, LENGTH = 16M
+	irom : ORIGIN = 0xfffc0000, LENGTH = 256K - 128
+	vector : ORIGIN = 0xffffff80, LENGTH = 128
+}
+
+SECTIONS
+{
+	.text :
+	{
+		PROVIDE (_ftext = .);
+		PROVIDE (_fcode = .);
+			PROVIDE (_start = .);
+
+		KEEP(arch/rx/cpu/rxv2/start.o (.text))
+		*(.text)
+		. = ALIGN(4);
+		PROVIDE (_ecode = .);
+	} > irom
+	.rodata :
+	{
+		*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+		. = ALIGN(4);
+	} > irom
+	.u_boot_list : {
+		KEEP(*(SORT(.u_boot_list*)));
+	} > irom
+	PROVIDE (_etext = .);
+
+	. = 0xffffff80;
+	.vector :
+	{
+		*(.vector);
+	} > vector
+
+	PROVIDE (__ram_vec = 0x00000000);
+
+	.data :
+	{
+		PROVIDE (_fdata = .);
+		*(.data)
+		*(.stack)
+		. = ALIGN(4);
+		PROVIDE (_edata = .);
+	} > iram AT>irom
+	_iram_start = _etext + SIZEOF(.data);
+	.iram.text :
+	{
+		_iram_text = .;
+		*(.iram.text)
+		_iram_text_end = .;
+	} > iram AT>irom
+
+	.bss :
+	{
+		PROVIDE (__bss_start = .);
+		*(.bss*)
+		. = ALIGN(4);
+	} > iram
+	PROVIDE (__bss_end = .);
+	PROVIDE (__init_end = .);
+
+	PROVIDE (__stack = 0x00040000);
+
+	PROVIDE (_end = .);
+}

--- /dev/null
+++ b/configs/ap_rx72m_0a_defconfig
@@ -0,0 +1,7 @@
+CONFIG_RX=y
+CONFIG_SYS_TEXT_BASE=0xfffc0000
+CONFIG_TARGET_AP_RX72M=y
+CONFIG_OF_CONTROL=y
+# CONFIG_NET is not set
+CONFIG_TIMER=y
+CONFIG_RX_TIMER=y

--- /dev/null
+++ b/include/configs/ap_rx72m_0a.h
@@ -0,0 +1,97 @@
+/*
+ * Configuation settings for AP-RX64M-0A
+ *
+ * Copyright (C) 2011 Yoshinori Sato
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __AP_RX64M_0A_H
+#define __AP_RX64M_0A_H
+
+/* SCI */
+#define CONFIG_SCIF_A		1
+#define CONFIG_SCIF_CONSOLE	1
+#define CONFIG_CONS_SCIF2	1
+
+/* memory */
+#define CONFIG_SYS_SRAM_BASE		0x00000000
+#define CONFIG_SYS_SRAM_SIZE		0x00080000
+#define CONFIG_SYS_SDRAM_BASE		0x08000000
+#define CONFIG_SYS_SDRAM_SIZE		(16 * 1024 * 1024)
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END		CONFIG_SYS_SDRAM_SIZE
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_MEMTEST_START + 0x100000)
+#define CONFIG_SYS_MONITOR_BASE		0x8000 /*(CONFIG_SYS_SDRAM_BASE)*/
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(64 * 1024)
+#define CONFIG_SYS_GBL_DATA_SIZE	256
+#define CONFIG_SYS_BOOTMAPSZ		(8 * 1024 * 1024)
+#define CONFIG_SYS_MAX_FLASH_SECT	128
+#define CONFIG_SYS_MAX_FLASH_BANKS	3
+#define CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_SYS_FLASH_SIZE		0x00400000
+
+#define CONFIG_SYS_CLK_FREQ 240000000
+#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
+#define CONFIG_SYS_HZ	1000
+
+#if defined(CONFIG_CMD_NET)
+#define CONFIG_SH_ETHER 1
+#define CONFIG_SH_ETHER_USE_PORT (0)
+#define CONFIG_SH_ETHER_PHY_ADDR (0x00)
+#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
+#define CONFIG_MII 1
+#define CONFIG_BITBANGMII 1
+#define CONFIG_BITBANGMII_MULTI 1
+#define CONFIG_PHYLIB 1
+#define CONFIG_PHY_SMSC 1
+#endif
+
+#if defined(CONFIG_CMD_USB)
+#define CONFIG_USB_R8A66597_HCD
+#define CONFIG_R8A66597_BASE_ADDR   0x000a0200
+#define CONFIG_R8A66597_ENDIAN      0x0000  /* little */
+#define CONFIG_SUPERH_ON_CHIP_R8A66597
+#define CONFIG_R8A66597_VBUS_NEG
+#define CONFIG_USB_STORAGE
+#endif
+
+#if 0
+#define CONFIG_USB_GADGET
+#define CONFIG_USB_GADGET_R8A66597
+#define CONFIG_R8A66597_UDC_BASE	0x000a0000
+#define CONFIG_USB_GADGET_SERIAL
+#define CONFIG_USB_TTY_CDC
+#endif
+
+#if defined(CONFIG_CMD_MMC_SPI) || defined(CONFIG_CMD_SPI)
+#define CONFIG_RX_RSPI
+#define CONFIG_RSPI_BASE	0x000883a0
+#define CONFIG_RSPI_CLK		CONFIG_SYS_CLK_FREQ
+#endif
+#if defined(CONFIG_CMD_MMC_SPI)
+#define CONFIG_MMC
+#define CONFIG_MMC_SPI
+#define CONFIG_GENERIC_MMC
+#endif
+
+/*#define CONFIG_RXRTC*/
+
+#endif