Revision | 3dc91ddbc68391f934bf6945853e99cf6810fc00 (tree) |
---|---|
Time | 2018-12-13 23:40:56 |
Author | Peter Maydell <peter.maydell@lina...> |
Commiter | Peter Maydell |
target/arm: Move id_aa64mmfr* to ARMISARegisters
At the same time, define the fields for these registers,
and use those defines in arm_pamax().
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20181203203839.757-2-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
[PMM: fixed up typo (s/achf/ahcf/) belatedly spotted by RTH]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
@@ -818,6 +818,8 @@ struct ARMCPU { | ||
818 | 818 | uint64_t id_aa64isar1; |
819 | 819 | uint64_t id_aa64pfr0; |
820 | 820 | uint64_t id_aa64pfr1; |
821 | + uint64_t id_aa64mmfr0; | |
822 | + uint64_t id_aa64mmfr1; | |
821 | 823 | } isar; |
822 | 824 | uint32_t midr; |
823 | 825 | uint32_t revidr; |
@@ -839,8 +841,6 @@ struct ARMCPU { | ||
839 | 841 | uint64_t id_aa64dfr1; |
840 | 842 | uint64_t id_aa64afr0; |
841 | 843 | uint64_t id_aa64afr1; |
842 | - uint64_t id_aa64mmfr0; | |
843 | - uint64_t id_aa64mmfr1; | |
844 | 844 | uint32_t dbgdidr; |
845 | 845 | uint32_t clidr; |
846 | 846 | uint64_t mp_affinity; /* MP ID without feature bits */ |
@@ -1557,6 +1557,28 @@ FIELD(ID_AA64PFR0, GIC, 24, 4) | ||
1557 | 1557 | FIELD(ID_AA64PFR0, RAS, 28, 4) |
1558 | 1558 | FIELD(ID_AA64PFR0, SVE, 32, 4) |
1559 | 1559 | |
1560 | +FIELD(ID_AA64MMFR0, PARANGE, 0, 4) | |
1561 | +FIELD(ID_AA64MMFR0, ASIDBITS, 4, 4) | |
1562 | +FIELD(ID_AA64MMFR0, BIGEND, 8, 4) | |
1563 | +FIELD(ID_AA64MMFR0, SNSMEM, 12, 4) | |
1564 | +FIELD(ID_AA64MMFR0, BIGENDEL0, 16, 4) | |
1565 | +FIELD(ID_AA64MMFR0, TGRAN16, 20, 4) | |
1566 | +FIELD(ID_AA64MMFR0, TGRAN64, 24, 4) | |
1567 | +FIELD(ID_AA64MMFR0, TGRAN4, 28, 4) | |
1568 | +FIELD(ID_AA64MMFR0, TGRAN16_2, 32, 4) | |
1569 | +FIELD(ID_AA64MMFR0, TGRAN64_2, 36, 4) | |
1570 | +FIELD(ID_AA64MMFR0, TGRAN4_2, 40, 4) | |
1571 | +FIELD(ID_AA64MMFR0, EXS, 44, 4) | |
1572 | + | |
1573 | +FIELD(ID_AA64MMFR1, HAFDBS, 0, 4) | |
1574 | +FIELD(ID_AA64MMFR1, VMIDBITS, 4, 4) | |
1575 | +FIELD(ID_AA64MMFR1, VH, 8, 4) | |
1576 | +FIELD(ID_AA64MMFR1, HPDS, 12, 4) | |
1577 | +FIELD(ID_AA64MMFR1, LO, 16, 4) | |
1578 | +FIELD(ID_AA64MMFR1, PAN, 20, 4) | |
1579 | +FIELD(ID_AA64MMFR1, SPECSEI, 24, 4) | |
1580 | +FIELD(ID_AA64MMFR1, XNX, 28, 4) | |
1581 | + | |
1560 | 1582 | QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <= R_V7M_CSSELR_INDEX_MASK); |
1561 | 1583 | |
1562 | 1584 | /* If adding a feature bit which corresponds to a Linux ELF |
@@ -141,7 +141,7 @@ static void aarch64_a57_initfn(Object *obj) | ||
141 | 141 | cpu->pmceid0 = 0x00000000; |
142 | 142 | cpu->pmceid1 = 0x00000000; |
143 | 143 | cpu->isar.id_aa64isar0 = 0x00011120; |
144 | - cpu->id_aa64mmfr0 = 0x00001124; | |
144 | + cpu->isar.id_aa64mmfr0 = 0x00001124; | |
145 | 145 | cpu->dbgdidr = 0x3516d000; |
146 | 146 | cpu->clidr = 0x0a200023; |
147 | 147 | cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */ |
@@ -195,7 +195,7 @@ static void aarch64_a53_initfn(Object *obj) | ||
195 | 195 | cpu->isar.id_aa64pfr0 = 0x00002222; |
196 | 196 | cpu->id_aa64dfr0 = 0x10305106; |
197 | 197 | cpu->isar.id_aa64isar0 = 0x00011120; |
198 | - cpu->id_aa64mmfr0 = 0x00001122; /* 40 bit physical addr */ | |
198 | + cpu->isar.id_aa64mmfr0 = 0x00001122; /* 40 bit physical addr */ | |
199 | 199 | cpu->dbgdidr = 0x3516d000; |
200 | 200 | cpu->clidr = 0x0a200023; |
201 | 201 | cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */ |
@@ -249,7 +249,7 @@ static void aarch64_a72_initfn(Object *obj) | ||
249 | 249 | cpu->pmceid0 = 0x00000000; |
250 | 250 | cpu->pmceid1 = 0x00000000; |
251 | 251 | cpu->isar.id_aa64isar0 = 0x00011120; |
252 | - cpu->id_aa64mmfr0 = 0x00001124; | |
252 | + cpu->isar.id_aa64mmfr0 = 0x00001124; | |
253 | 253 | cpu->dbgdidr = 0x3516d000; |
254 | 254 | cpu->clidr = 0x0a200023; |
255 | 255 | cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */ |
@@ -5207,11 +5207,11 @@ void register_cp_regs_for_features(ARMCPU *cpu) | ||
5207 | 5207 | { .name = "ID_AA64MMFR0_EL1", .state = ARM_CP_STATE_AA64, |
5208 | 5208 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0, |
5209 | 5209 | .access = PL1_R, .type = ARM_CP_CONST, |
5210 | - .resetvalue = cpu->id_aa64mmfr0 }, | |
5210 | + .resetvalue = cpu->isar.id_aa64mmfr0 }, | |
5211 | 5211 | { .name = "ID_AA64MMFR1_EL1", .state = ARM_CP_STATE_AA64, |
5212 | 5212 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 1, |
5213 | 5213 | .access = PL1_R, .type = ARM_CP_CONST, |
5214 | - .resetvalue = cpu->id_aa64mmfr1 }, | |
5214 | + .resetvalue = cpu->isar.id_aa64mmfr1 }, | |
5215 | 5215 | { .name = "ID_AA64MMFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64, |
5216 | 5216 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 2, |
5217 | 5217 | .access = PL1_R, .type = ARM_CP_CONST, |
@@ -229,7 +229,8 @@ static inline unsigned int arm_pamax(ARMCPU *cpu) | ||
229 | 229 | [4] = 44, |
230 | 230 | [5] = 48, |
231 | 231 | }; |
232 | - unsigned int parange = extract32(cpu->id_aa64mmfr0, 0, 4); | |
232 | + unsigned int parange = | |
233 | + FIELD_EX64(cpu->isar.id_aa64mmfr0, ID_AA64MMFR0, PARANGE); | |
233 | 234 | |
234 | 235 | /* id_aa64mmfr0 is a read-only register so values outside of the |
235 | 236 | * supported mappings can be considered an implementation error. */ |
@@ -538,6 +538,10 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) | ||
538 | 538 | ARM64_SYS_REG(3, 0, 0, 6, 0)); |
539 | 539 | err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64isar1, |
540 | 540 | ARM64_SYS_REG(3, 0, 0, 6, 1)); |
541 | + err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr0, | |
542 | + ARM64_SYS_REG(3, 0, 0, 7, 0)); | |
543 | + err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr1, | |
544 | + ARM64_SYS_REG(3, 0, 0, 7, 1)); | |
541 | 545 | |
542 | 546 | /* |
543 | 547 | * Note that if AArch32 support is not present in the host, |