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Revision50a7dc73c747c139f7ed8dc9d8bbf1e3c7c3e175 (tree)
Time2018-12-25 00:47:47
AuthorYoshinori Sato <ysato@user...>
CommiterYoshinori Sato

Log Message

Add RXv3 instruction support.
RXv3 manual
https://www.renesas.com/us/en/doc/products/mpumcu/doc/rx_family/r01us0316ej0100-rxv3sm.pdf

2018-12-25 Yoshinori Sato <ysato#users.sourceforge.jp>

* rx-decode.opc (DSIZE): New. double size.
(_ld): New. dmov size attribute.
(PSCALE): Add double size.
(DCR, DDR, DDRH, DDRL, DCND): New. Double FPU registers.
(SCR, SDR, SDRH, SDRL): Likewise.
(S2DR, S2CR): Likewise.
(SDD): New. double displacement.
(DL): New. Set dmov size attribute.
(rx_decode_opcode): Add RXv3 instructions.
* rx-decode.c: Regenerate.
* rx-dis.c (size_names): Add double entry.
(opsize_names): Likewise.
(double_register_names): New. Double FPU registers.
(double_register_high_names): Likewise.
(double_register_low_names): Likewise.
(double_register_control_names): Likewise.
(double_condition_names): dcmp condition.
(print_insn_rx): Add bfmov / bfmovz output.
Add double FPU output.
* config/rx-defs.h (rx_cpu_types): Add type RXV3 and RXV3FPU.
(rx_bfield): Add prototype.
(rx_post): Likewise.
* config/rx-parse.y: Add v3 instructions and Double FPU registers.
(DSIZE): Define.
(POST): Define.
(rx_check_v3): New. check v3 type.
(rx_check_dfpu): New. check have double support.
(double_condition_table): New. dcmp<cond> contiditon.
(check_condition): Multiple condition support.
(rx_lex): RXv3 instructions support.
Add parse dcmp<cond> instruction and Double FPU registers.
(immediate): Disable optimize in dmov #imm case.
(displacement): Add double displacement in dmov instraction.
* config/tc-rx.c (rx_use_conventional_section_names):
Invert default value in rx-*-linux target.
(cpu_type): Add additional ELF flags.
(cpu_type_list): Add RXv3.
(md_parse_option): Refer elf_flags from cpu_type_list.
(md_show_usage): Add rxv3 and rxv3-dfpu.
(rx_bytesT): Add post byte.
(rx_bfield): New. generate bfmov / bfmovz "imm" field.
(rx_post): New. Set instruction post byte.
(md_assemble): Add post byte.
* gas/testsuite/gas/rx/Xtod.d: New.
* gas/testsuite/gas/rx/Xtod.sm: New.
* gas/testsuite/gas/rx/bfmov.d: New.
* gas/testsuite/gas/rx/bfmov.sm: New.
* gas/testsuite/gas/rx/dabs.d: New.
* gas/testsuite/gas/rx/dabs.sm: New.
* gas/testsuite/gas/rx/dadd.d: New.
* gas/testsuite/gas/rx/dadd.sm: New.
* gas/testsuite/gas/rx/dcmp.d: New.
* gas/testsuite/gas/rx/dcmp.sm: New.
* gas/testsuite/gas/rx/ddiv.d: New.
* gas/testsuite/gas/rx/ddiv.sm: New.
* gas/testsuite/gas/rx/dmov.d: New.
* gas/testsuite/gas/rx/dmov.sm: New.
* gas/testsuite/gas/rx/dmul.d: New.
* gas/testsuite/gas/rx/dmul.sm: New.
* gas/testsuite/gas/rx/dneg.d: New.
* gas/testsuite/gas/rx/dneg.sm: New.
* gas/testsuite/gas/rx/dpopm.d: New.
* gas/testsuite/gas/rx/dpopm.sm: New.
* gas/testsuite/gas/rx/dpushm.d: New.
* gas/testsuite/gas/rx/dpushm.sm: New.
* gas/testsuite/gas/rx/dround.d: New.
* gas/testsuite/gas/rx/dround.sm: New.
* gas/testsuite/gas/rx/dsqrt.d: New.
* gas/testsuite/gas/rx/dsqrt.sm: New.
* gas/testsuite/gas/rx/dsub.d: New.
* gas/testsuite/gas/rx/dsub.sm: New.
* gas/testsuite/gas/rx/dtoX.d: New.
* gas/testsuite/gas/rx/dtoX.sm: New.
* gas/testsuite/gas/rx/macros.inc: Add double FPU registers.
* gas/testsuite/gas/rx/mvfdc.d: New.
* gas/testsuite/gas/rx/mvfdc.sm: New.
* gas/testsuite/gas/rx/mvfdr.d: New.
* gas/testsuite/gas/rx/mvfdr.sm: New.
* gas/testsuite/gas/rx/mvtdc.d: New.
* gas/testsuite/gas/rx/mvtdc.sm: New.
* gas/testsuite/gas/rx/rstr.d: New.
* gas/testsuite/gas/rx/rstr.sm: New.
* gas/testsuite/gas/rx/rx.exp: Use rxv3-dfpu option.
* gas/testsuite/gas/rx/save.d: New.
* gas/testsuite/gas/rx/save.sm: New.
* gas/testsuite/gas/rx/xor.d: New.
* gas/testsuite/gas/rx/xor.sm: Add pattern.
* elf/rx.h (EF_RX_CPU_MASK): Update new bits.
(E_FLAG_RX_V3): New RXv2 type.
* opcode/rx.h (RX_Size): Add double size.
(RX_Operand_Type): Add double FPU registers.
(RX_Opcode_ID): Add new instuctions.

rx_use_conventional_section_names

Change Summary