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hardware/intel/intel-driver


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Revisiona83bf50faa7b2c65e4ee5a4e8e58ac7a999f862e (tree)
Time2015-02-03 15:17:35
AuthorXiang, Haihao <haihao.xiang@inte...>
CommiterXiang, Haihao

Log Message

The SEND with EOT message must use R112-R127 for message payload on GEN7+

EOT message on GEN9 has used R112-R127, but the same message on GEN7-GEN8 still uses
other registers. To avoid potential issues, use R112-R127 on GEN7-GEN8 too

In additition, GEN7-GEN9 use the same 'write' message, so factor out the same
code to exa_wm_write.g7i in this patch

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>

Change Summary

Incremental Difference

--- a/src/shaders/render/Makefile.am
+++ b/src/shaders/render/Makefile.am
@@ -59,7 +59,8 @@ INTEL_G6B = \
5959 exa_wm_yuv_color_balance.g6b \
6060 exa_wm_yuv_rgb.g6b
6161
62-INTEL_G7I = $(INTEL_G4I)
62+INTEL_G7I = $(INTEL_G4I) \
63+ exa_wm_write.g7i
6364
6465 INTEL_G7A = \
6566 exa_wm_src_affine.g7a \
--- a/src/shaders/render/exa_wm_write.g7a
+++ b/src/shaders/render/exa_wm_write.g7a
@@ -23,61 +23,4 @@
2323 */
2424
2525 include(`exa_wm.g4i')
26-
27-/* header */
28-define(`data_port_msg_2_0', `g64')
29-define(`data_port_msg_2_1', `g65')
30-define(`data_port_msg_2_ind', `64')
31-
32-mov (8) data_port_msg_2_0<1>UD g0<8,8,1>UD {align1 mask_disable};
33-mov (8) data_port_msg_2_1<1>UD g1<8,8,1>UD {align1 mask_disable};
34-
35-/*
36- * Prepare data in g66-g67 for Red channel, g68-g69 for Green channel,
37- * g70-g71 for Blue and g72-g73 for Alpha channel
38- */
39-define(`slot_r_00', `g66')
40-define(`slot_r_01', `g67')
41-define(`slot_g_00', `g68')
42-define(`slot_g_01', `g69')
43-define(`slot_b_00', `g70')
44-define(`slot_b_01', `g71')
45-define(`slot_a_00', `g72')
46-define(`slot_a_01', `g73')
47-
48-mov (8) slot_r_00<1>F src_sample_r_01<8,8,1>F { align1 mask_disable };
49-mov (8) slot_r_01<1>F src_sample_r_23<8,8,1>F { align1 mask_disable };
50-
51-mov (8) slot_g_00<1>F src_sample_g_01<8,8,1>F { align1 mask_disable };
52-mov (8) slot_g_01<1>F src_sample_g_23<8,8,1>F { align1 mask_disable };
53-
54-mov (8) slot_b_00<1>F src_sample_b_01<8,8,1>F { align1 mask_disable };
55-mov (8) slot_b_01<1>F src_sample_b_23<8,8,1>F { align1 mask_disable };
56-
57-mov (8) slot_a_00<1>F src_sample_a_01<8,8,1>F { align1 mask_disable };
58-mov (8) slot_a_01<1>F src_sample_a_23<8,8,1>F { align1 mask_disable };
59-
60-send (16)
61- data_port_msg_2_ind
62- null<1>UW
63- null
64- write (
65- 0, /* binding table index */
66- 16, /* last render target(1) + slots 15:0(0) + msg type simd16 single source(000) */
67- 12, /* render target write */
68- 0, /* ignore for Ivybridge */
69- 1 /* header present */
70- )
71- mlen 10
72- rlen 0
73- { align1 EOT };
74-
75-nop;
76-nop;
77-nop;
78-nop;
79-nop;
80-nop;
81-nop;
82-nop;
83-
26+include(`exa_wm_write.g7i')
--- a/src/shaders/render/exa_wm_write.g7b
+++ b/src/shaders/render/exa_wm_write.g7b
@@ -1,14 +1,14 @@
1- { 0x00600201, 0x28000021, 0x008d0000, 0x00000000 },
2- { 0x00600201, 0x28200021, 0x008d0020, 0x00000000 },
3- { 0x00600201, 0x284003bd, 0x008d01c0, 0x00000000 },
4- { 0x00600201, 0x286003bd, 0x008d01e0, 0x00000000 },
5- { 0x00600201, 0x288003bd, 0x008d0200, 0x00000000 },
6- { 0x00600201, 0x28a003bd, 0x008d0220, 0x00000000 },
7- { 0x00600201, 0x28c003bd, 0x008d0240, 0x00000000 },
8- { 0x00600201, 0x28e003bd, 0x008d0260, 0x00000000 },
9- { 0x00600201, 0x290003bd, 0x008d0280, 0x00000000 },
10- { 0x00600201, 0x292003bd, 0x008d02a0, 0x00000000 },
11- { 0x05800031, 0x20001ca8, 0x00000800, 0x940b1000 },
1+ { 0x00600201, 0x2e000021, 0x008d0000, 0x00000000 },
2+ { 0x00600201, 0x2e200021, 0x008d0020, 0x00000000 },
3+ { 0x00600201, 0x2e4003bd, 0x008d01c0, 0x00000000 },
4+ { 0x00600201, 0x2e6003bd, 0x008d01e0, 0x00000000 },
5+ { 0x00600201, 0x2e8003bd, 0x008d0200, 0x00000000 },
6+ { 0x00600201, 0x2ea003bd, 0x008d0220, 0x00000000 },
7+ { 0x00600201, 0x2ec003bd, 0x008d0240, 0x00000000 },
8+ { 0x00600201, 0x2ee003bd, 0x008d0260, 0x00000000 },
9+ { 0x00600201, 0x2f0003bd, 0x008d0280, 0x00000000 },
10+ { 0x00600201, 0x2f2003bd, 0x008d02a0, 0x00000000 },
11+ { 0x05800031, 0x20001ca8, 0x00000e00, 0x940b1000 },
1212 { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
1313 { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
1414 { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
--- /dev/null
+++ b/src/shaders/render/exa_wm_write.g7i
@@ -0,0 +1,80 @@
1+/*
2+ * Copyright © 2010 Intel Corporation
3+ *
4+ * Permission is hereby granted, free of charge, to any person obtaining a
5+ * copy of this software and associated documentation files (the "Software"),
6+ * to deal in the Software without restriction, including without limitation
7+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8+ * and/or sell copies of the Software, and to permit persons to whom the
9+ * Software is furnished to do so, subject to the following conditions:
10+ *
11+ * The above copyright notice and this permission notice (including the next
12+ * paragraph) shall be included in all copies or substantial portions of the
13+ * Software.
14+ *
15+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21+ * IN THE SOFTWARE.
22+ *
23+ */
24+
25+/* header */
26+define(`data_port_msg_2_0', `g112')
27+define(`data_port_msg_2_1', `g113')
28+define(`data_port_msg_2_ind', `112')
29+
30+mov (8) data_port_msg_2_0<1>UD g0<8,8,1>UD {align1 mask_disable};
31+mov (8) data_port_msg_2_1<1>UD g1<8,8,1>UD {align1 mask_disable};
32+
33+/*
34+ * Prepare data in g114-g115 for Red channel, g116-g117 for Green channel,
35+ * g118-g119 for Blue and g120-g121 for Alpha channel
36+ */
37+define(`slot_r_00', `g114')
38+define(`slot_r_01', `g115')
39+define(`slot_g_00', `g116')
40+define(`slot_g_01', `g117')
41+define(`slot_b_00', `g118')
42+define(`slot_b_01', `g119')
43+define(`slot_a_00', `g120')
44+define(`slot_a_01', `g121')
45+
46+mov (8) slot_r_00<1>F src_sample_r_01<8,8,1>F { align1 mask_disable };
47+mov (8) slot_r_01<1>F src_sample_r_23<8,8,1>F { align1 mask_disable };
48+
49+mov (8) slot_g_00<1>F src_sample_g_01<8,8,1>F { align1 mask_disable };
50+mov (8) slot_g_01<1>F src_sample_g_23<8,8,1>F { align1 mask_disable };
51+
52+mov (8) slot_b_00<1>F src_sample_b_01<8,8,1>F { align1 mask_disable };
53+mov (8) slot_b_01<1>F src_sample_b_23<8,8,1>F { align1 mask_disable };
54+
55+mov (8) slot_a_00<1>F src_sample_a_01<8,8,1>F { align1 mask_disable };
56+mov (8) slot_a_01<1>F src_sample_a_23<8,8,1>F { align1 mask_disable };
57+
58+send (16)
59+ data_port_msg_2_ind
60+ null<1>UW
61+ null
62+ write (
63+ 0, /* binding table index */
64+ 16, /* last render target(1) + slots 15:0(0) + msg type simd16 single source(000) */
65+ 12, /* render target write */
66+ 0, /* ignore for Ivybridge */
67+ 1 /* header present */
68+ )
69+ mlen 10
70+ rlen 0
71+ { align1 EOT };
72+
73+nop;
74+nop;
75+nop;
76+nop;
77+nop;
78+nop;
79+nop;
80+nop;
--- a/src/shaders/render/exa_wm_write.g8a
+++ b/src/shaders/render/exa_wm_write.g8a
@@ -23,61 +23,4 @@
2323 */
2424
2525 include(`exa_wm.g4i')
26-
27-/* header */
28-define(`data_port_msg_2_0', `g64')
29-define(`data_port_msg_2_1', `g65')
30-define(`data_port_msg_2_ind', `64')
31-
32-mov (8) data_port_msg_2_0<1>UD g0<8,8,1>UD {align1 mask_disable};
33-mov (8) data_port_msg_2_1<1>UD g1<8,8,1>UD {align1 mask_disable};
34-
35-/*
36- * Prepare data in g66-g67 for Red channel, g68-g69 for Green channel,
37- * g70-g71 for Blue and g72-g73 for Alpha channel
38- */
39-define(`slot_r_00', `g66')
40-define(`slot_r_01', `g67')
41-define(`slot_g_00', `g68')
42-define(`slot_g_01', `g69')
43-define(`slot_b_00', `g70')
44-define(`slot_b_01', `g71')
45-define(`slot_a_00', `g72')
46-define(`slot_a_01', `g73')
47-
48-mov (8) slot_r_00<1>F src_sample_r_01<8,8,1>F { align1 mask_disable };
49-mov (8) slot_r_01<1>F src_sample_r_23<8,8,1>F { align1 mask_disable };
50-
51-mov (8) slot_g_00<1>F src_sample_g_01<8,8,1>F { align1 mask_disable };
52-mov (8) slot_g_01<1>F src_sample_g_23<8,8,1>F { align1 mask_disable };
53-
54-mov (8) slot_b_00<1>F src_sample_b_01<8,8,1>F { align1 mask_disable };
55-mov (8) slot_b_01<1>F src_sample_b_23<8,8,1>F { align1 mask_disable };
56-
57-mov (8) slot_a_00<1>F src_sample_a_01<8,8,1>F { align1 mask_disable };
58-mov (8) slot_a_01<1>F src_sample_a_23<8,8,1>F { align1 mask_disable };
59-
60-send (16)
61- data_port_msg_2_ind
62- null<1>UW
63- null
64- write (
65- 0, /* binding table index */
66- 16, /* last render target(1) + slots 15:0(0) + msg type simd16 single source(000) */
67- 12, /* render target write */
68- 0, /* ignore for Ivybridge */
69- 1 /* header present */
70- )
71- mlen 10
72- rlen 0
73- { align1 EOT };
74-
75-nop;
76-nop;
77-nop;
78-nop;
79-nop;
80-nop;
81-nop;
82-nop;
83-
26+include(`exa_wm_write.g7i')
--- a/src/shaders/render/exa_wm_write.g8b
+++ b/src/shaders/render/exa_wm_write.g8b
@@ -1,14 +1,14 @@
1- { 0x00600001, 0x2800020c, 0x008d0000, 0x00000000 },
2- { 0x00600001, 0x2820020c, 0x008d0020, 0x00000000 },
3- { 0x00600001, 0x28403aec, 0x008d01c0, 0x00000000 },
4- { 0x00600001, 0x28603aec, 0x008d01e0, 0x00000000 },
5- { 0x00600001, 0x28803aec, 0x008d0200, 0x00000000 },
6- { 0x00600001, 0x28a03aec, 0x008d0220, 0x00000000 },
7- { 0x00600001, 0x28c03aec, 0x008d0240, 0x00000000 },
8- { 0x00600001, 0x28e03aec, 0x008d0260, 0x00000000 },
9- { 0x00600001, 0x29003aec, 0x008d0280, 0x00000000 },
10- { 0x00600001, 0x29203aec, 0x008d02a0, 0x00000000 },
11- { 0x05800031, 0x20000a40, 0x0e000800, 0x940b1000 },
1+ { 0x00600001, 0x2e00020c, 0x008d0000, 0x00000000 },
2+ { 0x00600001, 0x2e20020c, 0x008d0020, 0x00000000 },
3+ { 0x00600001, 0x2e403aec, 0x008d01c0, 0x00000000 },
4+ { 0x00600001, 0x2e603aec, 0x008d01e0, 0x00000000 },
5+ { 0x00600001, 0x2e803aec, 0x008d0200, 0x00000000 },
6+ { 0x00600001, 0x2ea03aec, 0x008d0220, 0x00000000 },
7+ { 0x00600001, 0x2ec03aec, 0x008d0240, 0x00000000 },
8+ { 0x00600001, 0x2ee03aec, 0x008d0260, 0x00000000 },
9+ { 0x00600001, 0x2f003aec, 0x008d0280, 0x00000000 },
10+ { 0x00600001, 0x2f203aec, 0x008d02a0, 0x00000000 },
11+ { 0x05800031, 0x20000a40, 0x0e000e00, 0x940b1000 },
1212 { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
1313 { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
1414 { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
--- a/src/shaders/render/exa_wm_write.g9a
+++ b/src/shaders/render/exa_wm_write.g9a
@@ -23,60 +23,4 @@
2323 */
2424
2525 include(`exa_wm.g4i')
26-
27-/* header */
28-define(`data_port_msg_2_0', `g112')
29-define(`data_port_msg_2_1', `g113')
30-define(`data_port_msg_2_ind', `112')
31-
32-mov (8) data_port_msg_2_0<1>UD g0<8,8,1>UD {align1 mask_disable};
33-mov (8) data_port_msg_2_1<1>UD g1<8,8,1>UD {align1 mask_disable};
34-
35-/*
36- * Prepare data in g114-g115 for Red channel, g116-g117 for Green channel,
37- * g118-g119 for Blue and g120-g121 for Alpha channel
38- */
39-define(`slot_r_00', `g114')
40-define(`slot_r_01', `g115')
41-define(`slot_g_00', `g116')
42-define(`slot_g_01', `g117')
43-define(`slot_b_00', `g118')
44-define(`slot_b_01', `g119')
45-define(`slot_a_00', `g120')
46-define(`slot_a_01', `g121')
47-
48-mov (8) slot_r_00<1>F src_sample_r_01<8,8,1>F { align1 mask_disable };
49-mov (8) slot_r_01<1>F src_sample_r_23<8,8,1>F { align1 mask_disable };
50-
51-mov (8) slot_g_00<1>F src_sample_g_01<8,8,1>F { align1 mask_disable };
52-mov (8) slot_g_01<1>F src_sample_g_23<8,8,1>F { align1 mask_disable };
53-
54-mov (8) slot_b_00<1>F src_sample_b_01<8,8,1>F { align1 mask_disable };
55-mov (8) slot_b_01<1>F src_sample_b_23<8,8,1>F { align1 mask_disable };
56-
57-mov (8) slot_a_00<1>F src_sample_a_01<8,8,1>F { align1 mask_disable };
58-mov (8) slot_a_01<1>F src_sample_a_23<8,8,1>F { align1 mask_disable };
59-
60-send (16)
61- data_port_msg_2_ind
62- null<1>UW
63- null
64- write (
65- 0, /* binding table index */
66- 16, /* last render target(1) + slots 15:0(0) + msg type simd16 single source(000) */
67- 12, /* render target write */
68- 0, /* ignore for Ivybridge */
69- 1 /* header present */
70- )
71- mlen 10
72- rlen 0
73- { align1 EOT };
74-
75-nop;
76-nop;
77-nop;
78-nop;
79-nop;
80-nop;
81-nop;
82-nop;
26+include(`exa_wm_write.g7i')