Commit: 9e924b4d1a1862efb6ab20dd92dbb233f3acf19c - hardware-intel-intel-driver (git)

hardware/intel/intel-driver

Commit MetaInfo

• Revision: 9e924b4d1a1862efb6ab20dd92dbb233f3acf19c (tree)
• Time: 2016-05-09 17:52:22
• Author: Xiang, Haihao <haihao.xiang@inte...>
• Commiter: Xiang, Haihao

Log Message

Add 'struct i965_gpe_resource' and related utility functions

Signed-off-by: Xiang, Haihao <[e-mail]>
Reviewed-By: Sean V Kelley <[e-mail]>

Change Summary

• modified: src/i965_gpe_utils.c
• modified: src/i965_gpe_utils.h

Incremental Difference

--- a/src/i965_gpe_utils.c
+++ b/src/i965_gpe_utils.c
@@ -1308,3 +1308,119 @@ gen9_gpe_pipeline_end(VADriverContextP ctx,
               GEN9_FORCE_MEDIA_AWAKE_MASK);
     ADVANCE_BATCH(batch);
 }
+
+Bool
+i965_allocate_gpe_resource(dri_bufmgr *bufmgr,
+                           struct i965_gpe_resource *res,
+                           const char *name)
+{
+    res->bo = dri_bo_alloc(bufmgr, name, res->size, 4096);
+    res->map = NULL;
+
+    return (res->bo != NULL);
+}
+
+void
+i965_object_surface_to_2d_gpe_resource(struct i965_gpe_resource *res,
+                                       struct object_surface *obj_surface)
+{
+    unsigned int swizzle;
+
+    res->type = I965_GPE_RESOURCE_2D;
+    res->width = obj_surface->orig_width;
+    res->height = obj_surface->orig_height;
+    res->pitch = obj_surface->width;
+    res->size = obj_surface->size;
+    res->cb_cr_pitch = obj_surface->cb_cr_pitch;
+    res->x_cb_offset = obj_surface->x_cb_offset;
+    res->y_cb_offset = obj_surface->y_cb_offset;
+    res->bo = obj_surface->bo;
+    res->map = NULL;
+
+    dri_bo_reference(res->bo);
+    dri_bo_get_tiling(obj_surface->bo, &res->tiling, &swizzle);
+}
+
+void
+i965_dri_object_to_buffer_gpe_resource(struct i965_gpe_resource *res,
+                                       dri_bo *bo)
+{
+    unsigned int swizzle;
+
+    res->type = I965_GPE_RESOURCE_BUFFER;
+    res->width = bo->size;
+    res->height = 1;
+    res->pitch = res->width;
+    res->size = res->pitch * res->width;
+    res->bo = bo;
+    res->map = NULL;
+
+    dri_bo_reference(res->bo);
+    dri_bo_get_tiling(res->bo, &res->tiling, &swizzle);
+}
+
+void
+i965_gpe_dri_object_to_2d_gpe_resource(struct i965_gpe_resource *res,
+                                       dri_bo *bo,
+                                       unsigned int width,
+                                       unsigned int height,
+                                       unsigned int pitch)
+{
+    unsigned int swizzle;
+
+    res->type = I965_GPE_RESOURCE_2D;
+    res->width = width;
+    res->height = height;
+    res->pitch = pitch;
+    res->size = res->pitch * res->width;
+    res->bo = bo;
+    res->map = NULL;
+
+    dri_bo_reference(res->bo);
+    dri_bo_get_tiling(res->bo, &res->tiling, &swizzle);
+}
+
+void
+i965_zero_gpe_resource(struct i965_gpe_resource *res)
+{
+    if (res->bo) {
+        dri_bo_map(res->bo, 1);
+        memset(res->bo->virtual, 0, res->size);
+        dri_bo_unmap(res->bo);
+    }
+}
+
+void
+i965_free_gpe_resource(struct i965_gpe_resource *res)
+{
+    dri_bo_unreference(res->bo);
+    res->bo = NULL;
+    res->map = NULL;
+}
+
+void *
+i965_map_gpe_resource(struct i965_gpe_resource *res)
+{
+    int ret;
+
+    if (res->bo) {
+        ret = dri_bo_map(res->bo, 1);
+
+        if (ret == 0)
+            res->map = res->bo->virtual;
+        else
+            res->map = NULL;
+    } else
+        res->map = NULL;
+
+    return res->map;
+}
+
+void
+i965_unmap_gpe_resource(struct i965_gpe_resource *res)
+{
+    if (res->bo && res->map)
+        dri_bo_unmap(res->bo);
+
+    res->map = NULL;
+}

--- a/src/i965_gpe_utils.h
+++ b/src/i965_gpe_utils.h
@@ -44,6 +44,26 @@ struct i965_buffer_surface
     unsigned int pitch;
 };
 
+enum {
+    I965_GPE_RESOURCE_BUFFER = 0,
+    I965_GPE_RESOURCE_2D
+};
+
+struct i965_gpe_resource
+{
+    dri_bo *bo;
+    char *map;
+    uint32_t type;
+    uint32_t width;
+    uint32_t height;
+    uint32_t pitch;
+    uint32_t size;
+    uint32_t tiling;
+    uint32_t cb_cr_pitch;
+    uint32_t x_cb_offset;
+    uint32_t y_cb_offset;
+};
+
 struct i965_gpe_context
 {
     struct {
@@ -228,4 +248,28 @@ void gen9_gpe_pipeline_end(VADriverContextP ctx,
                              struct i965_gpe_context *gpe_context,
                              struct intel_batchbuffer *batch);
 
+Bool i965_allocate_gpe_resource(dri_bufmgr *bufmgr,
+                                struct i965_gpe_resource *res,
+                                const char *name);
+
+void i965_object_surface_to_2d_gpe_resource(struct i965_gpe_resource *res,
+                                            struct object_surface *obj_surface);
+
+void i965_dri_object_to_buffer_gpe_resource(struct i965_gpe_resource *res,
+                                            dri_bo *bo);
+
+void i965_gpe_dri_object_to_2d_gpe_resource(struct i965_gpe_resource *res,
+                                            dri_bo *bo,
+                                            unsigned int width,
+                                            unsigned int height,
+                                            unsigned int pitch);
+
+void i965_zero_gpe_resource(struct i965_gpe_resource *res);
+
+void i965_free_gpe_resource(struct i965_gpe_resource *res);
+
+void *i965_map_gpe_resource(struct i965_gpe_resource *res);
+
+void i965_unmap_gpe_resource(struct i965_gpe_resource *res);
+
 #endif /* _I965_GPE_UTILS_H_ */