hardware/intel/intel-driver
Revision | 44ed84c6fda3bb9f958a4de9304c3f4d86516b93 (tree) |
---|---|
Time | 2015-02-03 15:15:57 |
Author | Xiang, Haihao <haihao.xiang@inte...> |
Commiter | Xiang, Haihao |
Disable upper bound check for decoding on BDW+
We saw pixel corruption in stress test with the wrong up-bound address.
For simplicity, disable upper bound check in the driver.
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Tested-by: Zhao Yakui <yakui.zhao@intel.com>
Reviewed-by: Sean V Kelley <sean.v.kelley@intel.com>
@@ -282,7 +282,7 @@ gen8_mfd_ind_obj_base_addr_state(VADriverContextP ctx, | ||
282 | 282 | OUT_BCS_BATCH(batch, 0); |
283 | 283 | OUT_BCS_BATCH(batch, 0); |
284 | 284 | /* Upper bound 4-5 */ |
285 | - OUT_BCS_BATCH(batch, 0x80000000); /* must set, up to 2G */ | |
285 | + OUT_BCS_BATCH(batch, 0); | |
286 | 286 | OUT_BCS_BATCH(batch, 0); |
287 | 287 | |
288 | 288 | /* MFX indirect MV 6-10 */ |
@@ -2493,7 +2493,7 @@ gen8_jpeg_wa_ind_obj_base_addr_state(VADriverContextP ctx, | ||
2493 | 2493 | gen7_mfd_context->jpeg_wa_slice_data_bo, |
2494 | 2494 | I915_GEM_DOMAIN_INSTRUCTION, 0, |
2495 | 2495 | 0); |
2496 | - OUT_BCS_BATCH(batch, 0x80000000); /* must set, up to 2G */ | |
2496 | + OUT_BCS_BATCH(batch, 0); | |
2497 | 2497 | OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */ |
2498 | 2498 | OUT_BCS_BATCH(batch, 0); |
2499 | 2499 | OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */ |