Commit: cd7112c807c2ca461b2d635353aea1bec8ab9c7a - DocIdeas (hg)

Commit MetaInfo

• Revision: cd7112c807c2ca461b2d635353aea1bec8ab9c7a (tree)
• Time: 2023-03-25 07:06:39
• Author: Albert Mietus < albert AT mietus DOT nl >
• Commiter: Albert Mietus < albert AT mietus DOT nl >

Log Message

asis

Change Summary

• modified: CCastle/3.Design/B.Workshop/CC2Cpy/Components_and_Friends.rst
• modified: CCastle/3.Design/zz.todo.rst
• modified: CCastle/4.Blog/a.Heisenbug.rst
• add: CCastle/4.Blog/Heisenbug-sidebar-Sequence.irst
• add: CCastle/4.Blog/sieve-Sequence-OOO.puml
• add: CCastle/4.Blog/sieve-Sequence-concept.puml
• add: CCastle/4.Blog/sieve-Sequence-details.puml

Incremental Difference

diff -r 80fc934ac658 -r cd7112c807c2 CCastle/3.Design/B.Workshop/CC2Cpy/Components_and_Friends.rst
--- a/CCastle/3.Design/B.Workshop/CC2Cpy/Components_and_Friends.rst	Fri Mar 24 17:10:04 2023 +0100
+++ b/CCastle/3.Design/B.Workshop/CC2Cpy/Components_and_Friends.rst	Fri Mar 24 23:06:39 2023 +0100
@@ -3,7 +3,7 @@
 =========================================
 
 .. post::
-   :category: Castle, DesignStudy
+   :category: Castle, DesignStudy, CC2Cpy
    :tags: DRAFT
 
    Any compiler will read & parse the source, convert it into an abstract natation (like the AST) and write the result
@@ -23,9 +23,8 @@
 
 .. todo::
 
-   * Spilt the Modeling & Rendering parts; by using delegating to a ${Any}Rendering subclasses of ${Any}
    * Add (pseudo) namespaces-support, global/extern/static keyword and such (during generation)
-
+   * Better design & describe the Pre/In/PostFixes (see XXXX)
 
 Overview
 =========

diff -r 80fc934ac658 -r cd7112c807c2 CCastle/3.Design/zz.todo.rst
--- a/CCastle/3.Design/zz.todo.rst	Fri Mar 24 17:10:04 2023 +0100
+++ b/CCastle/3.Design/zz.todo.rst	Fri Mar 24 23:06:39 2023 +0100
@@ -34,8 +34,8 @@
 
 .. _TheMachinery:
 
-The Machinery
-=============
+The Machinery (ToDo)
+====================
 
 The CC-concept has abstracted the communication between components, by using ports, connections, and protocols. A
 protocol is a  “horizontal” interface: two port can be connected when they share the same protocol.
@@ -57,7 +57,7 @@
 Some example machineries
 ------------------------
 
-.. Machinery-DirectCall:
+.. _Machinery-DirectCall:
 
 DirectCall
 ~~~~~~~~~~
@@ -68,6 +68,7 @@
 
 It works great for simple single-threaded (small) applications
 
+.. _Machinery-LibDispatch:
 
 LibDispatch
 ~~~~~~~~~~~

diff -r 80fc934ac658 -r cd7112c807c2 CCastle/4.Blog/Heisenbug-sidebar-Sequence.irst
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/CCastle/4.Blog/Heisenbug-sidebar-Sequence.irst	Fri Mar 24 23:06:39 2023 +0100
@@ -0,0 +1,28 @@
+.. -*- rst -*-
+   included in  `a.Heisenbug.rst`
+
+.. sidebar::
+
+   .. tabs::
+
+      .. tab:: Conceptual
+
+         In this diagram, the order of the message in shown in a logical order. As we only show the integers that are
+         tested for (relative) prime, it looks simple and error-free.
+
+         .. uml:: ./sieve-Sequence-concept.puml
+
+      .. tab::  Out of order
+
+         But there is no garantie that the simple, conceptual order is used. By example, the Generator can be *“fast”*,
+         and produce the to-be-sieved integers faster than the Sieves handle them.
+
+         .. uml:: ./sieve-Sequence-OOO.puml
+
+      .. tab::  With details
+
+         Adding components-creation details (as well as  reconnecting) shows a
+         lot more details.  Here we added the
+         event/port-names. When studying carefully, we can already see there might be a problem when the order changes          ...
+
+         .. uml:: ./sieve-Sequence-details.puml

diff -r 80fc934ac658 -r cd7112c807c2 CCastle/4.Blog/a.Heisenbug.rst
--- a/CCastle/4.Blog/a.Heisenbug.rst	Fri Mar 24 17:10:04 2023 +0100
+++ b/CCastle/4.Blog/a.Heisenbug.rst	Fri Mar 24 23:06:39 2023 +0100
@@ -18,7 +18,7 @@
 
 
 What is a Heisenbug?
-********************
+====================
 
 The heisenbug is named to Werner Heisenberg, who described the “observer effect”: when you look closely, the behavior
 changes. The same can happen to software (bugs). The behavior apparently changes when you study -or slightly adjust-
@@ -26,15 +26,21 @@
 sequential code on slow CPU’s is less likely to have heisenbugs then concurrent code on fast multi-core systems. It’s
 also common in threaded programs.
 
+.. include:: ./Heisenbug-sidebar-Sequence.irst
+
 The sieve goes wrong
 ====================
 
-Also my standard Caste demo ‘Sieve of Eratosthenes’ can suffer from this issue. The initial version did work for years,
-and failed horrible when another “machinery” was used.
+Also my standard example ‘:ref:`Castle-TheSieve`’ can suffer from this issue. The initial version did work for years,
+but failed horrible when another “machinery” was used. After studying this, the bug is simple, and easy to fix.
 
 
 
 
- https://en.wikipedia.org/wiki/Heisenbug
+
+
+========================
+
+https://en.wikipedia.org/wiki/Heisenbug
 
 ..  LocalWords:  heisenbugs, heisenbug

diff -r 80fc934ac658 -r cd7112c807c2 CCastle/4.Blog/sieve-Sequence-OOO.puml
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/CCastle/4.Blog/sieve-Sequence-OOO.puml	Fri Mar 24 23:06:39 2023 +0100
@@ -0,0 +1,45 @@
+@startuml
+hide footbox
+title OutOfOrder (Fast generator)
+
+participant "Generator"  as G
+participant "Sieve(2)"   as S2
+participant "Sieve(3)"   as S3
+participant "Sieve(5)"   as S5
+participant "Sieve(7)"   as S7
+participant "Sieve(11)"  as S11
+
+G  -[#green]> S2:  2
+G  -[#blue]>  S2:  3
+G  -[#red]>   S2:  4
+G  -[#blue]>  S2:  5
+G  -[#red]>   S2:  6
+G  -[#blue]>  S2:  7
+G  -[#red]>   S2:  8
+G  -[#blue]>  S2:  9
+G  -[#red]>   S2: 10
+G  -[#blue]>  S2: 11
+
+activate S2
+S2 -[#green]> S3:  3
+S2 -[#blue]>  S3:  5
+S2 -[#blue]>  S3:  7
+S2 -[#red]>   S3:  9
+S2 -[#blue]>  S3: 11
+
+activate S3
+S3 -[#green]> S5:  5
+S3 -[#blue]>  S5:  7
+S3 -[#blue]>  S5: 11
+
+activate S5
+S5 -[#green]> S7:  7
+S5 -[#blue]>  S7: 11
+
+activate S7
+S7 -[#green]>S11: 11
+
+activate S11
+
+== etc ==
+@enduml

diff -r 80fc934ac658 -r cd7112c807c2 CCastle/4.Blog/sieve-Sequence-concept.puml
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/CCastle/4.Blog/sieve-Sequence-concept.puml	Fri Mar 24 23:06:39 2023 +0100
@@ -0,0 +1,50 @@
+@startuml
+hide footbox
+title Concept (sequential order)
+
+participant "Generator"  as G
+participant "Sieve(2)"   as S2
+participant "Sieve(3)"   as S3
+participant "Sieve(5)"   as S5
+participant "Sieve(7)"   as S7
+participant "Sieve(11)"  as S11
+
+G  -[#green]> S2: 2
+activate S2
+
+G  -[#blue]> S2: 3
+S2 -[#green]> S3: 3
+activate S3
+
+G  -[#red]> S2: 4
+
+G  -[#blue]> S2: 5
+S2 -[#blue]> S3: 5
+S3 -[#green]> S5: 5
+activate S5
+
+G  -[#red]> S2: 6
+
+G  -[#blue]> S2: 7
+S2 -[#blue]> S3: 7
+S3 -[#blue]> S5: 7
+S5 -[#green]> S7: 7
+activate S7
+
+G  -[#red]> S2: 8
+
+G  -[#blue]> S2: 9
+S2 -[#red]> S3: 9
+
+G  -[#red]> S2: 10
+
+
+G  -[#blue]> S2: 11
+S2 -[#blue]> S3: 11
+S3 -[#blue]> S5: 11
+S5 -[#blue]> S7: 11
+S7 -[#green]>S11: 11
+activate S11
+
+== etc ==
+@enduml

diff -r 80fc934ac658 -r cd7112c807c2 CCastle/4.Blog/sieve-Sequence-details.puml
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/CCastle/4.Blog/sieve-Sequence-details.puml	Fri Mar 24 23:06:39 2023 +0100
@@ -0,0 +1,62 @@
+@startuml
+hide footbox
+title Sieve creation details (sequantial order)
+
+participant  Main        as  M
+participant  Finder      as  F
+participant "Generator"  as  G
+
+participant "Sieve(2)"   as S2
+participant "Sieve(3)"   as S3
+participant "Sieve(5)"   as S5
+participant "Sieve(7)"   as S7
+
+
+
+G -[#purple]\\ F: try(2)
+F -\  M: found(2)
+M -\ S2: new
+activate S2
+G \\--o M: "reconneced to Sieve(2)"
+
+
+G  -[#blue]> S2: try(3)
+S2 -\\ F: try(3)
+F -\  M: found(3)
+M -\ S3: new
+activate S3
+S2 \\--o M: "reconneced to Sieve(3)"
+
+
+G  -[#red]> S2: try(4)
+
+G  -[#blue]> S2: try(5)
+S2 -[#blue]> S3: try(5)
+S3 -\\ F: found(5)
+F -\  M: found(5)
+M -\ S5: new
+activate S5
+S3 \\--o M: "reconneced to Sieve(5)"
+
+
+G  -[#red]> S2: try(6)
+
+G  -[#blue]> S2: try(7)
+S2 -[#blue]> S3: try(7)
+S3 -[#blue]> S5: try(7)
+S5 -\ G: try(7)
+F -\  M: found(7)
+M -\ S7: new
+activate S7
+S5 \\--o M: "reconneced to Sieve(7)"
+
+G  -[#red]> S2: try(8)
+
+G  -[#blue]> S2: try(9)
+S2 -[#red]> S3: try(9)
+
+G  -[#red]> S2: try(10)
+
+
+== etc ==
+@enduml