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aarch64: Fix ICE in final_scan_insn_1 [PR87839]

2021-05-07 Jakub Jelinek <jakub@redhat.com>

PR target/87839
* config/aarch64/atomics.md (aarch64_compare_and_swap<mode>): Use
rIJ constraint for aarch64_plus_operand rather than rn.

* gcc.target/aarch64/pr87839.c: New test.

libcpp: Fix up pragma preprocessing [PR100450]

Since the r0-85991-ga25a8f3be322fe0f838947b679f73d6efc2a412c
https://gcc.gnu.org/legacy-ml/gcc-patches/2008-02/msg01329.html
changes, so that we handle macros inside of pragmas that should expand
macros, during preprocessing we print those pragmas token by token,
with CPP_PRAGMA printed as
fputs ("#pragma ", print.outf);
if (space)
fprintf (print.outf, "%s %s", space, name);
else
fprintf (print.outf, "%s", name);
where name is some identifier (so e.g. print
#pragma omp parallel
or
#pragma omp for
etc.). Because it ends in an identifier, we need to handle it like
an identifier (i.e. CPP_NAME) for the decision whether a space needs
to be emitted in between that #pragma whatever or #pragma whatever whatever
and following token, otherwise the attached testcase is preprocessed as
#pragma omp forreduction(+:red)
rather than
#pragma omp for reduction(+:red)
The cpp_avoid_paste function is only called for this purpose.

2021-05-07 Jakub Jelinek <jakub@redhat.com>

PR c/100450
* lex.c (cpp_avoid_paste): Handle token1 CPP_PRAGMA like CPP_NAME.

* c-c++-common/gomp/pr100450.c: New test.

(cherry picked from commit 170c850e4bd46745e2a5130b5eb09f9fceb98416)

aarch64: Fix gcc.target/aarch64/pr99808.c for ILP32

Fix test for -mabi=ilp32

gcc/testsuite/ChangeLog:

PR target/99808
* gcc.target/aarch64/pr99808.c: Use ULL constant suffix.

aarch64: PR target/99037 Fix RTL represntation in move_lo_quad patterns

This patch fixes the RTL representation of the move_lo_quad patterns to use aarch64_simd_or_scalar_imm_zero
for the zero part rather than a vec_duplicate of zero or a const_int 0.
The expander that generates them is also adjusted so that we use and match the correct const_vector forms throughout.

Co-Authored-By: Jakub Jelinek <jakub@redhat.com>
gcc/ChangeLog:

PR target/99037
PR target/100441
* config/aarch64/aarch64-simd.md (move_lo_quad_internal_<mode>): Use
aarch64_simd_or_scalar_imm_zero to match zeroes. Remove pattern
matching const_int 0.
(move_lo_quad_internal_be_<mode>): Likewise.
(move_lo_quad_<mode>): Update for the above.
* config/aarch64/iterators.md (VQ_2E): Delete.

gcc/testsuite/ChangeLog:

PR target/99808
* gcc.target/aarch64/pr99808.c: New test.

Daily bump.

modulo-sched: skip loops with strange register defs [PR100225]

PR84878 fix adds an assertion which can fail, e.g. when stack pointer
is adjusted inside the loop. We have to prevent it and search earlier
for any 'strange' instruction. The solution is to skip the whole loop
if using 'note_stores' we found that one of hard registers is in
'df->regular_block_artificial_uses' set.

Also patch properly prohibit not single-set instruction in loop body.

gcc/ChangeLog:

PR rtl-optimization/100225
PR rtl-optimization/84878
* modulo-sched.c (sms_schedule): Use note_stores to skip loops
where we have an instruction which touches (writes) any hard
register from df->regular_block_artificial_uses set.
Allow not-single-set instruction only right before basic block
tail.

gcc/testsuite/ChangeLog:

PR rtl-optimization/100225
PR rtl-optimization/84878
* gcc.dg/pr100225.c: New test.

libgomp/ChangeLog:

* testsuite/libgomp.oacc-c-c++-common/atomic_capture-3.c: New test.

(cherry picked from commit 4cf3b10f27b1994cf4a9eb12079d85412ebc7cad)

Daily bump.

PR rtl-optimization/100263: Ensure register can change mode

For move2add_valid_value_p we also have to ask the target whether a
register can be accessed in a different mode than it was set before.

gcc/ChangeLog:

PR rtl-optimization/100263
* postreload.c (move2add_valid_value_p): Ensure register can
change mode.

(cherry picked from commit bb283170e7a1f39bf533651418daf10ad18eccfc)

tree-optimization/98786 - fix issue with phiopt and abnormals

This fixes factor_out_conditional_conversion to avoid creating overlapping
lifetimes for abnormals.

2021-01-22 Richard Biener <rguenther@suse.de>

PR tree-optimization/98786
* tree-ssa-phiopt.c (factor_out_conditional_conversion): Avoid
adding new uses of abnormals.

* gcc.dg/torture/pr98786.c: New testcase.

(cherry picked from commit 329f730fd1daa7cdae4a637244d4e215f9bb9a8c)

early-remat.c: Fix new/delete mismatch [PR100230]

This simple patch fixes a mistmatched operator new/delete in
early-remat.c which triggers ASan errors on (at least) AArch64 when
compiling SVE code.

gcc/ChangeLog:

PR rtl-optimization/100230
* early-remat.c (early_remat::sort_candidates): Use delete[]
instead of delete for array allocated with new[].

(cherry picked from commit 5d87c2251c441f056e0a44f928ffcb8a8a679b6b)

Daily bump.

nvptx: Fix up nvptx build against latest libstdc++ [PR100375]

The r12-220-gd96db15967e78d7cecea3b1cf3169ceb924678ac change
deprecated some non-standard std::pair constructors and that apparently
broke nvptx.c build, where pseudo_node_t is std::pair<struct basic_block_def *, int>
and so nullptr (or NULL) needs to be used for the first argument of the
ctors instead of 0.

2021-05-02 Jakub Jelinek <jakub@redhat.com>

PR target/100375
* config/nvptx/nvptx.c (nvptx_sese_pseudo): Use NULL instead of 0
as first argument of pseudo_node_t constructors.

(cherry picked from commit 7911a905276781c20f704f5a91b5125e0184d072)

aarch64: Fix ICE in aarch64_add_offset_1_temporaries [PR100302]

In PR94121 I've changed aarch64_add_offset_1 to use absu_hwi instead of
abs_hwi because offset can be HOST_WIDE_INT_MIN. As can be seen with
the testcase below, aarch64_add_offset_1_temporaries suffers from the same
problem and should be in sync with aarch64_add_offset_1, i.e. for
HOST_WIDE_INT_MIN it needs a temporary.

2021-04-29 Jakub Jelinek <jakub@redhat.com>

PR target/100302
* config/aarch64/aarch64.c (aarch64_add_offset_1_temporaries): Use
absu_hwi instead of abs_hwi.

(cherry picked from commit 1bb3e2c0ce6ed363c72caf814a6ba6d7b17c3e0a)

cfgcleanup: Fix -fcompare-debug issue in outgoing_edges_match [PR100254]

The following testcase fails with -fcompare-debug. The problem is that
outgoing_edges_match behaves differently between -g0 and -g, if
some load/store with REG_EH_REGION is followed by DEBUG_INSNs, the
REG_EH_REGION check is not done, while when there are no DEBUG_INSNs, it is
done.

We already compute last1 and last2 as BB_END (bb{1,2}) with skipped debug
insns and notes, so this patch just uses those.

2021-04-27 Jakub Jelinek <jakub@redhat.com>

PR rtl-optimization/100254
* cfgcleanup.c (outgoing_edges_match): Check REG_EH_REGION on
last1 and last2 insns rather than BB_END (bb1) and BB_END (bb2) insns.

* g++.dg/opt/pr100254.C: New test.

(cherry picked from commit e600df51a15b2ec7a72731921a2464ffe59cf5ab)

vmsdbgout: Remove useless register keywords

register keyword was removed in C++17, and in vmsdbgout.c it served no
useful purpose.

2021-04-26 Jakub Jelinek <jakub@redhat.com>

PR debug/100255
* vmsdbgout.c (ASM_OUTPUT_DEBUG_STRING, vmsdbgout_begin_block,
vmsdbgout_end_block, lookup_filename, vmsdbgout_source_line): Remove
register keywords.

(cherry picked from commit 297bfacdb448c0d29b8dfac2818350b90902bc75)

cprop: Fix -fcompare-debug bug in constprop_register [PR100148]

The following testcase shows different behavior between -g and -g0
in constprop_register, if a flags register setter is separated
from a conditional jump using those flags with -g by a DEBUG_INSN.
As it uses just NEXT_INSN, for -g it will look at the DEBUG_INSN which is
not a conditional jump, while otherwise it would look at the conditional
jump and call cprop_jump.

2021-04-21 Jakub Jelinek <jakub@redhat.com>

PR rtl-optimization/100148
* cprop.c (constprop_register): Use next_nondebug_insn instead of
NEXT_INSN.

* g++.dg/opt/pr100148.C: New test.

(cherry picked from commit 022f6ee3ad67ee30f62c8c2aeeb4156494f3284e)

Add missing alignment checks in epilogue loop vectorisation (PR 86877)

Epilogue loop vectorisation skips vect_enhance_data_refs_alignment
since it doesn't make sense to version or peel the epilogue loop
(that will already have happened for the main loop). But this means
that it also fails to check whether the accesses are suitably aligned
for the new vector subarch.

We don't seem to carry alignment information from the (potentially
peeled or versioned) main loop to the epilogue loop, which would be
good to fix at some point. I think we want this patch regardless,
since there's no guarantee that the alignment requirements are the
same for every subarch.

2018-09-20 Richard Sandiford <richard.sandiford@arm.com>

gcc/
PR tree-optimization/86877
* tree-vect-loop.c (vect_analyze_loop_2): Call
vect_verify_datarefs_alignment.

gcc/testsuite/
PR tree-optimization/86877
* gfortran.dg/vect/vect-8-epilogue.F90: New test.

(cherry picked from commit 508a909eca536f7f6a60af9bd7ecea761bd2e8f1)

re PR tree-optimization/86159 (g++ ICE at -O1 and above on valid code: incorrect type of vector CONSTRUCTOR elements)

2018-06-15 Richard Biener <rguenther@suse.de>

PR middle-end/86159
* tree-cfg.c (gimplify_build3): Do not strip sign conversions,
leave useless conversion stripping to force_gimple_operand_gsi.
(gimplify_build2): Likewise.
(gimplify_build1): Likewise.

* g++.dg/pr86159.C: New testcase.

(cherry picked from commit fa6852317327d978d4069175952109505204f6ae)

haifa-sched: handle fallthru edge to EXIT block (PR 85899)

2019-03-01 Alexander Monakov <amonakov@ispras.ru>

PR rtl-optimization/85899
* haifa-sched.c (find_fallthru_edge_from): Relax assert to account for
fallthru edges leading to the exit block.

* gcc.dg/pr85899.c: New test.

(cherry picked from commit 5055060066723e409519376c8e571e51cff1eb30)

re PR rtl-optimization/81025 (gcc ICE while building glibc for MIPS soft-float multi-lib variant)

2019-04-03 Jeff Law <law@redhat.com>

PR rtl-optimization/81025
* reorg.c (skip_consecutive_labels): Do not skip past a BARRIER.

(cherry picked from commit 9427422ddacdf1c2914adfb6e8edca87f250fdfc)

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