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Release 1.03
CSV-Verilog Maker II
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프로젝트 설명
CSV-Verilog Maker IIはCSVプリプロセッサ上で動作するプログラムです。
Excelで検証内容や設計内容を記載し、Verilogに変換するソースコード自動生成プログラムです。
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Pros
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CSV-CPU Maker II
1.07a
1.06
1.05
1.04
1.02
1.01
1.00
CSV-CPU Maker (Old Version)
1.02
CSV-SystemC Maker II
0.94a
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CSV-Verilog Maker II
1.28a
1.28
1.27
1.26b
1.26a
1.26
1.25
1.24
1.23
1.22
1.21
1.20d
1.20c
1.20b
1.20a
1.20
1.19a
1.19
1.18
1.17a
1.15
1.14
1.13a
CSV-Verilog Maker (Old Version)
1.00
sample
20090622-1
SystemC Source Maker
1.08
1.07
1.06
1.05
1.04
1.03
1.01
1.00
verilog_model
1.03
1.02
1.01
1.00
Verilog Source Maker
1.01
1.00
Released at 2012-06-03 19:49
verilog_model 1.03
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