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common_source_project-fm7: Commit

Common Source Code Project for Qt (a.k.a for FM-7).


Commit MetaInfo

Revisionf39e49d52d2db4fd8981b5981e6e8f6924dd8180 (tree)
Time2018-08-27 19:03:03
AuthorK.Ohta <whatisthis.sowhat@gmai...>
CommiterK.Ohta

Log Message

[VM][FMTOWNS] .

Change Summary

Incremental Difference

--- a/source/src/vm/fmtowns/towns_memory.cpp
+++ b/source/src/vm/fmtowns/towns_memory.cpp
@@ -8,7 +8,7 @@
88 */
99
1010 #include "./towns_memory.h"
11-#include "../i386.h"
11+#include "i386.h"
1212
1313 void TOWNS_MEMORY::initialize()
1414 {
@@ -19,7 +19,7 @@ void TOWNS_MEMORY::initialize()
1919
2020 vram_wait_val = 6;
2121 mem_wait_val = 3;
22-
22+
2323 memset(ram_page0, 0x00, sizeof(ram_page0));
2424 memset(ram_0f0, 0x00, sizeof(ram_0f0));
2525 memset(ram_0f8, 0x00, sizeof(ram_0f8));
@@ -52,12 +52,13 @@ void TOWNS_MEMORY::initialize()
5252 fio->Fread(msdos_rom, sizeof(msdos_rom), 1);
5353 fio->Fclose();
5454 }
55- if(fio->Fopen(create_local_path(_T("FMT_DIC.ROM")), FILEIO_READ_BINARY)) { // MSDOS
55+ if(fio->Fopen(create_local_path(_T("FMT_DIC.ROM")), FILEIO_READ_BINARY)) { // DICTIONARIES
5656 fio->Fread(dict_rom, sizeof(dict_rom), 1);
5757 fio->Fclose();
5858 }
5959 // ToDo: Will move to config.
6060 extram_size = TOWNS_EXTRAM_PAGES * 0x100000;
61+ // ToDo: Limit extram_size per VM.
6162 extram = (uint8_t *)malloc(extram_size);
6263
6364 initialize_tables();
@@ -73,573 +74,333 @@ void TOWNS_MEMORY::reset()
7374 d_cpu->set_address_mask(0xffffffff);
7475 }
7576
76-void TOWNS_MEMORY::write_data32w_page0(uint32_t addr, uint32_t data, int *wait)
77+uint32_t TOWNS_MEMORY::read_data8w(uint32_t addr, int *wait)
7778 {
78- pair_t nd;
79-
80- nd.d = data;
81- if((addr & 0xc8000) == 0xc8000) {
82- if(d_mmio != NULL) d_mmio->write_data32(addr & 0x7ffc, data, wait);
83- } else {
84- write_data8w_page0((addr & 0xffffc) + 0, nd.b.l, NULL);
85- write_data8w_page0((addr & 0xffffc) + 1, nd.b.h, wait);
86- write_data8w_page0((addr & 0xffffc) + 2, nd.b.h2, NULL);
87- write_data8w_page0((addr & 0xffffc) + 3, nd.b.h3, NULL);
79+ uint8_t *maddr;
80+ DEVICE *daddr;
81+ int udata;
82+ uint32_t mask;
83+ int wval;
84+ if(set_mapaddress(addr, false, &maddr, &daddr, &udata, &mask, &wval)) {
85+ if(maddr != NULL) {
86+ if(wait != NULL) *wait = wval;
87+ return (uint32_t)(*maddr);
88+ } else if(daddr != NULL) {
89+ return (uint32_t)(daddr->read_data8w((addr & mask) + (uint32_t)udata, wait));
90+ }
8891 }
92+ return 0xff;
8993 }
9094
91-void TOWNS_MEMORY::write_data16w_page0(uint32_t addr, uint32_t data, int *wait)
95+uint32_t TOWNS_MEMORY::read_data16w(uint32_t addr, int *wait)
9296 {
93- pair_t nd;
94- nd.d = data;
95- if((addr & 0xc8000) == 0xc8000) {
96- if(d_mmio != NULL) d_mmio->write_data32(addr & 0x7ffe, data, wait);
97- } else {
98- write_data8w_page0((addr & 0xffffe) + 0, nd.b.l, NULL);
99- write_data8w_page0((addr & 0xffffe) + 1, nd.b.h, wait);
97+ uint8_t *maddr;
98+ DEVICE *daddr;
99+ int udata;
100+ uint32_t mask;
101+ int wval;
102+ if(set_mapaddress(addr, false, &maddr, &daddr, &udata, &mask, &wval)) {
103+ if(maddr != NULL) {
104+ if(wait != NULL) *wait = wval;
105+ uiint16_t *p = (uint16_t *)maddr;
106+ return (uint32_t)(*p);
107+ } else if(daddr != NULL) {
108+ return (uint32_t)(daddr->read_data16w((addr & mask) + (uint32_t)udata, wait));
109+ }
100110 }
111+ return 0xffff;
101112 }
102113
103-void TOWNS_MEMORY::write_data8w_page0(uint32_t addr, uint32_t data, int *wait)
114+uint32_t TOWNS_MEMORY::read_data32w(uint32_t addr, int *wait)
104115 {
105- uint8_t naddr;
106- naddr = (uint8_t)((addr >> 12) & 0xff);
107- switch(naddr >> 4) {
108- case 0x0:
109- case 0x1:
110- case 0x2:
111- case 0x3:
112- case 0x4:
113- case 0x5:
114- case 0x6:
115- case 0x7:
116- case 0x8:
117- case 0x9:
118- case 0xa:
119- case 0xb: // FALLBACK
120- {
121- uint8_t *p = (uint8_t *)(&(ram_page0[addr & 0xfffff]));
122- *p = data;
123- if(wait != NULL) *wait = mem_wait_val;
124- }
125- break;
126- case 0xc:
127- if((addr & 0x0f000) < 0x08000) {
128- d_vram->write_data8w((addr & 0x7fff) + TOWNS_VRAM_OFFSET_PLANE, data, wait);
129- } else {
130- d_mmio->write_data8w((addr & 0x7fff), data, wait);
131- }
132- break;
133- case 0xd:
134- case 0xe:
135- {
136- uint32_t maddr = addr & 0x1f000;
137- if(maddr < 0x08000) {
138- // NOOP.Dictionary ROM.
139- } else if(maddr < 0x0a000) {
140- if((addr & 0x7fff) < 0x0800) {
141- uint8_t *p = (uint8_t *)(&(ram_cmos[addr & 0x07ff]));
142- *p = data;
143- if(wait != NULL) *wait = mem_wait_val; // OK?
144- } else {
145- d_vram->write_data8w((addr & 0x1fff) + TOWNS_VRAM_OFFSET_GAIJI, data, wait);
146- }
147-
148- }
149- }
150- break;
151- case 0xf:
152- if(naddr < 0xf8) {
153- uint8_t *p = (uint8_t *)(&(ram_0f0[addr & 0x7ff]));
154- *p = data;
155- if(wait != NULL) *wait = mem_wait_val; // OK?
156- } else {
157- if(!bootrom_selected) {
158- uint8_t *p = (uint8_t *)(&(ram_0f8[addr & 0x7ff]));
159- *p = data;
160- if(wait != NULL) *wait = mem_wait_val; // OK?
161- }
116+ uint8_t *maddr;
117+ DEVICE *daddr;
118+ int udata;
119+ uint32_t mask;
120+ int wval;
121+ if(set_mapaddress(addr, false, &maddr, &daddr, &udata, &mask, &wval)) {
122+ if(maddr != NULL) {
123+ if(wait != NULL) *wait = wval;
124+ uiint32_t *p = (uint32_t *)maddr;
125+ return *p;
126+ } else if(daddr != NULL) {
127+ return (uint32_t)(daddr->read_data32w((addr & mask) + (uint32_t)udata, wait));
162128 }
163- break;
164129 }
130+ return 0xffffffff;
165131 }
166132
167-
168-uint32_t TOWNS_MEMORY::read_data32w_page0(uint32_t addr, int *wait)
133+void TOWNS_MEMORY::write_data8w(uint32_t addr, uint32_t data, int *wait)
169134 {
170- pair_t nd;
171-
172- nd.d = 0x00000000;
173-
174- if((addr & 0xc8000) == 0xc8000) {
175- if(d_mmio != NULL) nd.d = d_mmio->read_data32(addr & 0x7ffc, wait);
176- } else {
177- nd.b.l = read_data8w_page0((addr & 0xffffc) + 0, NULL);
178- nd.b.h = read_data8w_page0((addr & 0xffffc) + 1, wait);
179- nd.b.h2 = read_data8w_page0((addr & 0xffffc) + 2, NULL);
180- nd.b.h3 = read_data8w_page0((addr & 0xffffc) + 3, NULL);
135+ uint8_t *maddr;
136+ DEVICE *daddr;
137+ int udata;
138+ uint32_t mask;
139+ int wval;
140+ if(set_mapaddress(addr, true, &maddr, &daddr, &udata, &mask, &wval)) {
141+ if(maddr != NULL) {
142+ if(wait != NULL) *wait = wval;
143+ *maddr = (uint8_t)data;
144+ } else if(daddr != NULL) {
145+ daddr->write_data8w((addr & mask) + (uint32_t)udata, data, wait);
146+ }
181147 }
182148 }
183149
184-uint32_t TOWNS_MEMORY::read_data16w_page0(uint32_t addr, int *wait)
185-{
186- pair_t nd;
187- nd.d = 0x00000000;
188-
189- if((addr & 0xc8000) == 0xc8000) {
190- if(d_mmio != NULL) nd.w.l = d_mmio->read_data16(addr & 0x7ffe, wait);
191- } else {
192- nd.b.l = read_data8w_page0((addr & 0xffffe) + 0, NULL);
193- nd.b.h = read_data8w_page0((addr & 0xffffe) + 1, wait);
194- }
195- return nd.d;
196-}
197150
198-uint32_t TOWNS_MEMORY::read_data8w_page0(uint32_t addr, int *wait)
151+void TOWNS_MEMORY::write_data16w(uint32_t addr, uint32_t data, int *wait)
199152 {
200- uint8_t naddr;
201- uint8_t retdata = 0xff;
202- naddr = (uint8_t)((addr >> 12) & 0xff);
203- switch(naddr >> 4) {
204- case 0x0:
205- case 0x1:
206- case 0x2:
207- case 0x3:
208- case 0x4:
209- case 0x5:
210- case 0x6:
211- case 0x7:
212- case 0x8:
213- case 0x9:
214- case 0xa:
215- case 0xb: // FALLBACK
216- {
217- uint8_t *p = (uint8_t *)(&(ram_page0[addr & 0xfffff]));
218- retdata = *p;
219- if(wait != NULL) *wait = mem_wait_val;
220- }
221- break;
222- case 0xc:
223- if((addr & 0x0f000) < 0x08000) {
224- retdata = d_vram->read_data8w((addr & 0x7fff) + TOWNS_VRAM_OFFSET_PLANE, wait);
225- } else {
226- retdata = d_mmio->read_data8w((addr & 0x7fff), wait);
227- }
228- break;
229- case 0xd:
230- case 0xe:
231- {
232- uint32_t maddr = addr & 0x1f000;
233- if(maddr < 0x08000) {
234- // NOOP.Dictionary ROM.
235- retdata = rom_dict[(addr & 0x07fff) + (dicrom_bank << 15)];
236- } else if(maddr < 0x0a000) {
237- if((addr & 0x7fff) < 0x0800) {
238- uint32_t *p = (uint32_t *)(&(ram_cmos[addr & 0x07ff]));
239- retdata = *p;
240- if(wait != NULL) *wait = mem_wait_val; // OK?
241- } else {
242- retdata = d_vram->read_data32w((addr & 0x1fff) + TOWNS_VRAM_OFFSET_GAIJI, wait);
243- }
244-
245- }
246- }
247- break;
248- case 0xf:
249- if(naddr < 0xf8) {
250- uint32_t *p = (uint32_t *)(&(ram_0f0[addr & 0x7fff]));
251- retdata = *p;
252- if(wait != NULL) *wait = mem_wait_val; // OK?
253- } else {
254- if(!bootrom_selected) {
255- uint32_t *p = (uint32_t *)(&(ram_0f8[addr & 0x7fff]));
256- retdata = *p;
257- if(wait != NULL) *wait = mem_wait_val; // OK?
258- } else {
259- uint32_t *p = (uint32_t *)(&(rom_system[(addr & 0x7fff) + 0x38000]));
260- retdata = *p;
261- if(wait != NULL) *wait = mem_wait_val; // OK?
262- }
153+ uint8_t *maddr;
154+ DEVICE *daddr;
155+ int udata;
156+ uint32_t mask;
157+ int wval;
158+ if(set_mapaddress(addr, true, &maddr, &daddr, &udata, &mask, &wval)) {
159+ if(maddr != NULL) {
160+ uint16_t *p = (uint16_t *)maddr;
161+ if(wait != NULL) *wait = wval;
162+ *p = (uint16_t)data;
163+ } else if(daddr != NULL) {
164+ daddr->write_data16w((addr & mask) + (uint32_t)udata, data, wait);
263165 }
264- break;
265166 }
266- return retdata;
267167 }
268168
269-uint32_t TOWNS_MEMORY::read_extram_data8w(uint32_t addr, int*wait)
169+void TOWNS_MEMORY::write_data32w(uint32_t addr, uint32_t data, int *wait)
270170 {
271- uint8_t retval;
272- if(extram == NULL) return 0xffffffff;
273- if(addr >= (0x00100000 + (extram_size & 0x3ff00000))) {
274- return 0xff;
275- } else { // EXTRAM_OK
276- retval = extram[(addr & 0xffffffff) - 0x00100000];
277- if(wait != NULL) *wait = mem_wait_val;
278- return (uint32_t)retval;
171+ uint8_t *maddr;
172+ DEVICE *daddr;
173+ int udata;
174+ uint32_t mask;
175+ int wval
176+ if(set_mapaddress(addr, true, &maddr, &daddr, &udata, &mask, &wval)) {
177+ if(maddr != NULL) {
178+ uint32_t *p = (uint32_t *)maddr;
179+ if(wait != NULL) *wait = wval;
180+ *p = data;
181+ } else if(daddr != NULL) {
182+ daddr->write_data32w((addr & mask) + (uint32_t)udata, data, wait);
183+ }
279184 }
280185 }
281186
282-uint32_t TOWNS_MEMORY::read_extram_data16w(uint32_t addr, int*wait)
283-{
284- uint16_t retval;
285- if(extram == NULL) return 0xffffffff;
286- if(addr >= (0x00100000 + (extram_size & 0x3ff00000))) {
287- return 0xffff;
288- } else { // EXTRAM_OK
289- uint16_t *p = (uint16_t *)(&(extram[(addr & 0xfffffffe) - 0x00100000]));
290- retval = *p;
291- if(wait != NULL) *wait = mem_wait_val;
292- return (uint32_t)retval;
293- }
294-}
295187
296-uint32_t TOWNS_MEMORY::read_extram_data32w(uint32_t addr, int*wait)
297-{
298- uint32_t retval;
299- if(extram == NULL) return 0xffffffff;
300- if(addr >= (0x00100000 + (extram_size & 0x3ff00000))) {
301- return 0xffffffff;
302- } else { // EXTRAM_OK
303- uint32_t *p = (uint32_t *)(&(extram[(addr & 0xfffffffc) - 0x00100000]));
304- retval = *p;
305- if(wait != NULL) *wait = mem_wait_val;
306- return (uint32_t)retval;
307- }
308-}
309-
310-uint32_t TOWNS_MEMORY::read_data32w(uint32_t addr, int* wait)
188+bool TOWNS_MEMORY::set_mapaddress(uint32_t addr, bool is_write, uint32_t **memory_address, DEVICE **device_address, int *userdata, uint32_t *maskdata, int *waitval)
311189 {
190+ uint8_t *retaddr = NULL;
191+ DEVICE *devaddr = NULL;
192+ uint32_t mask = 0xffffffff;
193+ bool stat = false;
194+ int udata = 0;
195+ int wait = 0;
312196 uint8_t upper_bank = (addr & 0xf0000000) >> 28;
313197 uint8_t mid_bank = (addr & 0x0f000000) >> 24;
314198 uint8_t low_bank = (addr & 0x00ff0000) >> 16;
315- addr = addr & 0xfffffffc;
316199
317200 switch(upper_bank) {
318201 case 0:
319202 {
320- if(mid_bank != 0) {
321- return read_extram_data32w(addr, wait);
322- } else {
323- {
324- if(low_bank < 0x10) {
325- return read_data32w_page0(addr, wait);
203+ if(addr < 0x100000) {
204+ uint8_t naddr = (uint8_t)((addr >> 12) & 0xff);
205+ switch(naddr >> 4) {
206+ case 0x0:
207+ case 0x1:
208+ case 0x2:
209+ case 0x3:
210+ case 0x4:
211+ case 0x5:
212+ case 0x6:
213+ case 0x7:
214+ case 0x8:
215+ case 0x9:
216+ case 0xa:
217+ case 0xb:
218+ wait = mem_wait_val;
219+ retaddr = (uint8_t *)(&(ram_page0[addr & 0xfffff]));
220+ stat = true;
221+ break;
222+ case 0xc:
223+ if((addr & 0x0f000) < 0x08000) {
224+ mask = 0x00007fff;
225+ devaddr = d_vram;
226+ udata = TOWNS_VRAM_OFFSET_PLANE_BANKED;
326227 } else {
327- return read_extram_data32w(addr, wait);
228+ mask = 0x00007fff;
229+ devaddr = d_mmio;
328230 }
329- }
330- }
331- }
332- break;
333- case 1:
334- case 2:
335- case 3:
336- return read_extram_data32w(addr, wait);
337- break;
338- case 4:
339- case 5:
340- case 6:
341- case 7:
342- // I/O extension slot
343- return 0xffffffff;
344- case 8:
345- // VRAM
346- if(addr < 0x81000000) {
347- if(d_vram != NULL) {
348- return d_vram->read_data32w(addr, data, wait);
349- }
350- return 0xffffffff;
351- } else {
352- if(addr < 0x81020000) {
353- if(d_sprite != NULL) {
354- return d_sprite->read_data32w(addr, data, wait);
355- }
356- return 0xffffffff;
357- } else {
358- // Reserve
359- return 0xffffffff;
360- }
361- }
362- break;
363- case 9:
364- case a:
365- case b:
366- // VRAM: Reserved
367- return 0xffffffff;
368- case 0xc:
369- if(addr < 0xc2000000) {
370- uint32_t cardbank = ((addr & 0x01000000) >> 24);
371- if(d_romcard[cardbank] != NULL) {
372- d_romcard[cardbank]->read_data32w((addr & 0xffffff), wait);
373- }
374- return 0xffffffff;
375- } else if(addr < 0xc2080000) {
376- uint32_t *p = (uint32_t *)(&(rom_msdos[addr & 0x7ffff]));
377- if(wait != NULL) *wait = mem_wait_val; // OK?
378- return *p;
379- } else if(addr < 0xc2100000) {
380- uint32_t *p = (uint32_t *)(&(rom_dict[addr & 0x7ffff]));
381- if(wait != NULL) *wait = mem_wait_val; // OK?
382- return *p;
383- } else if(addr < 0xc2140000) {
384- uint32_t *p = (uint32_t *)(&(rom_font[addr & 0x4ffff]));
385- if(wait != NULL) *wait = mem_wait_val; // OK?
386- return *p;
387- } else if(addr < 0xc2142000) {
388- uint32_t *p = (uint32_t *)(&(ram_cmos[addr & 0x1fff]));
389- if(wait != NULL) *wait = mem_wait_val; // OK?
390- return *p;
391- } else if(addr < 0xc2200000) {
392- // Reserve
393- return 0xffffffff;
394- } else if(addr < 0xc2201000) {
395- if(d_pcm != NULL) {
396- return d_pcm->read_data32w((addr & 0x0fff), wait);
397- }
398- return 0xffffffff;
399- } else {
400- return 0xffffffff;
401- }
402- break;
403- case 0xc:
404- case 0xd:
405- case 0xe:
406- return 0xffffffff;
407- break;
408- case 0xf:
409- if(addr < 0xfffc0000) {
410- return 0xffffffff;
411- } else {
412- uint32_t *p = (uint32_t *)(&(rom_system[addr & 0x3ffff]));
413- if(wait != NULL) *wait = mem_wait_val; // OK?
414- return *p;
415- }
416- break;
417- }
418- return 0xffffffff;
419-}
420-
421-uint32_t TOWNS_MEMORY::read_data16w(uint32_t addr, int* wait)
422-{
423- uint8_t upper_bank = (addr & 0xf0000000) >> 28;
424- uint8_t mid_bank = (addr & 0x0f000000) >> 24;
425- uint8_t low_bank = (addr & 0x00ff0000) >> 16;
426- addr = addr & 0xfffffffe;
427-
428- switch(upper_bank) {
429- case 0:
430- {
431- if(mid_bank != 0) {
432- return read_extram_data16w(addr, wait);
433- } else {
434- {
435- if(low_bank < 0x10) {
436- return read_data16w_page0(addr, wait);
231+ stat = true;
232+ break;
233+ case 0xd:
234+ case 0xe:
235+ {
236+ uint32_t maddr = addr & 0x1f000;
237+ if(maddr < 0x08000) {
238+ // Dictionary ROM.
239+ if(!is_write) {
240+ wait = vram_wait_val; // OK?
241+ retaddr = &(rom_dict[(addr & 0x07fff) + (dicrom_bank << 15)]);
242+ stat = true;
243+ }
244+ } else if(maddr < 0x0a000) {
245+ if((addr & 0x7fff) < 0x0800) {
246+ wait = mem_wait_val; // OK?
247+ if((addr & 0x01) == 0) {
248+ mask = 0x000007ff;
249+ retaddr = &(ram_cmos[addr & 0x07ff]);
250+ stat = true;
251+ }
252+ } else {
253+ wait = vram_wait_val; // OK?
254+ if((addr & 0x01) == 0) {
255+ devaddr = d_vram;
256+ udata = TOWNS_VRAM_OFFSET_GAIJI;
257+ mask = 0x0000ffff;
258+ stat = true;
259+ }
260+ }
261+
262+ }
263+ }
264+ break;
265+ case 0xf:
266+ if(naddr < 0xf8) {
267+ wait = mem_wait_val; // OK?
268+ retaddr = &(ram_0f0[addr & 0x7fff]);
269+ stat = true;
437270 } else {
438- return read_extram_data16w(addr, wait);
271+ if(!bootrom_selected) {
272+ wait = mem_wait_val; // OK?
273+ retaddr = &(ram_0f8[addr & 0x7fff]);
274+ stat = true;
275+ } else {
276+ wait = mem_wait_val; // OK?
277+ if(!is_write) {
278+ retaddr = &(rom_system[(addr & 0x7fff) + 0x38000]);
279+ stat = true;
280+ }
281+ }
439282 }
283+ break;
440284 }
441- }
442- }
443- return 0xffff;
444- break;
445- case 1:
446- case 2:
447- case 3:
448- return read_extram_data16w(addr, wait);
449- break;
450- case 4:
451- case 5:
452- case 6:
453- case 7:
454- // I/O extension slot
455- return 0xffff;
456- case 8:
457- // VRAM
458- if(addr < 0x81000000) {
459- if(d_vram != NULL) {
460- return d_vram->read_data16w(addr, data, wait);
461- }
462- return 0xffff;
463- } else {
464- if(addr < 0x81020000) {
465- if(d_sprite != NULL) {
466- return d_sprite->read_data16w(addr, data, wait);
467- }
468- return 0xffff;
469- } else {
470- // Reserve
471- return 0xffff;
472- }
473- }
474- break;
475- case 9:
476- case a:
477- case b:
478- // VRAM: Reserved
479- return 0xffff;
480- case 0xc:
481- if(addr < 0xc2000000) {
482- uint32_t cardbank = ((addr & 0x01000000) >> 24);
483- if(d_romcard[cardbank] != NULL) {
484- d_romcard[cardbank]->read_data16w((addr & 0xffffff), wait);
485- }
486- return 0xffff;
487- } else if(addr < 0xc2080000) {
488- uint16_t *p = (uint16_t *)(&(rom_msdos[addr & 0x7ffff]));
489- if(wait != NULL) *wait = mem_wait_val; // OK?
490- return *p;
491- } else if(addr < 0xc2100000) {
492- uint16_t *p = (uint16_t *)(&(rom_dict[addr & 0x7ffff]));
493- if(wait != NULL) *wait = mem_wait_val; // OK?
494- return (uint32_t)(*p);
495- } else if(addr < 0xc2140000) {
496- uint16_t *p = (uint16_t *)(&(rom_font[addr & 0x4ffff]));
497- if(wait != NULL) *wait = mem_wait_val; // OK?
498- return (uint32_t)(*p);
499- } else if(addr < 0xc2142000) {
500- uint16_t *p = (uint16_t *)(&(ram_cmos[addr & 0x1fff]));
501- if(wait != NULL) *wait = mem_wait_val; // OK?
502- return (uint32_t)(*p);
503- } else if(addr < 0xc2200000) {
504- // Reserve
505- return 0xffff;
506- } else if(addr < 0xc2201000) {
507- if(d_pcm != NULL) {
508- return d_pcm->read_data16w((addr & 0x0fff), wait);
509- }
510- return 0ffff;
511- } else {
512- return 0xffff;
513- }
514- break;
515- case 0xc:
516- case 0xd:
517- case 0xe:
518- return 0xffff;
519- break;
520- case 0xf:
521- if(addr < 0xfffc0000) {
522- return 0xffff;
523- } else {
524- uint16_t *p = (uint16_t *)(&(rom_system[addr & 0x3ffff]));
525- if(wait != NULL) *wait = mem_wait_val; // OK?
526- return (uint32_t)(*p);
527- }
528- break;
529- }
530- return 0xffff;
531-}
532-
533-uint32_t TOWNS_MEMORY::read_data8w(uint32_t addr, int* wait)
534-{
535- uint8_t upper_bank = (addr & 0xf0000000) >> 28;
536- uint8_t mid_bank = (addr & 0x0f000000) >> 24;
537- uint8_t low_bank = (addr & 0x00ff0000) >> 16;
538- switch(upper_bank) {
539- case 0:
540- {
541- if(mid_bank != 0) {
542- return read_extram_data8w(addr, wait);
543285 } else {
544- {
545- if(low_bank < 0x10) {
546- return read_data8w_page0(addr, wait);
547- } else {
548- return read_extram_data8w(addr, wait);
549- }
286+ wait = mem_wait_val; // OK?
287+ if(extram_size >= (addr - 0x100000)) {
288+ retaddr = &(extram[addr - 0x100000]);
289+ stat = true;
550290 }
551291 }
552292 }
553- return 0xff;
554293 break;
555294 case 1:
556295 case 2:
557296 case 3:
558- return read_extram_data8w(addr, wait);
297+ if(extram_size >= (addr - 0x100000)) {
298+ wait = mem_wait_val; // OK?
299+ retaddr = &(extram[addr - 0x100000]);
300+ stat = true;
301+ }
559302 break;
560303 case 4:
561304 case 5:
562305 case 6:
563306 case 7:
564307 // I/O extension slot
565- return 0xff;
308+ udata = FMTOWNS_IO_EXPAND_SLOT;
309+ mask = 0x3fffffff;
310+ wait = mem_wait_val; // OK?
311+ retaddr = NULL;
312+ stat = true;
313+ break;
566314 case 8:
567315 // VRAM
568316 if(addr < 0x81000000) {
569317 if(d_vram != NULL) {
570- return d_vram->read_data8w(addr, data, wait);
571- }
572- return 0xff;
573- } else {
574- if(addr < 0x81020000) {
575- if(d_sprite != NULL) {
576- return d_sprite->read_data8w(addr, data, wait);
318+ devaddr = d_vram;
319+ mask = 0x000fffff; // OK?
320+ if(addr < 0x80100000) {
321+ udata = TOWNS_VRAM_OFFSET_SPLIT;
322+ } else if(addr < 0x80200000) {
323+ udata = TOWNS_VRAM_OFFSET_SINGLE;
324+ } else {
325+ udata = TOWNS_VRAM_OFFSET_UNDEFINED;
577326 }
578- return 0xff;
579- } else {
580- // Reserve
581- return 0xff;
327+ wait = vram_wait_val; // OK?
328+ stat = true;
582329 }
330+ } else if(addr < 0x81020000) {
331+ mask = 0x0001ffff; // OK?
332+ devaddr = d_sprite;
333+ stat = true;
583334 }
584335 break;
585336 case 9:
586337 case a:
587338 case b:
588339 // VRAM: Reserved
589- return 0xff;
340+
341+ break;
590342 case 0xc:
591343 if(addr < 0xc2000000) {
592344 uint32_t cardbank = ((addr & 0x01000000) >> 24);
593345 if(d_romcard[cardbank] != NULL) {
594- d_romcard[cardbank]->read_data8w((addr & 0xffffff), wait);
346+ wait = mem_wait_val; // OK?
347+ devaddr = d_romcard[cardbank];
348+ stat = true;
595349 }
596- return 0xff;
597350 } else if(addr < 0xc2080000) {
598- uint8_t *p = (uint8_t *)(&(rom_msdos[addr & 0x7ffff]));
599- if(wait != NULL) *wait = mem_wait_val; // OK?
600- return *p;
351+ if(!is_write) {
352+ wait = mem_wait_val; // OK?
353+ retaddr = &(rom_msdos[addr & 0x7ffff]);
354+ stat = true;
355+ }
601356 } else if(addr < 0xc2100000) {
602- uint8_t *p = (uint8_t *)(&(rom_dict[addr & 0x7ffff]));
603- if(wait != NULL) *wait = mem_wait_val; // OK?
604- return (uint32_t)(*p);
357+ if(!is_write) {
358+ wait = mem_wait_val; // OK?
359+ retaddr = &(rom_dict[addr & 0x7ffff]);
360+ stat = true;
361+ }
605362 } else if(addr < 0xc2140000) {
606- uint8_t *p = (uint8_t *)(&(rom_font[addr & 0x4ffff]));
607- if(wait != NULL) *wait = mem_wait_val; // OK?
608- return (uint32_t)(*p);
363+ if(!is_write) {
364+ wait = mem_wait_val; // OK?
365+ retaddr = &(rom_font[addr & 0x4ffff]);
366+ stat = true;
367+ }
609368 } else if(addr < 0xc2142000) {
610- uint8_t *p = (uint8_t *)(&(ram_cmos[addr & 0x1fff]));
611- if(wait != NULL) *wait = mem_wait_val; // OK?
612- return (uint32_t)(*p);
369+ wait = mem_wait_val; // OK?
370+ retaddr = &(ram_cmos[addr & 0x1fff]);
371+ stat = true;
613372 } else if(addr < 0xc2200000) {
614373 // Reserve
615- return 0xff;
616374 } else if(addr < 0xc2201000) {
617375 if(d_pcm != NULL) {
618- return d_pcm->read_data8w((addr & 0x0fff), wait);
376+ devarrd = d_pcm;
377+ stat = true;
619378 }
620- return 0xff;
621- } else {
622- return 0xff;
623379 }
624380 break;
625381 case 0xc:
626382 case 0xd:
627383 case 0xe:
628- return 0xff;
629384 break;
630385 case 0xf:
631- if(addr < 0xfffc0000) {
632- return 0xff;
633- } else {
634- uint8_t *p = (uint8_t *)(&(rom_system[addr & 0x3ffff]));
635- if(wait != NULL) *wait = mem_wait_val; // OK?
636- return (uint32_t)(*p);
386+ if(addr >= 0xfffc0000) {
387+ if(!is_write) {
388+ wait = mem_wait_val; // OK?
389+ retaddr = &(rom_system[addr & 0x3ffff]);
390+ stat = true;
391+ }
637392 }
638393 break;
639394 }
640- return 0xff;
395+ if(memory_address != NULL) *memory_address = retaddr;
396+ if(device_address != NULL) *device_address = devaddr;
397+ if(userdata != NULL) *userdata = udata;
398+ if(maskdata != NULL) *maskdata = mask;
399+ if(waitval != NULL) *waitval = wait;
400+ return stat;
641401 }
642402
403+
643404 uint32_t TOWNS_MEMORY::read_data32(uint32_t addr)
644405 {
645406 return read_data32w(addr, NULL);
@@ -711,258 +472,9 @@ void TOWNS_MEMORY::write_data32(uint32_t addr, uint32_t data)
711472 write_data32w(addr, data, &wait);
712473 }
713474
714-void TOWNS_MEMORY::write_data8w(uint32_t addr, uint32_t data, int *wait)
715-{
716- uint32_t addr_head = (addr & 0xf0000000) >> 28;
717- uint32_t addr_mid;
718- uint32_t addr_low;
719- uint32_t ui;
720- uint8_t *pp;
721-
722- if(wait != NULL) *wait = mem_wait_val;
723- switch(addr_head) {
724- case 0x0:
725- case 0x1:
726- case 0x2:
727- case 0x3:
728- if(addr < 0x00100000) {
729- write_page0_8(addr, data, wait);
730- } else {
731- ui = (((addr - 0x00100000) & 0x3ff00000) >> 20);
732- uint8_t *p = extram_adrs[ui];
733- if(p != NULL) {
734- addr_low = addr & 0x000fffff;
735- p[addr_low] = (uint8_t)data;
736- }
737- }
738- break;
739- case 4:
740- case 5:
741- case 6:
742- case 7:
743- if(extio != NULL) extio->write_data8(addr, data);
744- break;
745- case 8:
746- if(d_vram != NULL) {
747- d_vram->write_data8(addr, data);
748- if(wait != NULL) *wait = vram_wait_val;
749- }
750- break;
751- case 9:
752- case 0x0a:
753- case 0x0b:
754- // ??
755- break;
756- case 0x0c:
757- addr_mid = (addr & 0x03fff000) >> 16 ;
758- addr_low = addr & 0x00000fff;
759- pp = write_bank_adrs_cx[addr_mid];
760- if(pp != NULL) {
761- pp[addr_low] = (uint8_t)data;
762- } else if(device_type_adrs_cx[addr_mid] != 0) {
763- switch(device_type_adrs_cx[addr_mid]) {
764- case TOWNS_MEMORY_TYPE_WAVERAM:
765- if(d_pcm != NULL) {
766- d_pcm->write_data8(addr, data);
767- }
768- break;
769- case TOWNS_MEMORY_TYPE_DICTLEARN:
770- if(d_cmos != NULL) {
771- d_cmos->write_data8(addr, data);
772- }
773- break;
774- case TOWNS_MEMORY_TYPE_FORBID:
775- default:
776- break;
777- }
778- }
779- break;
780- case 0x0d:
781- case 0x0e:
782- // ??
783- break;
784- case 0x0f:
785- // ROM, maybe unable to write.
786- break;
787- }
788-}
789-
790-void TOWNS_MEMORY::write_data16w(uint32_t addr, uint32_t data, int *wait)
791-{
792- uint32_t addr_head = (addr & 0xf0000000) >> 28;
793- uint32_t addr_low;
794- uint32_t addr_mid;
795- uint16_t *pp;
796- if(wait != NULL) *wait = mem_wait_val;
797- switch(addr_head) {
798- case 0x0:
799- case 0x1:
800- case 0x2:
801- case 0x3:
802- if(addr < 0x00100000) {
803- write_page0_16(addr, data, wait);
804- } else {
805- ui = (((addr - 0x00100000) & 0x3ff00000) >> 20);
806- uint16_t *p = (uint16_t *)extram_adrs[ui];
807- if(p != NULL) {
808- addr_low = (addr & 0x000fffff) >> 1;
809-#if __LITTLE_ENDIAN__
810- p[addr_low] = (uint16_t)data;
811-#else
812- uint8_t *p8 = (uint8_*)(&(p[addr_low]));
813- pair_t d;
814- d.d = data;
815- d.write_2bytes_le_to(p8);
816-#endif
817- }
818- }
819- break;
820- case 4:
821- case 5:
822- case 6:
823- case 7:
824- if(extio != NULL) extio->write_data16(addr, data);
825- break;
826- case 8:
827- if(d_vram != NULL) {
828- d_vram->write_data16(addr, data);
829- if(wait != NULL) *wait = mem_wait_val;
830- }
831- break;
832- case 9:
833- case 0x0a:
834- case 0x0b:
835- // ??
836- break;
837- case 0x0c:
838- addr_mid = (addr & 0x03fff000) >> 16 ;
839- addr_low = addr & 0x00000fff;
840- pp = (uint16_t *)write_bank_adrs_cx[addr_mid];
841- if(pp != NULL) {
842-#if __LITTLE_ENDIAN__
843- pp[addr_low >> 1] = (uint16_t)data;
844-#else
845- uint8_t *p8 = (uint8_*)(&(pp[addr_low]));
846- pair_t d;
847- d.d = data;
848- d.write_2bytes_le_to(p8);
849-#endif
850- } else if(device_type_adrs_cx[addr_mid] != 0) {
851- switch(device_type_adrs_cx[addr_mid]) {
852- case TOWNS_MEMORY_TYPE_WAVERAM:
853- if(d_pcm != NULL) {
854- d_pcm->write_data8(addr, data);
855- }
856- break;
857- case TOWNS_MEMORY_TYPE_DICTLEARN:
858- if(d_cmos != NULL) {
859- d_cmos->write_data8(addr, data);
860- }
861- break;
862- case TOWNS_MEMORY_TYPE_FORBID:
863- default:
864- break;
865- }
866- }
867- break;
868- case 0x0d:
869- case 0x0e:
870- // ??
871- break;
872- case 0x0f:
873- // ROM, maybe unable to write.
874- break;
875- }
876-}
877-
878-void TOWNS_MEMORY::write_data32w(uint32_t addr, uint32_t data, int *wait)
879-{
880- uint32_t addr_head = (addr & 0xf0000000) >> 28;
881- uint32_t addr_low;
882- uint32_t addr_mid;
883- uint32_t *pp;
884- if(wait != NULL) *wait = mem_wait_val;
885- switch(addr_head) {
886- case 0x0:
887- case 0x1:
888- case 0x2:
889- case 0x3:
890- if(addr < 0x00100000) {
891- write_page0_32(addr, data, wait);
892- } else {
893- ui = (((addr - 0x00100000) & 0x3ff00000) >> 20);
894- uint32_t *p = (uint32_t *)extram_adrs[ui];
895- if(p != NULL) {
896- addr_low = (addr & 0x000fffff) >> 2;
897-#if __LITTLE_ENDIAN__
898- p[addr_low] = data;
899-#else
900- uint8_t *p8 = (uint8_*)(&(p[addr_low]));
901- pair_t d;
902- d.d = data;
903- d.write_4bytes_le_to(p8);
904-#endif
905- }
906- }
907- break;
908- case 4:
909- case 5:
910- case 6:
911- case 7:
912- if(extio != NULL) extio->write_data32(addr, data);
913- break;
914- case 8:
915- if(d_vram != NULL) {
916- d_vram->write_data32(addr, data);
917- if(wait != NULL) *wait = vram_wait_val;
918- }
919- break;
920- case 9:
921- case 0x0a:
922- case 0x0b:
923- // ??
924- break;
925- case 0x0c:
926- addr_mid = (addr & 0x03fff000) >> 16 ;
927- addr_low = (addr & 0x00000fff >> 2);
928- pp = (uint32_t *)write_bank_adrs_cx[addr_mid];
929- if(pp != NULL) {
930-#if __LITTLE_ENDIAN__
931- pp[addr_low >> 2] = data;
932-#else
933- uint8_t *p8 = (uint8_*)(&(pp[addr_low]));
934- pair_t d;
935- d.d = data;
936- d.write_4bytes_le_to(p8);
937-#endif
938- } else if(device_type_adrs_cx[addr_mid] != 0) {
939- switch(device_type_adrs_cx[addr_mid]) {
940- case TOWNS_MEMORY_TYPE_WAVERAM:
941- if(d_pcm != NULL) {
942- d_pcm->write_data8(addr, data);
943- }
944- break;
945- case TOWNS_MEMORY_TYPE_DICTLEARN:
946- if(d_cmos != NULL) {
947- d_cmos->write_data8(addr, data);
948- }
949- break;
950- case TOWNS_MEMORY_TYPE_FORBID:
951- default:
952- break;
953- }
954- }
955- break;
956- case 0x0d:
957- case 0x0e:
958- // ??
959- break;
960- case 0x0f:
961- // ROM, maybe unable to write.
962- break;
963- }
964-}
475+#if 0
965476
477+// ToDo: Inter operability
966478 uint32_t TOWNS_MEMORY::read_page0_8(uint32_t addr, int *wait)
967479 {
968480
@@ -1056,7 +568,7 @@ uint32_t TOWNS_MEMORY::read_page0_8(uint32_t addr, int *wait)
1056568 }
1057569 return 0xff;
1058570 }
1059-
571+#endif
1060572
1061573 uint32_t TOWNS_MEMORY::read_data8(uint32_t addr)
1062574 {
@@ -1076,330 +588,6 @@ uint32_t TOWNS_MEMORY::read_data32(uint32_t addr)
1076588 return read_data32w(addr, &wait);
1077589 }
1078590
1079-uint32_t TOWNS_MEMORY::read_data8w(uint32_t addr, int *wait)
1080-{
1081- uint32_t addr_head = (addr & 0xf0000000) >> 28;
1082- uint32_t addr_mid;
1083- uint32_t addr_low;
1084- uint32_t ui;
1085- uint8_t *pp;
1086-
1087- if(wait != NULL) *wait = mem_wait_val;
1088- switch(addr_head) {
1089- case 0x00:
1090- case 0x01:
1091- case 0x02:
1092- case 0x03:
1093- if(addr < 0x00100000) {
1094- return read_page0_8(addr, wait);
1095- } else {
1096- ui = (((addr - 0x00100000) & 0x3ff00000) >> 20);
1097- pp = extram_adrs[ui];
1098- if(pp != NULL) {
1099- addr_low = addr & 0x000fffff;
1100- return pp[addr_low];
1101- }
1102- }
1103- return 0xff;
1104- break;
1105- case 0x04:
1106- case 0x05:
1107- case 0x06:
1108- case 0x07:
1109- if(extio != NULL) return extio->read_data8(addr);
1110- break;
1111- case 0x08:
1112- if(d_vram != NULL) {
1113- if(wait != NULL) *wait = vram_wait_val;
1114- return d_vram->read_data8(addr);
1115- }
1116- break;
1117- case 0x09:
1118- case 0x0a:
1119- case 0x0b:
1120- return 0xff;
1121- // ??
1122- break;
1123- case 0x0c:
1124- addr_mid = (addr & 0x03fff000) >> 12 ;
1125- pp = read_bank_adrs_cx[addr_mid];
1126- if(pp != NULL) {
1127- addr_low = addr & 0x00000fff;
1128- return pp[addr_low];
1129- } else if(device_type_adrs_cx[addr_mid] != 0) {
1130- switch(device_type_adrs_cx[addr_mid]) {
1131- case TOWNS_MEMORY_TYPE_WAVERAM:
1132- if(d_pcm != NULL) {
1133- return d_pcm->read_data8((addr & 0x0ffe));
1134- }
1135- break;
1136- case TOWNS_MEMORY_TYPE_DICTLEARN:
1137- if(d_cmos != NULL) {
1138- return d_cmos->read_data8((addr & 0x0ffe));
1139- }
1140- break;
1141- case TOWNS_MEMORY_TYPE_FORBID:
1142- default:
1143- return 0xff;
1144- break;
1145- }
1146- return 0xff;
1147- } else {
1148- return 0xff;
1149- }
1150- break;
1151- case 0x0d:
1152- case 0x0e:
1153- // ??
1154- return 0xff;
1155- break;
1156- case 0x0f:
1157- // ROM, maybe unable to write.
1158- if(addr < 0xfffc0000) {
1159- return 0xff;
1160- } else {
1161- pp = system_rom;
1162- addr_low = addr - 0xfffc0000;
1163- return (uint32_t)pp[addr_low];
1164- }
1165- break;
1166- }
1167- return 0xff;
1168-}
1169-
1170-uint32_t TOWNS_MEMORY::read_data16w(uint32_t addr, int *wait)
1171-{
1172- uint32_t addr_head = (addr & 0xf0000000) >> 28;
1173- uint32_t addr_mid;
1174- uint32_t addr_low;
1175- uint32_t ui;
1176- uint16_t *pp;
1177-
1178-
1179- if(wait != NULL) *wait = mem_wait_val;
1180- switch(addr_head) {
1181- case 0x00:
1182- case 0x01:
1183- case 0x02:
1184- case 0x03:
1185- if(addr < 0x00100000) {
1186- return read_page0_16(addr, wait);
1187- } else {
1188- ui = (((addr - 0x00100000) & 0x3ff00000) >> 20);
1189- pp = (uint16_t *)extram_adrs[ui];
1190- if(pp != NULL) {
1191-#ifdef __LITTLE_ENDIAN__
1192- addr_low = (addr & 0x000fffff) >> 1;
1193- return pp[addr_low];
1194-#else
1195- pair_t d;
1196- uint8 *p8 = (uint8 *)pp;
1197- addr_low = addr & 0x000ffffe;
1198- d.read_2bytes_le_from(&(p8[addr_low]));
1199- return d.d;
1200-#endif
1201- }
1202- }
1203- return 0xffffffff;
1204- break;
1205- case 0x04:
1206- case 0x05:
1207- case 0x06:
1208- case 0x07:
1209- if(extio != NULL) return extio->read_data16(addr);
1210- break;
1211- case 0x08:
1212- if(d_vram != NULL) {
1213- if(wait != NULL) *wait = vram_wait_val;
1214- return d_vram->read_data16(addr);
1215- }
1216- break;
1217- case 0x09:
1218- case 0x0a:
1219- case 0x0b:
1220- return 0xffffffff;
1221- // ??
1222- break;
1223- case 0x0c:
1224- addr_mid = (addr & 0x03fff000) >> 12 ;
1225- pp = (uint16_t *)read_bank_adrs_cx[addr_mid];
1226- if(pp != NULL) {
1227-#ifdef __LITTLE_ENDIAN__
1228- addr_low = (addr & 0x00000fff) >> 1;
1229- return pp[addr_low];
1230-#else
1231- pair_t d;
1232- uint8 *p8 = (uint8 *)pp;
1233- addr_low = addr & 0x00000ffe;
1234- d.read_2bytes_le_from(&(p8[addr_low]));
1235- return d.d;
1236-#endif
1237- } else if(device_type_adrs_cx[addr_mid] != 0) {
1238- switch(device_type_adrs_cx[addr_mid]) {
1239- case TOWNS_MEMORY_TYPE_WAVERAM:
1240- if(d_pcm != NULL) {
1241- return d_pcm->read_data8((addr & 0x0ffe));
1242- }
1243- break;
1244- case TOWNS_MEMORY_TYPE_DICTLEARN:
1245- if(d_cmos != NULL) {
1246- return d_cmos->read_data8((addr & 0x0ffe));
1247- }
1248- break;
1249- case TOWNS_MEMORY_TYPE_FORBID:
1250- default:
1251- return 0xffff;
1252- break;
1253- }
1254- return 0xffff;
1255- } else {
1256- return 0xffff;
1257- }
1258- break;
1259- case 0x0d:
1260- case 0x0e:
1261- // ??
1262- return 0xffff;
1263- break;
1264- case 0x0f:
1265- // ROM, maybe unable to write.
1266- if(addr < 0xfffc0000) {
1267- return 0xffff;
1268- } else {
1269-#ifdef __LITTLE_ENDIAN__
1270- pp = (uint16_t *)system_rom;
1271- addr_low = (addr - 0xfffc0000) >> 1;
1272- return (uint32_t)pp[addr_low];
1273-#else
1274- pair_t d;
1275- uint8_t *p8;
1276- addr_low = (addr - 0xfffc0000) & 0x3fffe;
1277- p8 = &(system_rom[addr_low]);
1278- d.read_2bytes_le_from(p8);
1279- return d.d;
1280-#endif
1281- }
1282- break;
1283- }
1284- return 0xffff;
1285-}
1286-
1287-uint32_t TOWNS_MEMORY::read_data32w(uint32_t addr, int *wait)
1288-{
1289- uint32_t addr_head = (addr & 0xf0000000) >> 28;
1290- uint32_t addr_mid;
1291- uint32_t addr_low;
1292- uint32_t ui;
1293- uint32_t *pp;
1294-
1295- if(wait != NULL) *wait = mem_wait_val;
1296- switch(addr_head) {
1297- case 0x00:
1298- case 0x01:
1299- case 0x02:
1300- case 0x03:
1301- if(addr < 0x00100000) {
1302- return read_page0_32(addr);
1303- } else {
1304- ui = (((addr - 0x00100000) & 0x3ff00000) >> 20);
1305- pp = (uint32_t *)extram_adrs[ui];
1306- if(pp != NULL) {
1307-#ifdef __LITTLE_ENDIAN__
1308- addr_low = (addr & 0x000fffff) >> 2;
1309- return pp[addr_low];
1310-#else
1311- pair_t d;
1312- uint8 *p8 = (uint8 *)pp;
1313- addr_low = addr & 0x000ffffc;
1314- d.read_4bytes_le_from(&(p8[addr_low]));
1315- return d.d;
1316-#endif
1317- }
1318- }
1319- return 0xffffffff;
1320- break;
1321- case 0x04:
1322- case 0x05:
1323- case 0x06:
1324- case 0x07:
1325- if(extio != NULL) return extio->read_data32(addr);
1326- break;
1327- case 0x08:
1328- if(d_vram != NULL) {
1329- if(wait != NULL) *wait = vram_wait_val;
1330- return d_vram->read_data32(addr);
1331- }
1332- break;
1333- case 0x09:
1334- case 0x0a:
1335- case 0x0b:
1336- return 0xffffffff;
1337- // ??
1338- break;
1339- case 0x0c:
1340- addr_mid = (addr & 0x03fff000) >> 12 ;
1341- pp = (uint32_t *)read_bank_adrs_cx[addr_mid];
1342- if(pp != NULL) {
1343-#ifdef __LITTLE_ENDIAN__
1344- addr_low = (addr & 0x00000fff) >> 2;
1345- return pp[addr_low];
1346-#else
1347- pair_t d;
1348- uint8 *p8 = (uint8 *)pp;
1349- addr_low = addr & 0x00000ffc;
1350- d.read_4bytes_le_from(&(p8[addr_low]));
1351- return d.d;
1352-#endif
1353- } else if(device_type_adrs_cx[addr_mid] != 0) {
1354- switch(device_type_adrs_cx[addr_mid]) {
1355- case TOWNS_MEMORY_TYPE_WAVERAM:
1356- if(d_pcm != NULL) {
1357- return d_pcm->read_data8((addr & 0x0ffc));
1358- }
1359- break;
1360- case TOWNS_MEMORY_TYPE_DICTLEARN:
1361- if(d_cmos != NULL) {
1362- return d_cmos->read_data8((addr & 0x0ffc));
1363- }
1364- break;
1365- case TOWNS_MEMORY_TYPE_FORBID:
1366- default:
1367- return 0xffffffff;
1368- break;
1369- }
1370- return 0xffffffff;
1371- } else {
1372- return 0xffffffff;
1373- }
1374- break;
1375- case 0x0d:
1376- case 0x0e:
1377- // ??
1378- return 0xffffffff;
1379- break;
1380- case 0x0f:
1381- // ROM, maybe unable to write.
1382- if(addr < 0xfffc0000) {
1383- return 0xffffffff;
1384- } else {
1385-#ifdef __LITTLE_ENDIAN__
1386- pp = (uint32_t *)system_rom;
1387- addr_low = (addr - 0xfffc0000) >> 2;
1388- return pp[addr_low];
1389-#else
1390- pair_t d;
1391- uint8_t *p8;
1392- addr_low = (addr - 0xfffc0000) & 0x3fffc;
1393- p8 = &(system_rom[addr_low]);
1394- d.read_4bytes_le_from(p8);
1395- return d.d;
1396-#endif
1397- }
1398- break;
1399- }
1400- return 0xffffffff;
1401-}
1402-
1403591 void TOWNS_MEMORY::write_dma_data8(uint32_t addr, uint32_t data)
1404592 {
1405593 int wait;
@@ -1617,8 +805,11 @@ void TOWNS_MEMORY::update_dma_addr_mask()
1617805 }
1618806 }
1619807
1620-#define STATE_VERSION 1
808+#define STATE_VERSION 2
1621809
810+void TOWNS_MEMORY::decl_state()
811+{
812+}
1622813 void TOWNS_MEMORY::save_state(FILEIO* state_fio)
1623814 {
1624815 state_fio->FputUint32(STATE_VERSION);
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