Common Source Code Project for Qt (a.k.a for FM-7).
| Revision | 0ab5a189ee3adf3db1e27fd3ba21d0230e6d02a1 (tree) |
|---|---|
| Time | 2020-02-19 00:15:06 |
| Author | K.Ohta <whatisthis.sowhat@gmai...> |
| Commiter | K.Ohta |
[VM][FMTOWNS][CDROM][WIP] Has read a first sector, but overwritten by another sector (;_;)
source/src/vm/fmtowns/cdc.cpp (diff)
source/src/vm/fmtowns/cdc.h (diff) source/src/vm/fmtowns/fmtowns.cpp (diff) source/src/vm/fmtowns/towns_cdrom.cpp (diff) source/src/vm/fmtowns/towns_cdrom.h (diff) source/src/vm/fmtowns/towns_dmac.cpp (diff) source/src/vm/fmtowns/towns_dmac.h (diff) source/src/vm/scsi_dev.cpp (diff)| @@ -28,6 +28,7 @@ namespace FMTOWNS { | ||
| 28 | 28 | #define EVENT_POLL_BUS_FREE 7 |
| 29 | 29 | #define EVENT_CDC_RESET 8 |
| 30 | 30 | #define EVENT_WAIT_CMD_REQ_OFF 9 |
| 31 | +#define EVENT_CDC_STATUS 10 | |
| 31 | 32 | |
| 32 | 33 | void CDC::set_context_scsi_host(SCSI_HOST* dev) |
| 33 | 34 | { |
| @@ -68,8 +69,8 @@ void CDC::reset() | ||
| 68 | 69 | dma_intr = false; |
| 69 | 70 | submpu_intr = false; |
| 70 | 71 | |
| 71 | - dma_transfer = false; | |
| 72 | - pio_transfer = true; | |
| 72 | + dma_transfer = true; | |
| 73 | + pio_transfer = false; | |
| 73 | 74 | command_type_play = false; // false = status command |
| 74 | 75 | stat_reply_intr = false; |
| 75 | 76 | req_status = false; |
| @@ -103,6 +104,11 @@ void CDC::reset() | ||
| 103 | 104 | cancel_event(this, event_wait_req); |
| 104 | 105 | event_wait_req = -1; |
| 105 | 106 | } |
| 107 | + if(event_cdc_status > -1) { | |
| 108 | + cancel_event(this, event_cdc_status); | |
| 109 | + event_cdc_status = -1; | |
| 110 | + } | |
| 111 | + buffer_count = -1; | |
| 106 | 112 | // d_scsi_host->reset(); |
| 107 | 113 | d_scsi_host->write_signal(SIG_SCSI_RST, 1, 1); |
| 108 | 114 | d_scsi_host->write_signal(SIG_SCSI_ATN, 0, 1); |
| @@ -136,6 +142,7 @@ void CDC::initialize() | ||
| 136 | 142 | event_enqueue_cmd = -1; |
| 137 | 143 | event_wait_req = -1; |
| 138 | 144 | event_wait_cmd_req_off = -1; |
| 145 | + event_cdc_status = -1; | |
| 139 | 146 | } |
| 140 | 147 | |
| 141 | 148 | void CDC::release() |
| @@ -212,6 +219,11 @@ bool CDC::check_data_in() | ||
| 212 | 219 | return (!(cd_status) && !(msg_status) && (io_status)); |
| 213 | 220 | } |
| 214 | 221 | |
| 222 | +bool CDC::check_status() | |
| 223 | +{ | |
| 224 | + return ((cd_status) && !(msg_status) && !(io_status)); | |
| 225 | +} | |
| 226 | + | |
| 215 | 227 | void CDC::select_unit_on() |
| 216 | 228 | { |
| 217 | 229 | out_debug_log("BUS FREE->SEL ON"); |
| @@ -245,13 +257,15 @@ void CDC::prologue_command_phase() | ||
| 245 | 257 | if(check_command_phase()) { |
| 246 | 258 | out_debug_log("COMMAND PHASE"); |
| 247 | 259 | accept_command = true; |
| 248 | - cancel_event(this, event_poll_cmd); | |
| 260 | + if(event_poll_cmd > -1) { | |
| 261 | + cancel_event(this, event_poll_cmd); | |
| 262 | + } | |
| 249 | 263 | event_poll_cmd = -1; |
| 250 | 264 | if(event_enqueue_cmd > -1) { |
| 251 | 265 | cancel_event(this, event_enqueue_cmd); |
| 252 | 266 | } |
| 253 | 267 | if(left_cmdqueue < CDC_COMMAND_QUEUE_LENGTH) { |
| 254 | -// d_scsi_host->write_signal(SIG_SCSI_SEL, 1, 1); | |
| 268 | + d_scsi_host->write_signal(SIG_SCSI_SEL, 1, 1); | |
| 255 | 269 | start_enqueue_command(); |
| 256 | 270 | } |
| 257 | 271 |
| @@ -261,6 +275,10 @@ void CDC::prologue_command_phase() | ||
| 261 | 275 | void CDC::event_callback(int id, int error) |
| 262 | 276 | { |
| 263 | 277 | switch(id) { |
| 278 | + case EVENT_CDC_STATUS: | |
| 279 | + write_signal(SIG_TOWNS_CDC_CDROM_DONE, 1, 1); | |
| 280 | + event_cdc_status = -1; | |
| 281 | + break; | |
| 264 | 282 | case EVENT_CDC_RESET: |
| 265 | 283 | d_scsi_host->write_signal(SIG_SCSI_RST, 0, 1); |
| 266 | 284 | break; |
| @@ -281,7 +299,7 @@ void CDC::event_callback(int id, int error) | ||
| 281 | 299 | } |
| 282 | 300 | break; |
| 283 | 301 | case EVENT_ENQUEUE_CMD: |
| 284 | - if((scsi_req_status) && (cd_status) && !(msg_status) && !(io_status)) { | |
| 302 | + if((scsi_req_status) && (check_command_phase())) { | |
| 285 | 303 | if((accept_command) && (left_cmdqueue < CDC_COMMAND_QUEUE_LENGTH)) { |
| 286 | 304 | data_in_status = false; |
| 287 | 305 | uint8_t val = cmdqueue[current_cmdqueue].command[cmdqueue[current_cmdqueue].cmd_write_ptr]; |
| @@ -325,7 +343,7 @@ void CDC::event_callback(int id, int error) | ||
| 325 | 343 | current_cmdqueue++; |
| 326 | 344 | current_cmdqueue = current_cmdqueue & (CDC_COMMAND_QUEUE_LENGTH - 1); |
| 327 | 345 | d_scsi_host->write_signal(SIG_SCSI_ACK, 0, 1); |
| 328 | - register_event(this, EVENT_WAIT_REQ, 1.0, true, &event_wait_req); | |
| 346 | + register_event(this, EVENT_WAIT_REQ, 1.0e6 / 300.0e3, true, &event_wait_req); | |
| 329 | 347 | } else { |
| 330 | 348 | // Continue |
| 331 | 349 | if(event_enqueue_cmd > -1) { |
| @@ -336,45 +354,56 @@ void CDC::event_callback(int id, int error) | ||
| 336 | 354 | } |
| 337 | 355 | } |
| 338 | 356 | case EVENT_WAIT_REQ: |
| 339 | - if((scsi_req_status)) { | |
| 340 | 357 | #if 0 |
| 341 | - if(!(cd_status) && !(msg_status) && (io_status)) { // DATA IN | |
| 342 | - out_debug_log("DATA IN"); | |
| 343 | - data_in_status = true; | |
| 344 | - if(!(pio_transfer) && (dma_transfer)) { | |
| 345 | - // WAIT FOR DRQ, NOT EVENT. | |
| 346 | - cancel_event(this, event_wait_req); | |
| 347 | - event_wait_req = -1; | |
| 348 | - } else if((pio_transfer) && !(dma_transfer)) { | |
| 349 | - data_reg = d_scsi_host->read_dma_io8(0); | |
| 350 | -// data_in_status = false; | |
| 351 | - // WAIT FOR DRQ, NOT EVENT. | |
| 352 | -// cancel_event(this, event_wait_req); | |
| 353 | -// event_wait_req = -1; | |
| 354 | - } | |
| 355 | - } else | |
| 356 | -#endif | |
| 357 | - if(((cd_status) && !(msg_status) && (io_status)) ||// STATUS | |
| 358 | - ((cd_status) && (msg_status) && (io_status))) { // MSG IN | |
| 359 | - data_in_status = true; | |
| 360 | - if(!(pio_transfer) && (dma_transfer)) { | |
| 361 | - //uint8_t val = d_scsi_host->read_dma_io8(0); | |
| 362 | - //out_debug_log(_T("STATUS DATA=%02X"), val); | |
| 363 | - d_dmac->write_signal(SIG_UPD71071_CH3, 0xff, 0xff); | |
| 364 | - //data_reg = val; | |
| 365 | - // WAIT FOR DRQ, NOT EVENT. | |
| 366 | - cancel_event(this, event_wait_req); | |
| 367 | - event_wait_req = -1; | |
| 368 | - } else if((pio_transfer) && !(dma_transfer)) { | |
| 369 | - data_reg = d_scsi_host->read_dma_io8(0); | |
| 370 | - out_debug_log(_T("STATUS DATA=%02X"), data_reg); | |
| 371 | - d_scsi_host->write_signal(SIG_SCSI_ACK, 1, 1); | |
| 372 | - // WAIT FOR DRQ, NOT EVENT. | |
| 373 | -// cancel_event(this, event_wait_req); | |
| 374 | -// event_wait_req = -1; | |
| 375 | - } | |
| 376 | - } else { // ToDo: implement DATA OUT, MSG OUT and COMMAND | |
| 377 | - } | |
| 358 | + if((scsi_req_status)) { | |
| 359 | + if((check_data_in()) && (busy_status)) { | |
| 360 | + if(dma_transfer) { // DATA IN and DMA TRANSFER | |
| 361 | + if(buffer_count < 0) { | |
| 362 | + // Timeout or read ended | |
| 363 | + //dma_transfer = false; | |
| 364 | + //pio_transter = false; | |
| 365 | + //if(event_wait_req > -1) { | |
| 366 | + // cancel_event(this, event_wait_req); | |
| 367 | + // event_wait_req = true; | |
| 368 | + //} | |
| 369 | + } else { | |
| 370 | + d_dmac->write_signal(SIG_UPD71071_CH3, 0xff, 0xff); | |
| 371 | + buffer_count++; | |
| 372 | + if(buffer_count >= 2048) { | |
| 373 | + //data_reg = d_scsi_host->read_dma_io8(0); | |
| 374 | + if(check_status()) { | |
| 375 | + // END OF READING | |
| 376 | + extra_status = 0; | |
| 377 | + write_status(0x06, 0x00, 0x00, 0x00); | |
| 378 | + pio_transfer = false; | |
| 379 | + dma_transfer = false; | |
| 380 | + write_signal(SIG_TOWNS_CDC_IRQ, 1, 1); | |
| 381 | + buffer_count = -1; | |
| 382 | + submpu_ready = true; | |
| 383 | + if(event_wait_req > -1) { | |
| 384 | + cancel_event(this, event_wait_req); | |
| 385 | + event_wait_req = true; | |
| 386 | + } | |
| 387 | + } else { | |
| 388 | + // Try to next | |
| 389 | + extra_status = 0; | |
| 390 | + write_status(0x22, 0x00, 0x00, 0x00); | |
| 391 | + write_signal(SIG_TOWNS_CDC_IRQ, 1, 1); | |
| 392 | + //submpu_ready = true; | |
| 393 | + pio_transfer = false; | |
| 394 | + dma_transfer = true; | |
| 395 | + buffer_count = 0; | |
| 396 | + } | |
| 397 | + } | |
| 398 | + } | |
| 399 | + } else { | |
| 400 | + // PIO TRANSFER | |
| 401 | + if(event_wait_req > -1) { | |
| 402 | + cancel_event(this, event_wait_req); | |
| 403 | + event_wait_req = true; | |
| 404 | + } | |
| 405 | + } | |
| 406 | + } | |
| 378 | 407 | } else { |
| 379 | 408 | // BUS FREE |
| 380 | 409 | // d_scsi_host->write_signal(SIG_SCSI_SEL, 0, 1); |
| @@ -382,6 +411,12 @@ void CDC::event_callback(int id, int error) | ||
| 382 | 411 | // event_wait_req = -1; |
| 383 | 412 | // EOL |
| 384 | 413 | } |
| 414 | +#else | |
| 415 | + if(event_wait_req > -1) { | |
| 416 | + cancel_event(this, event_wait_req); | |
| 417 | + event_wait_req = true; | |
| 418 | + } | |
| 419 | +#endif | |
| 385 | 420 | break; |
| 386 | 421 | } |
| 387 | 422 | } |
| @@ -438,10 +473,15 @@ void CDC::write_io8(uint32_t address, uint32_t data) | ||
| 438 | 473 | if((data & 0x08) != 0) { |
| 439 | 474 | dma_transfer = false; |
| 440 | 475 | pio_transfer = true; |
| 476 | + buffer_count = 0; | |
| 441 | 477 | } |
| 442 | 478 | if((data & 0x10) != 0) { |
| 443 | 479 | dma_transfer = true; |
| 444 | 480 | pio_transfer = false; |
| 481 | + if(buffer_count < 0) { | |
| 482 | + buffer_count = 0; | |
| 483 | + // Read speed | |
| 484 | + } | |
| 445 | 485 | } |
| 446 | 486 | w_regs[address & 0x0f] = data; |
| 447 | 487 | break; |
| @@ -458,7 +498,8 @@ uint32_t CDC::read_io8(uint32_t address) | ||
| 458 | 498 | /* |
| 459 | 499 | * 04C0h : Master status register |
| 460 | 500 | */ |
| 461 | - uint32_t val = 0xff; | |
| 501 | + uint32_t val = 0; | |
| 502 | +// val = (uint32_t)(stat_fifo->read_not_remove(0) & 0xff); | |
| 462 | 503 | switch(address & 0x0f) { |
| 463 | 504 | case 0x0: //Master status |
| 464 | 505 | { |
| @@ -472,7 +513,9 @@ uint32_t CDC::read_io8(uint32_t address) | ||
| 472 | 513 | } |
| 473 | 514 | break; |
| 474 | 515 | case 0x2: // Status register |
| 516 | +// val = (uint32_t)(stat_fifo->read_not_remove(0) & 0xff); | |
| 475 | 517 | val = (uint32_t)(stat_fifo->read() & 0xff); |
| 518 | + out_debug_log(_T("STATUS=%02X"), val); | |
| 476 | 519 | if(stat_fifo->empty()) { |
| 477 | 520 | has_status = false; |
| 478 | 521 | if(extra_status != 0) { |
| @@ -524,9 +567,9 @@ uint32_t CDC::read_io8(uint32_t address) | ||
| 524 | 567 | } |
| 525 | 568 | break; |
| 526 | 569 | default: |
| 527 | - if(extra_status == 7) { | |
| 528 | - d_cdrom->write_signal(SIG_TOWNS_CDROM_SET_STAT_TRACK, 0x01, 0x01); | |
| 529 | - } | |
| 570 | +// if(extra_status == 7) { | |
| 571 | +// d_cdrom->write_signal(SIG_TOWNS_CDROM_SET_STAT_TRACK, 0x01, 0x01); | |
| 572 | +// } | |
| 530 | 573 | if((extra_status & 0x01) != 0) { |
| 531 | 574 | uint32_t adr_control = d_cdrom->read_signal(SIG_TOWNS_CDROM_GET_ADR); |
| 532 | 575 | write_status(0x16, ((adr_control & 0x0f) << 4) | ((adr_control >> 4) & 0x0f), TO_BCD((extra_status / 2) - 2), 0x00); |
| @@ -543,7 +586,7 @@ uint32_t CDC::read_io8(uint32_t address) | ||
| 543 | 586 | break; |
| 544 | 587 | } |
| 545 | 588 | } |
| 546 | - case 0x06: // CDDA status | |
| 589 | + case 0x06: // READ CDDA status | |
| 547 | 590 | { |
| 548 | 591 | switch(extra_status) { |
| 549 | 592 | case 1: // Get current track |
| @@ -579,14 +622,48 @@ uint32_t CDC::read_io8(uint32_t address) | ||
| 579 | 622 | write_status(0x11, 0x00, 0x00, 0x00); |
| 580 | 623 | extra_status = 0; |
| 581 | 624 | break; |
| 625 | + case 0x85: | |
| 626 | + write_status(0x12, 0x00, 0x00, 0x00); | |
| 627 | + extra_status = 0; | |
| 628 | + break; | |
| 582 | 629 | } |
| 630 | + } else { | |
| 631 | + has_status = false; | |
| 583 | 632 | } |
| 584 | 633 | } |
| 634 | +// stat_fifo->read(); // Increment read pointer | |
| 635 | + if(stat_fifo->empty()) { | |
| 636 | + //stat_fifo->clear(); // | |
| 637 | + } | |
| 585 | 638 | break; |
| 586 | 639 | case 0x4: // |
| 587 | - val = data_reg; | |
| 588 | 640 | if((pio_transfer)) { |
| 589 | - data_reg = d_scsi_host->read_dma_io8(0); | |
| 641 | + if((scsi_req_status) && (check_data_in()) && (busy_status)) { | |
| 642 | + data_reg = d_scsi_host->read_dma_io8(0); | |
| 643 | + buffer_count++; | |
| 644 | + if(buffer_count >= 2048) { | |
| 645 | + if(check_status()) { | |
| 646 | + // END OF READING | |
| 647 | + extra_status = 0; | |
| 648 | + write_status(0x06, 0x00, 0x00, 0x00); | |
| 649 | + pio_transfer = false; | |
| 650 | + dma_transfer = false; | |
| 651 | + write_signal(SIG_TOWNS_CDC_IRQ, 1, 1); | |
| 652 | + buffer_count = -1; | |
| 653 | + submpu_ready = true; | |
| 654 | + } else { | |
| 655 | + // Try to next | |
| 656 | + extra_status = 0; | |
| 657 | + write_status(0x21, 0x00, 0x00, 0x00); | |
| 658 | + write_signal(SIG_TOWNS_CDC_IRQ, 1, 1); | |
| 659 | + //submpu_ready = true; | |
| 660 | + pio_transfer = true; | |
| 661 | + dma_transfer = false; | |
| 662 | + buffer_count = 0; | |
| 663 | + } | |
| 664 | + } | |
| 665 | + } | |
| 666 | + val = data_reg; | |
| 590 | 667 | // out_debug_log(_T("PIO READ DATA=%02X"), val); |
| 591 | 668 | } |
| 592 | 669 | break; |
| @@ -641,23 +718,35 @@ void CDC::read_cdrom(bool req_reply) | ||
| 641 | 718 | write_status(0x01, 0x00, 0x00, 0x00); |
| 642 | 719 | return; |
| 643 | 720 | } |
| 721 | +// __remain = ((lba2 - lba1) >> 2) + 1; | |
| 644 | 722 | __remain = lba2 - lba1; |
| 645 | 723 | //seek_time = get_seek_time(lba1); |
| 646 | 724 | uint8_t command[16] = {0}; |
| 725 | + extra_status = 0; | |
| 726 | +#if 0 | |
| 727 | + command[0] = SCSI_CMD_READ6; | |
| 728 | + command[1] = (uint8_t)((lba1 / 0x10000) & 0x1f); | |
| 729 | + command[2] = (uint8_t)((lba1 / 0x100) & 0xff); | |
| 730 | + command[3] = (uint8_t)(lba1 & 0xff); | |
| 731 | + command[4] = (uint8_t) (__remain % 0x100); | |
| 732 | + enqueue_cmdqueue(6, command); | |
| 733 | +#else | |
| 734 | + out_debug_log(_T("LOGICAL BLOCK SIZE=%d"), d_cdrom->logical_block_size()); | |
| 647 | 735 | command[0] = SCSI_CMD_READ12; |
| 648 | 736 | command[1] = 0; |
| 649 | 737 | command[2] = 0; |
| 650 | - command[3] = m1; | |
| 651 | - command[4] = s1; | |
| 652 | - command[5] = f1; | |
| 653 | - | |
| 738 | + command[2] = (uint8_t)((lba1 / 0x1000000) & 0xff); | |
| 739 | + command[3] = (uint8_t)((lba1 / 0x10000) & 0xff); | |
| 740 | + command[4] = (uint8_t)((lba1 / 0x100) & 0xff); | |
| 741 | + command[5] = (uint8_t)(lba1 & 0xff); | |
| 654 | 742 | command[6] = 0; |
| 655 | 743 | command[7] = (uint8_t)((__remain / 0x10000) & 0xff); |
| 656 | 744 | command[8] = (uint8_t)((__remain / 0x100) & 0xff); |
| 657 | 745 | command[9] = (uint8_t) (__remain % 0x100); |
| 658 | 746 | |
| 659 | 747 | enqueue_cmdqueue(12, command); |
| 660 | - | |
| 748 | +#endif | |
| 749 | +#if 0 | |
| 661 | 750 | if(req_reply) { |
| 662 | 751 | extra_status = 2; |
| 663 | 752 | write_status(0x00, 0x00, 0x00, 0x00); |
| @@ -669,7 +758,8 @@ void CDC::read_cdrom(bool req_reply) | ||
| 669 | 758 | write_status(0x22, 0x00, 0x00, 0x00); |
| 670 | 759 | } |
| 671 | 760 | } |
| 672 | -// submpu_ready = false; | |
| 761 | +#endif | |
| 762 | + submpu_ready = false; | |
| 673 | 763 | } |
| 674 | 764 | |
| 675 | 765 | void CDC::stop_cdda(bool req_reply) |
| @@ -830,7 +920,7 @@ void CDC::play_cdda(bool req_reply) | ||
| 830 | 920 | // submpu_ready = false; |
| 831 | 921 | } |
| 832 | 922 | |
| 833 | -void CDC::write_status(uint8_t a, uint8_t b, uint8_t c, uint8_t d) | |
| 923 | +void CDC::write_status(uint8_t a, uint8_t b, uint8_t c, uint8_t d, bool immediately) | |
| 834 | 924 | { |
| 835 | 925 | has_status = true; |
| 836 | 926 | stat_fifo->clear(); |
| @@ -838,13 +928,16 @@ void CDC::write_status(uint8_t a, uint8_t b, uint8_t c, uint8_t d) | ||
| 838 | 928 | stat_fifo->write(b); |
| 839 | 929 | stat_fifo->write(c); |
| 840 | 930 | stat_fifo->write(d); |
| 841 | - if(stat_reply_intr) { | |
| 842 | - submpu_intr = true; | |
| 843 | - if(!(submpu_intr_mask)) { | |
| 844 | - write_signals(&output_submpu_intr, 0xffffffff); | |
| 845 | - } | |
| 846 | - submpu_ready = true; | |
| 931 | + if(event_cdc_status > -1) { | |
| 932 | + cancel_event(this, event_cdc_status); | |
| 933 | + event_cdc_status = -1; | |
| 934 | + } | |
| 935 | + if(immediately) { | |
| 936 | + event_callback(EVENT_CDC_STATUS, 0); | |
| 937 | + } else { | |
| 938 | + register_event(this, EVENT_CDC_STATUS, 1000.0, false, &event_cdc_status); | |
| 847 | 939 | } |
| 940 | + out_debug_log(_T("STATUS=%02X %02X %02X %02X"), a, b, c, d); | |
| 848 | 941 | } |
| 849 | 942 | |
| 850 | 943 | void CDC::enqueue_command_play(uint8_t cmd) |
| @@ -858,7 +951,6 @@ void CDC::enqueue_command_play(uint8_t cmd) | ||
| 858 | 951 | } |
| 859 | 952 | } else { |
| 860 | 953 | has_status = false; |
| 861 | -// d_scsi_host->write_dma_io8(0, 0x81); // SELECT SCSI 0 | |
| 862 | 954 | switch(cmd & 0x1f) { |
| 863 | 955 | case 0x00: // SEEK |
| 864 | 956 | out_debug_log(_T("CMD SEEK (%02X)"), cmd); |
| @@ -877,6 +969,7 @@ void CDC::enqueue_command_play(uint8_t cmd) | ||
| 877 | 969 | break; |
| 878 | 970 | case 0x02: // READ (Mode1) |
| 879 | 971 | out_debug_log(_T("CMD READ MODE1 (%02X)"), cmd); |
| 972 | + d_cdrom->set_read_mode(false); // MAKE CDROM to MODE1(2048 bytes / sector) | |
| 880 | 973 | read_cdrom(req_status); |
| 881 | 974 | break; |
| 882 | 975 | case 0x04: // PLAY CDDA |
| @@ -969,20 +1062,48 @@ void CDC::write_signal(int ch, uint32_t data, uint32_t mask) | ||
| 969 | 1062 | { |
| 970 | 1063 | switch(ch) { |
| 971 | 1064 | case SIG_TOWNS_CDC_DRQ: |
| 972 | -// out_debug_log(_T("SIG_TOWNS_CDC_DRQ")); | |
| 1065 | +// out_debug_log(_T("SIG_TOWNS_CDC_DRQ %02X %02X"), data, mask); | |
| 973 | 1066 | if((data & mask) != 0) { |
| 974 | 1067 | if((dma_transfer) ) { |
| 975 | 1068 | software_transfer_phase = false; |
| 976 | - out_debug_log(_T("DRQ/DMA")); | |
| 977 | - if((scsi_req_status) && (check_data_in())) { | |
| 978 | - out_debug_log(_T("SEND DMAREQ to DMA3")); | |
| 1069 | +// out_debug_log(_T("DRQ/DMA")); | |
| 1070 | +// d_scsi_host->write_signal(SIG_SCSI_ACK, 0, 1); | |
| 1071 | + //if((scsi_req_status) && (check_data_in())) { | |
| 979 | 1072 | d_dmac->write_signal(SIG_UPD71071_CH3, 0xff, 0xff); |
| 980 | - } | |
| 1073 | + buffer_count++; | |
| 1074 | +// out_debug_log(_T("SEND DMAREQ to DMA3 COUNT=%d"), buffer_count); | |
| 1075 | + if(buffer_count >= 2048) { | |
| 1076 | + if(check_status()) { | |
| 1077 | + // END OF READING | |
| 1078 | + extra_status = 0; | |
| 1079 | + write_status(0x06, 0x00, 0x00, 0x00, true); | |
| 1080 | + write_signal(SIG_TOWNS_CDC_IRQ, 1, 1); | |
| 1081 | + buffer_count = -1; | |
| 1082 | + submpu_ready = true; | |
| 1083 | + if(event_wait_req > -1) { | |
| 1084 | + cancel_event(this, event_wait_req); | |
| 1085 | + event_wait_req = true; | |
| 1086 | + } | |
| 1087 | + out_debug_log(_T("TRANSFER COMPLETED")); | |
| 1088 | + } else { | |
| 1089 | + // Try to next | |
| 1090 | + extra_status = 0; | |
| 1091 | + write_status(0x22, 0x00, 0x00, 0x00, true); | |
| 1092 | + write_signal(SIG_TOWNS_CDC_IRQ, 1, 1); | |
| 1093 | + buffer_count = -1; | |
| 1094 | + out_debug_log(_T("SEEK TO NEXT SECTOR")); | |
| 1095 | + } | |
| 1096 | + } | |
| 1097 | + //} | |
| 981 | 1098 | } else if((pio_transfer) ) { |
| 982 | 1099 | software_transfer_phase = true; |
| 983 | 1100 | } else { |
| 984 | 1101 | software_transfer_phase = false; |
| 985 | 1102 | } |
| 1103 | + } else { | |
| 1104 | + if((dma_transfer) ) { | |
| 1105 | + d_dmac->write_signal(SIG_UPD71071_CH3, 0x00, 0xff); | |
| 1106 | + } | |
| 986 | 1107 | } |
| 987 | 1108 | break; |
| 988 | 1109 | case SIG_TOWNS_CDC_CDROM_DONE: |
| @@ -996,13 +1117,18 @@ void CDC::write_signal(int ch, uint32_t data, uint32_t mask) | ||
| 996 | 1117 | } |
| 997 | 1118 | break; |
| 998 | 1119 | case SIG_TOWNS_CDC_IRQ: |
| 999 | - dma_intr = ((data & mask) != 0); | |
| 1000 | - if((dma_intr & dma_intr_mask)) { | |
| 1001 | - if(stat_reply_intr) { | |
| 1002 | - write_signals(&output_dma_intr, 0xffffffff); | |
| 1120 | + { | |
| 1121 | + bool backup = dma_intr; | |
| 1122 | + dma_intr = ((data & mask) != 0); | |
| 1123 | + if(dma_intr == backup) break; | |
| 1124 | + if((dma_intr & dma_intr_mask)) { | |
| 1125 | + if(stat_reply_intr) { | |
| 1126 | + write_signals(&output_dma_intr, 0xffffffff); | |
| 1127 | + } | |
| 1128 | + out_debug_log(_T("IRQ")); | |
| 1129 | + } else if(!(dma_intr) && (dma_intr_mask)) { | |
| 1130 | + write_signals(&output_dma_intr, 0x00000000); | |
| 1003 | 1131 | } |
| 1004 | - } else if(!(dma_intr) && (dma_intr_mask)) { | |
| 1005 | - write_signals(&output_dma_intr, 0x00000000); | |
| 1006 | 1132 | } |
| 1007 | 1133 | break; |
| 1008 | 1134 | case SIG_TOWNS_CDC_BSY: |
| @@ -1115,6 +1241,7 @@ bool CDC::process_state(FILEIO* state_fio, bool loading) | ||
| 1115 | 1241 | state_fio->StateValue(cmdqueue[i].cmd_table_size); |
| 1116 | 1242 | state_fio->StateValue(cmdqueue[i].cmd_write_ptr); |
| 1117 | 1243 | } |
| 1244 | + state_fio->StateValue(buffer_count); | |
| 1118 | 1245 | |
| 1119 | 1246 | state_fio->StateValue(event_cdrom_sel); |
| 1120 | 1247 | state_fio->StateValue(event_poll_cmd); |
| @@ -1122,6 +1249,8 @@ bool CDC::process_state(FILEIO* state_fio, bool loading) | ||
| 1122 | 1249 | state_fio->StateValue(event_wait_req); |
| 1123 | 1250 | state_fio->StateValue(event_wait_cmd_req_off); |
| 1124 | 1251 | |
| 1252 | + state_fio->StateValue(event_cdc_status); | |
| 1253 | + | |
| 1125 | 1254 | return true; |
| 1126 | 1255 | |
| 1127 | 1256 | } |
| @@ -81,25 +81,28 @@ protected: | ||
| 81 | 81 | |
| 82 | 82 | bool accept_command; |
| 83 | 83 | bool req_status; |
| 84 | + int buffer_count; | |
| 84 | 85 | |
| 85 | 86 | int event_cdrom_sel; |
| 86 | 87 | int event_poll_cmd; |
| 87 | 88 | int event_enqueue_cmd; |
| 88 | 89 | int event_wait_req; |
| 89 | 90 | int event_wait_cmd_req_off; |
| 91 | + int event_cdc_status; | |
| 90 | 92 | |
| 91 | 93 | virtual void read_cdrom(bool req_reply); |
| 92 | 94 | virtual void stop_cdda(bool req_reply); |
| 93 | 95 | virtual void stop_cdda2(bool req_reply); |
| 94 | 96 | virtual void unpause_cdda(bool rea_reply); |
| 95 | 97 | virtual void play_cdda(bool req_reply); |
| 96 | - virtual void write_status(uint8_t a, uint8_t b, uint8_t c, uint8_t d); | |
| 98 | + virtual void __FASTCALL write_status(uint8_t a, uint8_t b, uint8_t c, uint8_t d, bool immediately = false); | |
| 97 | 99 | virtual void enqueue_command_play(uint8_t cmd); |
| 98 | 100 | virtual void enqueue_command_status(uint8_t cmd); |
| 99 | 101 | |
| 100 | 102 | bool check_bus_free(); |
| 101 | 103 | bool check_command_phase(); |
| 102 | 104 | bool check_data_in(); |
| 105 | + bool check_status(); | |
| 103 | 106 | void select_unit_on(); |
| 104 | 107 | void select_unit_off(); |
| 105 | 108 | void select_unit_off2(); |
| @@ -349,7 +349,7 @@ VM::VM(EMU* parent_emu) : VM_TEMPLATE(parent_emu) | ||
| 349 | 349 | cdrom->set_context_interface(cdc_scsi); |
| 350 | 350 | cdc->set_context_scsi_host(cdc_scsi); |
| 351 | 351 | cdc_scsi->set_context_target(cdrom); |
| 352 | - cdrom->set_context_done(cdc, SIG_TOWNS_CDC_CDROM_DONE, 1); | |
| 352 | +// cdrom->set_context_done(cdc, SIG_TOWNS_CDC_CDROM_DONE, 1); | |
| 353 | 353 | |
| 354 | 354 | cdc->set_context_cdrom(cdrom); |
| 355 | 355 | cdc->set_context_dmac(dma); |
| @@ -253,7 +253,6 @@ void TOWNS_CDROM::start_command() | ||
| 253 | 253 | case SCSI_CMD_READ10: |
| 254 | 254 | case SCSI_CMD_READ12: |
| 255 | 255 | SCSI_CDROM::start_command(); |
| 256 | - set_subq(); // First | |
| 257 | 256 | break; |
| 258 | 257 | case 0xff: |
| 259 | 258 | // End of List |
| @@ -371,7 +370,7 @@ void TOWNS_CDROM::set_subq(void) | ||
| 371 | 370 | subq_buffer->write(TO_BCD((msf_abs >> 8) & 0xff)); // S (absolute) |
| 372 | 371 | subq_buffer->write(TO_BCD((msf_abs >> 0) & 0xff)); // F (absolute) |
| 373 | 372 | // transfer length |
| 374 | - remain = subq_buffer->count(); | |
| 373 | + //remain = subq_buffer->count(); | |
| 375 | 374 | // set first data |
| 376 | 375 | // change to data in phase |
| 377 | 376 | //set_phase_delay(SCSI_PHASE_DATA_IN, 10.0); |
| @@ -379,9 +378,9 @@ void TOWNS_CDROM::set_subq(void) | ||
| 379 | 378 | //write_signals(&output_subq_overrun, (subq_buffer->empty()) ? 0x00000000 : 0xffffffff); // OK? |
| 380 | 379 | subq_buffer->clear(); |
| 381 | 380 | // transfer length |
| 382 | - remain = subq_buffer->count(); | |
| 381 | + //remain = subq_buffer->count(); | |
| 383 | 382 | set_dat(is_device_ready() ? SCSI_STATUS_GOOD : SCSI_STATUS_CHKCOND); |
| 384 | - //set_phase_delay(SCSI_PHASE_STATUS, 10.0); | |
| 383 | + set_phase_delay(SCSI_PHASE_STATUS, 10.0); | |
| 385 | 384 | } |
| 386 | 385 | return; |
| 387 | 386 | } |
| @@ -103,6 +103,10 @@ public: | ||
| 103 | 103 | { |
| 104 | 104 | return cdda_status; |
| 105 | 105 | } |
| 106 | + void set_read_mode(bool is_mode2) | |
| 107 | + { | |
| 108 | + read_mode = is_mode2; | |
| 109 | + } | |
| 106 | 110 | }; |
| 107 | 111 | |
| 108 | 112 | } |
| @@ -27,6 +27,10 @@ void TOWNS_DMAC::write_io8(uint32_t addr, uint32_t data) | ||
| 27 | 27 | dma_high_address = (data & 0xff) << 24; |
| 28 | 28 | return; |
| 29 | 29 | break; |
| 30 | +// case 0x08: | |
| 31 | +// cmd = (cmd & 0xff00) | (data & 0xfb); | |
| 32 | +// return; | |
| 33 | +// break; | |
| 30 | 34 | default: |
| 31 | 35 | break; |
| 32 | 36 | } |
| @@ -42,7 +46,7 @@ uint32_t TOWNS_DMAC::read_io8(uint32_t addr) | ||
| 42 | 46 | } |
| 43 | 47 | return UPD71071::read_io8(addr); |
| 44 | 48 | } |
| 45 | - | |
| 49 | +#if 0 | |
| 46 | 50 | // Note: DATABUS will be 16bit wide. 20200131 K.O |
| 47 | 51 | void TOWNS_DMAC::do_dma_verify_16bit(int c) |
| 48 | 52 | { |
| @@ -143,7 +147,7 @@ void TOWNS_DMAC::do_dma_mem_to_dev_16bit(int c) | ||
| 143 | 147 | // update temporary register |
| 144 | 148 | tmp = val; |
| 145 | 149 | } |
| 146 | - | |
| 150 | +#endif | |
| 147 | 151 | |
| 148 | 152 | void TOWNS_DMAC::do_dma_inc_dec_ptr_8bit(int c) |
| 149 | 153 | { |
| @@ -217,6 +221,7 @@ void TOWNS_DMAC::write_signal(int id, uint32_t data, uint32_t mask) | ||
| 217 | 221 | |
| 218 | 222 | void TOWNS_DMAC::write_via_debugger_data8(uint32_t addr, uint32_t data) |
| 219 | 223 | { |
| 224 | + out_debug_log(_T("WRITE 8BIT ADDR %08X to DATA:%02X"), addr, data); | |
| 220 | 225 | d_mem->write_dma_data8(addr & dma_addr_mask, data); |
| 221 | 226 | } |
| 222 | 227 |
| @@ -227,6 +232,7 @@ uint32_t TOWNS_DMAC::read_via_debugger_data8(uint32_t addr) | ||
| 227 | 232 | |
| 228 | 233 | void TOWNS_DMAC::write_via_debugger_data16(uint32_t addr, uint32_t data) |
| 229 | 234 | { |
| 235 | +// out_debug_log(_T("WRITE 16BIT DATA:%04X"), data); | |
| 230 | 236 | d_mem->write_dma_data16(addr & dma_addr_mask, data); |
| 231 | 237 | } |
| 232 | 238 |
| @@ -18,9 +18,9 @@ protected: | ||
| 18 | 18 | uint32_t dma_addr_mask; |
| 19 | 19 | uint32_t dma_high_address; |
| 20 | 20 | |
| 21 | - virtual void __FASTCALL do_dma_verify_16bit(int c); | |
| 22 | - virtual void __FASTCALL do_dma_dev_to_mem_16bit(int c); | |
| 23 | - virtual void __FASTCALL do_dma_mem_to_dev_16bit(int c); | |
| 21 | +// virtual void __FASTCALL do_dma_verify_16bit(int c); | |
| 22 | +// virtual void __FASTCALL do_dma_dev_to_mem_16bit(int c); | |
| 23 | +// virtual void __FASTCALL do_dma_mem_to_dev_16bit(int c); | |
| 24 | 24 | virtual void __FASTCALL do_dma_inc_dec_ptr_8bit(int c); |
| 25 | 25 | virtual void __FASTCALL do_dma_inc_dec_ptr_16bit(int c); |
| 26 | 26 | public: |
| @@ -248,6 +248,7 @@ void SCSI_DEV::write_signal(int id, uint32_t data, uint32_t mask) | ||
| 248 | 248 | // update buffer |
| 249 | 249 | if(buffer->count() == 0) { |
| 250 | 250 | int length = remain > SCSI_BUFFER_SIZE ? SCSI_BUFFER_SIZE : (int)remain; |
| 251 | + out_debug_log(_T("LOAD BUFFER to %d bytes"), length); | |
| 251 | 252 | if(!read_buffer(length)) { |
| 252 | 253 | // change to status phase |
| 253 | 254 | set_dat(SCSI_STATUS_CHKCOND); |
| @@ -713,15 +714,16 @@ void SCSI_DEV::start_command() | ||
| 713 | 714 | case SCSI_CMD_READ12: |
| 714 | 715 | // start position |
| 715 | 716 | position = command[2] * 0x1000000 + command[3] * 0x10000 + command[4] * 0x100 + command[5]; |
| 716 | - out_debug_log(_T("Command: Read 12-byte LBA=%d BLOCKS=%d\n"), position, command[6] * 0x1000000 + command[7] * 0x10000 + command[8] * 0x100 + command[9]); | |
| 717 | - position *= physical_block_size(); | |
| 718 | 717 | // transfer length |
| 719 | 718 | remain = command[6] * 0x1000000 + command[7] * 0x10000 + command[8] * 0x100 + command[9]; |
| 719 | + out_debug_log(_T("Command: Read 12-byte LBA=%d BLOCKS=%d PBS=%d LBS=%d\n"), position, remain, physical_block_size(), logical_block_size()); | |
| 720 | + position *= physical_block_size(); | |
| 720 | 721 | remain *= logical_block_size(); |
| 721 | 722 | if(remain != 0) { |
| 722 | 723 | // read data buffer |
| 723 | 724 | buffer->clear(); |
| 724 | 725 | int length = remain > SCSI_BUFFER_SIZE ? SCSI_BUFFER_SIZE : (int)remain; |
| 726 | + out_debug_log(_T("LOAD BUFFER to %d bytes"), length); | |
| 725 | 727 | if(!read_buffer(length)) { |
| 726 | 728 | // change to status phase |
| 727 | 729 | set_dat(SCSI_STATUS_CHKCOND); |
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