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chibios: Commit


Commit MetaInfo

Revision2871 (tree)
Time2011-04-09 07:15:30
Authorbrian360

Log Message

Add STM32 Ethernet driver and LWIP demo (for Olimex STM32-P107 board).

Change Summary

Incremental Difference

--- branches/stm32_ethernet_wrapper/boards/OLIMEX_STM32_P107/board.h (revision 2870)
+++ branches/stm32_ethernet_wrapper/boards/OLIMEX_STM32_P107/board.h (revision 2871)
@@ -40,7 +40,9 @@
4040 /*
4141 * MCU type, supported types are defined in ./os/hal/platforms/hal_lld.h.
4242 */
43+#ifndef STM32F10X_CL
4344 #define STM32F10X_CL
45+#endif
4446
4547 /*
4648 * IO pins assignments.
--- branches/stm32_ethernet_wrapper/demos/ARMCM3-STM32F107-LWIP/lwip/arch/cc.h (nonexistent)
+++ branches/stm32_ethernet_wrapper/demos/ARMCM3-STM32F107-LWIP/lwip/arch/cc.h (revision 2871)
@@ -0,0 +1,91 @@
1+/*
2+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.
3+
4+ This file is part of ChibiOS/RT.
5+
6+ ChibiOS/RT is free software; you can redistribute it and/or modify
7+ it under the terms of the GNU General Public License as published by
8+ the Free Software Foundation; either version 3 of the License, or
9+ (at your option) any later version.
10+
11+ ChibiOS/RT is distributed in the hope that it will be useful,
12+ but WITHOUT ANY WARRANTY; without even the implied warranty of
13+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14+ GNU General Public License for more details.
15+
16+ You should have received a copy of the GNU General Public License
17+ along with this program. If not, see <http://www.gnu.org/licenses/>.
18+
19+ ---
20+
21+ A special exception to the GPL can be applied should you wish to distribute
22+ a combined work that includes ChibiOS/RT, without being obliged to provide
23+ the source code for any proprietary components. See the file exception.txt
24+ for full details of how and when the exception can be applied.
25+*/
26+/*
27+ * **** This file incorporates work covered by the following copyright and ****
28+ * **** permission notice: ****
29+ *
30+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
31+ * All rights reserved.
32+ *
33+ * Redistribution and use in source and binary forms, with or without modification,
34+ * are permitted provided that the following conditions are met:
35+ *
36+ * 1. Redistributions of source code must retain the above copyright notice,
37+ * this list of conditions and the following disclaimer.
38+ * 2. Redistributions in binary form must reproduce the above copyright notice,
39+ * this list of conditions and the following disclaimer in the documentation
40+ * and/or other materials provided with the distribution.
41+ * 3. The name of the author may not be used to endorse or promote products
42+ * derived from this software without specific prior written permission.
43+ *
44+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
45+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
46+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
47+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
48+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
49+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
50+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
51+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
52+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
53+ * OF SUCH DAMAGE.
54+ *
55+ * This file is part of the lwIP TCP/IP stack.
56+ *
57+ * Author: Adam Dunkels <adam@sics.se>
58+ *
59+ */
60+
61+#ifndef __CC_H__
62+#define __CC_H__
63+
64+#include <ch.h>
65+
66+#define LWIP_PROVIDE_ERRNO
67+
68+typedef uint8_t u8_t;
69+typedef int8_t s8_t;
70+typedef uint16_t u16_t;
71+typedef int16_t s16_t;
72+typedef uint32_t u32_t;
73+typedef int32_t s32_t;
74+typedef uint32_t mem_ptr_t;
75+
76+#define LWIP_PLATFORM_DIAG(x)
77+#define LWIP_PLATFORM_ASSERT(x) { \
78+ chSysHalt(); \
79+}
80+
81+#define BYTE_ORDER LITTLE_ENDIAN
82+
83+#define PACK_STRUCT_BEGIN
84+#ifdef PACK_STRUCT_STRUCT
85+#undef PACK_STRUCT_STRUCT
86+#endif
87+#define PACK_STRUCT_STRUCT __attribute__ ((__packed__))
88+#define PACK_STRUCT_END
89+#define PACK_STRUCT_FIELD(x) x
90+
91+#endif /* __CC_H__ */
--- branches/stm32_ethernet_wrapper/demos/ARMCM3-STM32F107-LWIP/lwip/arch/perf.h (nonexistent)
+++ branches/stm32_ethernet_wrapper/demos/ARMCM3-STM32F107-LWIP/lwip/arch/perf.h (revision 2871)
@@ -0,0 +1,67 @@
1+/*
2+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.
3+
4+ This file is part of ChibiOS/RT.
5+
6+ ChibiOS/RT is free software; you can redistribute it and/or modify
7+ it under the terms of the GNU General Public License as published by
8+ the Free Software Foundation; either version 3 of the License, or
9+ (at your option) any later version.
10+
11+ ChibiOS/RT is distributed in the hope that it will be useful,
12+ but WITHOUT ANY WARRANTY; without even the implied warranty of
13+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14+ GNU General Public License for more details.
15+
16+ You should have received a copy of the GNU General Public License
17+ along with this program. If not, see <http://www.gnu.org/licenses/>.
18+
19+ ---
20+
21+ A special exception to the GPL can be applied should you wish to distribute
22+ a combined work that includes ChibiOS/RT, without being obliged to provide
23+ the source code for any proprietary components. See the file exception.txt
24+ for full details of how and when the exception can be applied.
25+*/
26+/*
27+ * **** This file incorporates work covered by the following copyright and ****
28+ * **** permission notice: ****
29+ *
30+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
31+ * All rights reserved.
32+ *
33+ * Redistribution and use in source and binary forms, with or without modification,
34+ * are permitted provided that the following conditions are met:
35+ *
36+ * 1. Redistributions of source code must retain the above copyright notice,
37+ * this list of conditions and the following disclaimer.
38+ * 2. Redistributions in binary form must reproduce the above copyright notice,
39+ * this list of conditions and the following disclaimer in the documentation
40+ * and/or other materials provided with the distribution.
41+ * 3. The name of the author may not be used to endorse or promote products
42+ * derived from this software without specific prior written permission.
43+ *
44+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
45+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
46+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
47+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
48+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
49+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
50+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
51+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
52+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
53+ * OF SUCH DAMAGE.
54+ *
55+ * This file is part of the lwIP TCP/IP stack.
56+ *
57+ * Author: Adam Dunkels <adam@sics.se>
58+ *
59+ */
60+
61+#ifndef __PERF_H__
62+#define __PERF_H__
63+
64+#define PERF_START
65+#define PERF_STOP(x)
66+
67+#endif /* __PERF_H__ */
--- branches/stm32_ethernet_wrapper/demos/ARMCM3-STM32F107-LWIP/lwip/arch/sys_arch.c (nonexistent)
+++ branches/stm32_ethernet_wrapper/demos/ARMCM3-STM32F107-LWIP/lwip/arch/sys_arch.c (revision 2871)
@@ -0,0 +1,208 @@
1+/*
2+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.
3+
4+ This file is part of ChibiOS/RT.
5+
6+ ChibiOS/RT is free software; you can redistribute it and/or modify
7+ it under the terms of the GNU General Public License as published by
8+ the Free Software Foundation; either version 3 of the License, or
9+ (at your option) any later version.
10+
11+ ChibiOS/RT is distributed in the hope that it will be useful,
12+ but WITHOUT ANY WARRANTY; without even the implied warranty of
13+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14+ GNU General Public License for more details.
15+
16+ You should have received a copy of the GNU General Public License
17+ along with this program. If not, see <http://www.gnu.org/licenses/>.
18+
19+ ---
20+
21+ A special exception to the GPL can be applied should you wish to distribute
22+ a combined work that includes ChibiOS/RT, without being obliged to provide
23+ the source code for any proprietary components. See the file exception.txt
24+ for full details of how and when the exception can be applied.
25+*/
26+/*
27+ * **** This file incorporates work covered by the following copyright and ****
28+ * **** permission notice: ****
29+ *
30+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
31+ * All rights reserved.
32+ *
33+ * Redistribution and use in source and binary forms, with or without modification,
34+ * are permitted provided that the following conditions are met:
35+ *
36+ * 1. Redistributions of source code must retain the above copyright notice,
37+ * this list of conditions and the following disclaimer.
38+ * 2. Redistributions in binary form must reproduce the above copyright notice,
39+ * this list of conditions and the following disclaimer in the documentation
40+ * and/or other materials provided with the distribution.
41+ * 3. The name of the author may not be used to endorse or promote products
42+ * derived from this software without specific prior written permission.
43+ *
44+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
45+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
46+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
47+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
48+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
49+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
50+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
51+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
52+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
53+ * OF SUCH DAMAGE.
54+ *
55+ * This file is part of the lwIP TCP/IP stack.
56+ *
57+ * Author: Adam Dunkels <adam@sics.se>
58+ *
59+ */
60+
61+#include "ch.h"
62+
63+#include "lwip/opt.h"
64+#include "lwip/mem.h"
65+#include "lwip/sys.h"
66+#include "lwip/stats.h"
67+
68+#include "arch/cc.h"
69+#include "arch/sys_arch.h"
70+
71+void sys_init(void) {
72+
73+}
74+
75+err_t sys_sem_new(sys_sem_t *sem, u8_t count) {
76+
77+ *sem = chHeapAlloc(NULL, sizeof(Semaphore));
78+ if (*sem == 0) {
79+ SYS_STATS_INC(sem.err);
80+ return ERR_MEM;
81+ }
82+ else {
83+ chSemInit(*sem, (cnt_t)count);
84+ SYS_STATS_INC(sem.used);
85+ }
86+ return ERR_OK;
87+}
88+
89+void sys_sem_free(sys_sem_t *sem) {
90+
91+ chHeapFree(*sem);
92+ *sem = SYS_SEM_NULL;
93+ SYS_STATS_DEC(sem.used);
94+}
95+
96+void sys_sem_signal(sys_sem_t *sem) {
97+
98+ chSemSignal(*sem);
99+}
100+
101+u32_t sys_arch_sem_wait(sys_sem_t *sem, u32_t timeout) {
102+ systime_t time;
103+
104+ chSysLock();
105+ time = chTimeNow();
106+ if (chSemWaitTimeoutS(*sem, (systime_t)timeout) != RDY_OK)
107+ time = SYS_ARCH_TIMEOUT;
108+ else
109+ time = chTimeNow() - time;
110+ chSysUnlock();
111+ return time;
112+}
113+
114+int sys_sem_valid(sys_sem_t *sem) {
115+ return *sem != SYS_SEM_NULL;
116+}
117+
118+void sys_sem_set_invalid(sys_sem_t *sem) {
119+ *sem = SYS_SEM_NULL;
120+}
121+
122+err_t sys_mbox_new(sys_mbox_t *mbox, int size) {
123+
124+ *mbox = chHeapAlloc(NULL, sizeof(Mailbox) + sizeof(msg_t) * size);
125+ if (*mbox == 0) {
126+ SYS_STATS_INC(mbox.err);
127+ return ERR_MEM;
128+ }
129+ else {
130+ chMBInit(*mbox, (void *)(((uint8_t *)*mbox) + sizeof(Mailbox)), size);
131+ SYS_STATS_INC(mbox.used);
132+ }
133+ return ERR_OK;
134+}
135+
136+void sys_mbox_free(sys_mbox_t *mbox) {
137+
138+ chHeapFree(*mbox);
139+ *mbox = SYS_MBOX_NULL;
140+ SYS_STATS_DEC(mbox.used);
141+}
142+
143+void sys_mbox_post(sys_mbox_t *mbox, void *msg) {
144+
145+ chMBPost(*mbox, (msg_t)msg, TIME_INFINITE);
146+}
147+
148+err_t sys_mbox_trypost(sys_mbox_t *mbox, void *msg) {
149+
150+ if (chMBPost(*mbox, (msg_t)msg, TIME_IMMEDIATE) == RDY_TIMEOUT)
151+ return ERR_MEM;
152+ return ERR_OK;
153+}
154+
155+u32_t sys_arch_mbox_fetch(sys_mbox_t *mbox, void **msg, u32_t timeout) {
156+ systime_t time;
157+
158+ chSysLock();
159+ time = chTimeNow();
160+ if (chMBFetchS(*mbox, (msg_t *)msg, (systime_t)timeout) != RDY_OK)
161+ time = SYS_ARCH_TIMEOUT;
162+ else
163+ time = chTimeNow() - time;
164+ chSysUnlock();
165+ return time;
166+}
167+
168+u32_t sys_arch_mbox_tryfetch(sys_mbox_t *mbox, void **msg) {
169+
170+ if (chMBFetch(*mbox, (msg_t *)msg, TIME_IMMEDIATE) == RDY_TIMEOUT)
171+ return SYS_MBOX_EMPTY;
172+ return 0;
173+}
174+
175+int sys_mbox_valid(sys_mbox_t *mbox) {
176+ return *mbox != SYS_MBOX_NULL;
177+}
178+
179+void sys_mbox_set_invalid(sys_mbox_t *mbox) {
180+ *mbox = SYS_MBOX_NULL;
181+}
182+
183+struct sys_timeouts *sys_arch_timeouts(void) {
184+
185+ return (struct sys_timeouts *)currp->p_lwipspace;
186+}
187+
188+sys_thread_t sys_thread_new(const char *name, void (* thread)(void *arg),
189+ void *arg, int stacksize, int prio) {
190+ (void)name;
191+ size_t wsz = THD_WA_SIZE(stacksize);
192+ void *wsp = chCoreAlloc(wsz);
193+ if (wsp == NULL)
194+ return NULL;
195+ return (sys_thread_t)chThdCreateStatic(wsp, wsz, prio, (tfunc_t)thread, arg);
196+}
197+
198+sys_prot_t sys_arch_protect(void) {
199+
200+ chSysLock();
201+ return 0;
202+}
203+
204+void sys_arch_unprotect(sys_prot_t pval) {
205+
206+ (void)pval;
207+ chSysUnlock();
208+}
--- branches/stm32_ethernet_wrapper/demos/ARMCM3-STM32F107-LWIP/lwip/arch/sys_arch.h (nonexistent)
+++ branches/stm32_ethernet_wrapper/demos/ARMCM3-STM32F107-LWIP/lwip/arch/sys_arch.h (revision 2871)
@@ -0,0 +1,105 @@
1+/*
2+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.
3+
4+ This file is part of ChibiOS/RT.
5+
6+ ChibiOS/RT is free software; you can redistribute it and/or modify
7+ it under the terms of the GNU General Public License as published by
8+ the Free Software Foundation; either version 3 of the License, or
9+ (at your option) any later version.
10+
11+ ChibiOS/RT is distributed in the hope that it will be useful,
12+ but WITHOUT ANY WARRANTY; without even the implied warranty of
13+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14+ GNU General Public License for more details.
15+
16+ You should have received a copy of the GNU General Public License
17+ along with this program. If not, see <http://www.gnu.org/licenses/>.
18+
19+ ---
20+
21+ A special exception to the GPL can be applied should you wish to distribute
22+ a combined work that includes ChibiOS/RT, without being obliged to provide
23+ the source code for any proprietary components. See the file exception.txt
24+ for full details of how and when the exception can be applied.
25+*/
26+/*
27+ * **** This file incorporates work covered by the following copyright and ****
28+ * **** permission notice: ****
29+ *
30+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
31+ * All rights reserved.
32+ *
33+ * Redistribution and use in source and binary forms, with or without modification,
34+ * are permitted provided that the following conditions are met:
35+ *
36+ * 1. Redistributions of source code must retain the above copyright notice,
37+ * this list of conditions and the following disclaimer.
38+ * 2. Redistributions in binary form must reproduce the above copyright notice,
39+ * this list of conditions and the following disclaimer in the documentation
40+ * and/or other materials provided with the distribution.
41+ * 3. The name of the author may not be used to endorse or promote products
42+ * derived from this software without specific prior written permission.
43+ *
44+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
45+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
46+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
47+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
48+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
49+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
50+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
51+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
52+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
53+ * OF SUCH DAMAGE.
54+ *
55+ * This file is part of the lwIP TCP/IP stack.
56+ *
57+ * Author: Adam Dunkels <adam@sics.se>
58+ *
59+ */
60+
61+#include <ch.h>
62+
63+#ifndef __SYS_ARCH_H__
64+#define __SYS_ARCH_H__
65+
66+#define LWIP_COMPAT_MUTEX 1
67+
68+typedef Semaphore * sys_sem_t;
69+typedef Mailbox * sys_mbox_t;
70+typedef Thread * sys_thread_t;
71+typedef int sys_prot_t;
72+
73+#define SYS_MBOX_NULL (Mailbox *)0
74+#define SYS_THREAD_NULL (Thread *)0
75+#define SYS_SEM_NULL (Semaphore *)0
76+
77+void sys_init(void);
78+err_t sys_sem_new(sys_sem_t *sem, u8_t count);
79+void sys_sem_free(sys_sem_t *sem);
80+void sys_sem_signal(sys_sem_t *sem);
81+u32_t sys_arch_sem_wait(sys_sem_t *sem, u32_t timeout);
82+int sys_sem_valid(sys_sem_t *sem);
83+void sys_sem_set_invalid(sys_sem_t *sem);
84+
85+err_t sys_mbox_new(sys_mbox_t *mbox, int size);
86+void sys_mbox_free(sys_mbox_t *mbox);
87+void sys_mbox_post(sys_mbox_t *mbox, void *msg);
88+err_t sys_mbox_trypost(sys_mbox_t *mbox, void *msg);
89+u32_t sys_arch_mbox_fetch(sys_mbox_t *mbox, void **msg, u32_t timeout);
90+u32_t sys_arch_mbox_tryfetch(sys_mbox_t *mbox, void **msg);
91+int sys_mbox_valid(sys_mbox_t *mbox);
92+void sys_mbox_set_invalid(sys_mbox_t *mbox);
93+
94+struct sys_timeouts *sys_arch_timeouts(void);
95+
96+sys_thread_t sys_thread_new(const char *name,
97+ void (* thread)(void *arg),
98+ void *arg,
99+ int stacksize,
100+ int prio);
101+
102+sys_prot_t sys_arch_protect(void);
103+void sys_arch_unprotect(sys_prot_t pval);
104+
105+#endif /* __SYS_ARCH_H__ */
--- branches/stm32_ethernet_wrapper/demos/ARMCM3-STM32F107-LWIP/lwip/lwipthread.c (nonexistent)
+++ branches/stm32_ethernet_wrapper/demos/ARMCM3-STM32F107-LWIP/lwip/lwipthread.c (revision 2871)
@@ -0,0 +1,309 @@
1+/*
2+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.
3+
4+ This file is part of ChibiOS/RT.
5+
6+ ChibiOS/RT is free software; you can redistribute it and/or modify
7+ it under the terms of the GNU General Public License as published by
8+ the Free Software Foundation; either version 3 of the License, or
9+ (at your option) any later version.
10+
11+ ChibiOS/RT is distributed in the hope that it will be useful,
12+ but WITHOUT ANY WARRANTY; without even the implied warranty of
13+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14+ GNU General Public License for more details.
15+
16+ You should have received a copy of the GNU General Public License
17+ along with this program. If not, see <http://www.gnu.org/licenses/>.
18+
19+ ---
20+
21+ A special exception to the GPL can be applied should you wish to distribute
22+ a combined work that includes ChibiOS/RT, without being obliged to provide
23+ the source code for any proprietary components. See the file exception.txt
24+ for full details of how and when the exception can be applied.
25+*/
26+/*
27+ * **** This file incorporates work covered by the following copyright and ****
28+ * **** permission notice: ****
29+ *
30+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
31+ * All rights reserved.
32+ *
33+ * Redistribution and use in source and binary forms, with or without modification,
34+ * are permitted provided that the following conditions are met:
35+ *
36+ * 1. Redistributions of source code must retain the above copyright notice,
37+ * this list of conditions and the following disclaimer.
38+ * 2. Redistributions in binary form must reproduce the above copyright notice,
39+ * this list of conditions and the following disclaimer in the documentation
40+ * and/or other materials provided with the distribution.
41+ * 3. The name of the author may not be used to endorse or promote products
42+ * derived from this software without specific prior written permission.
43+ *
44+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
45+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
46+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
47+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
48+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
49+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
50+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
51+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
52+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
53+ * OF SUCH DAMAGE.
54+ *
55+ * This file is part of the lwIP TCP/IP stack.
56+ *
57+ * Author: Adam Dunkels <adam@sics.se>
58+ *
59+ */
60+
61+/**
62+ * @file lwipthread.c
63+ * @brief LWIP wrapper thread code.
64+ * @addtogroup LWIP_THREAD
65+ * @{
66+ */
67+
68+#include "ch.h"
69+#include "hal.h"
70+#include "evtimer.h"
71+
72+#include "lwip/opt.h"
73+
74+#include "lwip/def.h"
75+#include "lwip/mem.h"
76+#include "lwip/pbuf.h"
77+#include "lwip/sys.h"
78+#include <lwip/stats.h>
79+#include <lwip/snmp.h>
80+#include <lwip/tcpip.h>
81+#include "netif/etharp.h"
82+#include "netif/ppp_oe.h"
83+
84+#include "lwipthread.h"
85+
86+#define PERIODIC_TIMER_ID 1
87+#define FRAME_RECEIVED_ID 2
88+
89+/**
90+ * Stack area for the LWIP-MAC thread.
91+ */
92+WORKING_AREA(wa_lwip_thread, LWIP_THREAD_STACK_SIZE);
93+
94+/*
95+ * Initialization.
96+ */
97+static void low_level_init(struct netif *netif) {
98+ /* set MAC hardware address length */
99+ netif->hwaddr_len = ETHARP_HWADDR_LEN;
100+
101+ /* maximum transfer unit */
102+ netif->mtu = 1500;
103+
104+ /* device capabilities */
105+ /* don't set NETIF_FLAG_ETHARP if this device is not an ethernet one */
106+ netif->flags = NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP | NETIF_FLAG_LINK_UP;
107+
108+ /* Do whatever else is needed to initialize interface. */
109+}
110+
111+/*
112+ * Transmits a frame.
113+ */
114+static err_t low_level_output(struct netif *netif, struct pbuf *p) {
115+ struct pbuf *q;
116+ MACTransmitDescriptor td;
117+
118+ (void)netif;
119+ if (macWaitTransmitDescriptor(&ETH1, &td, MS2ST(LWIP_SEND_TIMEOUT)) != RDY_OK)
120+ return ERR_TIMEOUT;
121+
122+#if ETH_PAD_SIZE
123+ pbuf_header(p, -ETH_PAD_SIZE); /* drop the padding word */
124+#endif
125+
126+ /* Iterates through the pbuf chain. */
127+ for(q = p; q != NULL; q = q->next) {
128+ macWriteTransmitDescriptor(&td, (uint8_t *)q->payload, (size_t)q->len);
129+ }
130+ macReleaseTransmitDescriptor(&td);
131+
132+#if ETH_PAD_SIZE
133+ pbuf_header(p, ETH_PAD_SIZE); /* reclaim the padding word */
134+#endif
135+
136+ LINK_STATS_INC(link.xmit);
137+
138+ return ERR_OK;
139+}
140+
141+/*
142+ * Receives a frame.
143+ */
144+static struct pbuf *low_level_input(struct netif *netif) {
145+ MACReceiveDescriptor rd;
146+ struct pbuf *p, *q;
147+ u16_t len;
148+
149+ (void)netif;
150+ if (macWaitReceiveDescriptor(&ETH1, &rd, TIME_IMMEDIATE) == RDY_OK) {
151+ len = (u16_t)rd.size;
152+
153+#if ETH_PAD_SIZE
154+ len += ETH_PAD_SIZE; /* allow room for Ethernet padding */
155+#endif
156+
157+ /* We allocate a pbuf chain of pbufs from the pool. */
158+ p = pbuf_alloc(PBUF_RAW, len, PBUF_POOL);
159+
160+ if (p != NULL) {
161+
162+#if ETH_PAD_SIZE
163+ pbuf_header(p, -ETH_PAD_SIZE); /* drop the padding word */
164+#endif
165+
166+ /* Iterates through the pbuf chain. */
167+ for(q = p; q != NULL; q = q->next) {
168+ macReadReceiveDescriptor(&rd, (uint8_t *)q->payload, (size_t)q->len);
169+ }
170+ macReleaseReceiveDescriptor(&rd);
171+
172+#if ETH_PAD_SIZE
173+ pbuf_header(p, ETH_PAD_SIZE); /* reclaim the padding word */
174+#endif
175+
176+ LINK_STATS_INC(link.recv);
177+ }
178+ else {
179+ macReleaseReceiveDescriptor(&rd);
180+ LINK_STATS_INC(link.memerr);
181+ LINK_STATS_INC(link.drop);
182+ }
183+ return p;
184+ }
185+ return NULL;
186+}
187+
188+/*
189+ * Initialization.
190+ */
191+static err_t ethernetif_init(struct netif *netif) {
192+#if LWIP_NETIF_HOSTNAME
193+ /* Initialize interface hostname */
194+ netif->hostname = "lwip";
195+#endif /* LWIP_NETIF_HOSTNAME */
196+
197+ /*
198+ * Initialize the snmp variables and counters inside the struct netif.
199+ * The last argument should be replaced with your link speed, in units
200+ * of bits per second.
201+ */
202+ NETIF_INIT_SNMP(netif, snmp_ifType_ethernet_csmacd, LWIP_LINK_SPEED);
203+
204+ netif->state = NULL;
205+ netif->name[0] = LWIP_IFNAME0;
206+ netif->name[1] = LWIP_IFNAME1;
207+ /* We directly use etharp_output() here to save a function call.
208+ * You can instead declare your own function an call etharp_output()
209+ * from it if you have to do some checks before sending (e.g. if link
210+ * is available...) */
211+ netif->output = etharp_output;
212+ netif->linkoutput = low_level_output;
213+
214+ /* initialize the hardware */
215+ low_level_init(netif);
216+
217+ return ERR_OK;
218+}
219+
220+/**
221+ * @brief LWIP handling thread.
222+ *
223+ * @param[in] p pointer to a @p lwipthread_opts structure or @p NULL
224+ * @return The function does not return.
225+ */
226+msg_t lwip_thread(void *p) {
227+ EvTimer evt;
228+ EventListener el0, el1;
229+ struct ip_addr ip, gateway, netmask;
230+ static struct netif thisif;
231+
232+ /* Initializes the thing.*/
233+ sys_init();
234+ mem_init();
235+ memp_init();
236+ pbuf_init();
237+ netif_init();
238+ ip_init();
239+ tcpip_init(NULL, NULL);
240+
241+ /* TCP/IP parameters, runtime or compile time.*/
242+ if (p) {
243+ struct lwipthread_opts *opts = p;
244+ unsigned i;
245+
246+ for (i = 0; i < 6; i++)
247+ thisif.hwaddr[i] = opts->macaddress[i];
248+ ip.addr = opts->address;
249+ gateway.addr = opts->gateway;
250+ netmask.addr = opts->netmask;
251+ }
252+ else {
253+ thisif.hwaddr[0] = LWIP_ETHADDR_0;
254+ thisif.hwaddr[1] = LWIP_ETHADDR_1;
255+ thisif.hwaddr[2] = LWIP_ETHADDR_2;
256+ thisif.hwaddr[3] = LWIP_ETHADDR_3;
257+ thisif.hwaddr[4] = LWIP_ETHADDR_4;
258+ thisif.hwaddr[5] = LWIP_ETHADDR_5;
259+ LWIP_IPADDR(&ip);
260+ LWIP_GATEWAY(&gateway);
261+ LWIP_NETMASK(&netmask);
262+ }
263+ macSetAddress(&ETH1, thisif.hwaddr);
264+ netif_add(&thisif, &ip, &netmask, &gateway, NULL, ethernetif_init, tcpip_input);
265+
266+ netif_set_default(&thisif);
267+ netif_set_up(&thisif);
268+
269+ /* Setup event sources.*/
270+ evtInit(&evt, S2ST(5));
271+ evtStart(&evt);
272+ chEvtRegisterMask(&evt.et_es, &el0, PERIODIC_TIMER_ID);
273+ chEvtRegisterMask(macGetReceiveEventSource(&ETH1), &el1, FRAME_RECEIVED_ID);
274+ chEvtAddFlags(PERIODIC_TIMER_ID | FRAME_RECEIVED_ID);
275+
276+ /* Goes to the final priority after initialization.*/
277+ chThdSetPriority(LWIP_THREAD_PRIORITY);
278+
279+ while (TRUE) {
280+ eventmask_t mask = chEvtWaitAny(ALL_EVENTS);
281+ if (mask & PERIODIC_TIMER_ID)
282+ (void)macPollLinkStatus(&ETH1);
283+ if (mask & FRAME_RECEIVED_ID) {
284+ struct pbuf *p;
285+ while ((p = low_level_input(&thisif)) != NULL) {
286+ struct eth_hdr *ethhdr = p->payload;
287+ switch (htons(ethhdr->type)) {
288+ /* IP or ARP packet? */
289+ case ETHTYPE_IP:
290+ case ETHTYPE_ARP:
291+#if PPPOE_SUPPORT
292+ /* PPPoE packet? */
293+ case ETHTYPE_PPPOEDISC:
294+ case ETHTYPE_PPPOE:
295+#endif /* PPPOE_SUPPORT */
296+ /* full packet send to tcpip_thread to process */
297+ if (thisif.input(p, &thisif) == ERR_OK)
298+ break;
299+ LWIP_DEBUGF(NETIF_DEBUG, ("ethernetif_input: IP input error\n"));
300+ default:
301+ pbuf_free(p);
302+ }
303+ }
304+ }
305+ }
306+ return 0;
307+}
308+
309+/** @} */
--- branches/stm32_ethernet_wrapper/demos/ARMCM3-STM32F107-LWIP/lwip/lwipthread.h (nonexistent)
+++ branches/stm32_ethernet_wrapper/demos/ARMCM3-STM32F107-LWIP/lwip/lwipthread.h (revision 2871)
@@ -0,0 +1,134 @@
1+/*
2+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.
3+
4+ This file is part of ChibiOS/RT.
5+
6+ ChibiOS/RT is free software; you can redistribute it and/or modify
7+ it under the terms of the GNU General Public License as published by
8+ the Free Software Foundation; either version 3 of the License, or
9+ (at your option) any later version.
10+
11+ ChibiOS/RT is distributed in the hope that it will be useful,
12+ but WITHOUT ANY WARRANTY; without even the implied warranty of
13+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14+ GNU General Public License for more details.
15+
16+ You should have received a copy of the GNU General Public License
17+ along with this program. If not, see <http://www.gnu.org/licenses/>.
18+
19+ ---
20+
21+ A special exception to the GPL can be applied should you wish to distribute
22+ a combined work that includes ChibiOS/RT, without being obliged to provide
23+ the source code for any proprietary components. See the file exception.txt
24+ for full details of how and when the exception can be applied.
25+*/
26+
27+/**
28+ * @file lwipthread.h
29+ * @brief LWIP wrapper thread macros and structures.
30+ * @addtogroup LWIP_THREAD
31+ * @{
32+ */
33+
34+#ifndef _LWIPTHREAD_H_
35+#define _LWIPTHREAD_H_
36+
37+/** @brief MAC thread priority.*/
38+#ifndef LWIP_THREAD_PRIORITY
39+#define LWIP_THREAD_PRIORITY LOWPRIO
40+#endif
41+
42+/** @brief IP Address. */
43+#if !defined(LWIP_IPADDR) || defined(__DOXYGEN__)
44+#define LWIP_IPADDR(p) IP4_ADDR(p, 192, 168, 0, 225)
45+#endif
46+
47+/** @brief IP Gateway. */
48+#if !defined(LWIP_GATEWAY) || defined(__DOXYGEN__)
49+#define LWIP_GATEWAY(p) IP4_ADDR(p, 192, 168, 0, 1)
50+#endif
51+
52+/** @brief IP netmask. */
53+#if !defined(LWIP_NETMASK) || defined(__DOXYGEN__)
54+#define LWIP_NETMASK(p) IP4_ADDR(p, 255, 255, 255, 0)
55+#endif
56+
57+/** @brief MAC thread stack size. */
58+#if !defined(LWIP_THREAD_STACK_SIZE) || defined(__DOXYGEN__)
59+#define LWIP_THREAD_STACK_SIZE 4096
60+#endif
61+
62+/** @brief Transmission timeout. */
63+#if !defined(LWIP_SEND_TIMEOUT) || defined(__DOXYGEN__)
64+#define LWIP_SEND_TIMEOUT 50
65+#endif
66+
67+/** @brief Link speed. */
68+#if !defined(LWIP_LINK_SPEED) || defined(__DOXYGEN__)
69+#define LWIP_LINK_SPEED 100000000
70+#endif
71+
72+/** @brief MAC Address byte 0. */
73+#if !defined(LWIP_ETHADDR_0) || defined(__DOXYGEN__)
74+#define LWIP_ETHADDR_0 0xC2
75+#endif
76+
77+/** @brief MAC Address byte 1. */
78+#if !defined(LWIP_ETHADDR_1) || defined(__DOXYGEN__)
79+#define LWIP_ETHADDR_1 0xAF
80+#endif
81+
82+/** @brief MAC Address byte 2. */
83+#if !defined(LWIP_ETHADDR_2) || defined(__DOXYGEN__)
84+#define LWIP_ETHADDR_2 0x51
85+#endif
86+
87+/** @brief MAC Address byte 3. */
88+#if !defined(LWIP_ETHADDR_3) || defined(__DOXYGEN__)
89+#define LWIP_ETHADDR_3 0x03
90+#endif
91+
92+/** @brief MAC Address byte 4. */
93+#if !defined(LWIP_ETHADDR_4) || defined(__DOXYGEN__)
94+#define LWIP_ETHADDR_4 0xCF
95+#endif
96+
97+/** @brief MAC Address byte 5. */
98+#if !defined(LWIP_ETHADDR_5) || defined(__DOXYGEN__)
99+#define LWIP_ETHADDR_5 0x46
100+#endif
101+
102+/** @brief Interface name byte 0. */
103+#if !defined(LWIP_IFNAME0) || defined(__DOXYGEN__)
104+#define LWIP_IFNAME0 'm'
105+#endif
106+
107+/** @brief Interface name byte 1. */
108+#if !defined(LWIP_IFNAME1) || defined(__DOXYGEN__)
109+#define LWIP_IFNAME1 's'
110+#endif
111+
112+/**
113+ * @brief Runtime TCP/IP settings.
114+ */
115+struct lwipthread_opts {
116+ uint8_t *macaddress;
117+ uint32_t address;
118+ uint32_t netmask;
119+ uint32_t gateway;
120+};
121+
122+extern WORKING_AREA(wa_lwip_thread, LWIP_THREAD_STACK_SIZE);
123+
124+#ifdef __cplusplus
125+extern "C" {
126+#endif
127+ msg_t lwip_thread(void *p);
128+#ifdef __cplusplus
129+}
130+#endif
131+
132+#endif /* _LWIPTHREAD_H_ */
133+
134+/** @} */
--- branches/stm32_ethernet_wrapper/demos/ARMCM3-STM32F107-LWIP/web/web.c (nonexistent)
+++ branches/stm32_ethernet_wrapper/demos/ARMCM3-STM32F107-LWIP/web/web.c (revision 2871)
@@ -0,0 +1,139 @@
1+/*
2+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.
3+
4+ This file is part of ChibiOS/RT.
5+
6+ ChibiOS/RT is free software; you can redistribute it and/or modify
7+ it under the terms of the GNU General Public License as published by
8+ the Free Software Foundation; either version 3 of the License, or
9+ (at your option) any later version.
10+
11+ ChibiOS/RT is distributed in the hope that it will be useful,
12+ but WITHOUT ANY WARRANTY; without even the implied warranty of
13+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14+ GNU General Public License for more details.
15+
16+ You should have received a copy of the GNU General Public License
17+ along with this program. If not, see <http://www.gnu.org/licenses/>.
18+
19+ ---
20+
21+ A special exception to the GPL can be applied should you wish to distribute
22+ a combined work that includes ChibiOS/RT, without being obliged to provide
23+ the source code for any proprietary components. See the file exception.txt
24+ for full details of how and when the exception can be applied.
25+*/
26+
27+/*
28+ * This file is a modified version of the lwIP web server demo. The original
29+ * author is unknown because the file didn't contain any license information.
30+ */
31+
32+/**
33+ * @file web.c
34+ * @brief HTTP server wrapper thread code.
35+ * @addtogroup WEB_THREAD
36+ * @{
37+ */
38+
39+#include "ch.h"
40+
41+#include "lwip/opt.h"
42+#include "lwip/arch.h"
43+#include "lwip/api.h"
44+
45+#include "web.h"
46+
47+#if LWIP_NETCONN
48+
49+#ifndef HTTPD_DEBUG
50+#define HTTPD_DEBUG LWIP_DBG_OFF
51+#endif
52+
53+static const char http_html_hdr[] = "HTTP/1.1 200 OK\r\nContent-type: text/html\r\n\r\n";
54+static const char http_index_html[] = "<html><head><title>Congrats!</title></head><body><h1>Welcome to our lwIP HTTP server!</h1><p>This is a small test page.</body></html>";
55+
56+static void http_server_serve(struct netconn *conn) {
57+ struct netbuf *inbuf;
58+ char *buf;
59+ u16_t buflen;
60+ err_t err;
61+
62+ /* Read the data from the port, blocking if nothing yet there.
63+ We assume the request (the part we care about) is in one netbuf */
64+ err = netconn_recv(conn, &inbuf);
65+
66+ if (err == ERR_OK) {
67+ netbuf_data(inbuf, (void**)&buf, &buflen);
68+
69+ /* Is this an HTTP GET command? (only check the first 5 chars, since
70+ there are other formats for GET, and we're keeping it very simple )*/
71+ if (buflen>=5 &&
72+ buf[0]=='G' &&
73+ buf[1]=='E' &&
74+ buf[2]=='T' &&
75+ buf[3]==' ' &&
76+ buf[4]=='/' ) {
77+
78+ /* Send the HTML header
79+ * subtract 1 from the size, since we dont send the \0 in the string
80+ * NETCONN_NOCOPY: our data is const static, so no need to copy it
81+ */
82+ netconn_write(conn, http_html_hdr, sizeof(http_html_hdr)-1, NETCONN_NOCOPY);
83+
84+ /* Send our HTML page */
85+ netconn_write(conn, http_index_html, sizeof(http_index_html)-1, NETCONN_NOCOPY);
86+ }
87+ }
88+ /* Close the connection (server closes in HTTP) */
89+ netconn_close(conn);
90+
91+ /* Delete the buffer (netconn_recv gives us ownership,
92+ so we have to make sure to deallocate the buffer) */
93+ netbuf_delete(inbuf);
94+}
95+
96+/**
97+ * Stack area for the http thread.
98+ */
99+WORKING_AREA(wa_http_server, WEB_THREAD_STACK_SIZE);
100+
101+/**
102+ * HTTP server thread.
103+ */
104+msg_t http_server(void *p) {
105+ struct netconn *conn, *newconn;
106+ err_t err;
107+
108+ (void)p;
109+
110+ /* Create a new TCP connection handle */
111+ conn = netconn_new(NETCONN_TCP);
112+ LWIP_ERROR("http_server: invalid conn", (conn != NULL), return;);
113+
114+ /* Bind to port 80 (HTTP) with default IP address */
115+ netconn_bind(conn, NULL, WEB_THREAD_PORT);
116+
117+ /* Put the connection into LISTEN state */
118+ netconn_listen(conn);
119+
120+ /* Goes to the final priority after initialization.*/
121+ chThdSetPriority(WEB_THREAD_PRIORITY);
122+
123+ do {
124+ err = netconn_accept(conn, &newconn);
125+ if (err == ERR_OK) {
126+ http_server_serve(newconn);
127+ netconn_delete(newconn);
128+ }
129+ } while(err == ERR_OK);
130+ LWIP_DEBUGF(HTTPD_DEBUG,
131+ ("http_server_netconn_thread: netconn_accept received error %d, shutting down",
132+ err));
133+ netconn_close(conn);
134+ netconn_delete(conn);
135+}
136+
137+#endif /* LWIP_NETCONN */
138+
139+/** @} */
--- branches/stm32_ethernet_wrapper/demos/ARMCM3-STM32F107-LWIP/web/web.h (nonexistent)
+++ branches/stm32_ethernet_wrapper/demos/ARMCM3-STM32F107-LWIP/web/web.h (revision 2871)
@@ -0,0 +1,61 @@
1+/*
2+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.
3+
4+ This file is part of ChibiOS/RT.
5+
6+ ChibiOS/RT is free software; you can redistribute it and/or modify
7+ it under the terms of the GNU General Public License as published by
8+ the Free Software Foundation; either version 3 of the License, or
9+ (at your option) any later version.
10+
11+ ChibiOS/RT is distributed in the hope that it will be useful,
12+ but WITHOUT ANY WARRANTY; without even the implied warranty of
13+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14+ GNU General Public License for more details.
15+
16+ You should have received a copy of the GNU General Public License
17+ along with this program. If not, see <http://www.gnu.org/licenses/>.
18+
19+ ---
20+
21+ A special exception to the GPL can be applied should you wish to distribute
22+ a combined work that includes ChibiOS/RT, without being obliged to provide
23+ the source code for any proprietary components. See the file exception.txt
24+ for full details of how and when the exception can be applied.
25+*/
26+
27+/**
28+ * @file web.h
29+ * @brief HTTP server wrapper thread macros and structures.
30+ * @addtogroup WEB_THREAD
31+ * @{
32+ */
33+
34+#ifndef _WEB_H_
35+#define _WEB_H_
36+
37+#ifndef WEB_THREAD_STACK_SIZE
38+#define WEB_THREAD_STACK_SIZE 1024
39+#endif
40+
41+#ifndef WEB_THREAD_PORT
42+#define WEB_THREAD_PORT 80
43+#endif
44+
45+#ifndef WEB_THREAD_PRIORITY
46+#define WEB_THREAD_PRIORITY (LOWPRIO + 2)
47+#endif
48+
49+extern WORKING_AREA(wa_http_server, WEB_THREAD_STACK_SIZE);
50+
51+#ifdef __cplusplus
52+extern "C" {
53+#endif
54+ msg_t http_server(void *p);
55+#ifdef __cplusplus
56+}
57+#endif
58+
59+#endif /* _WEB_H_ */
60+
61+/** @} */
--- branches/stm32_ethernet_wrapper/demos/ARMCM3-STM32F107-LWIP/Makefile (nonexistent)
+++ branches/stm32_ethernet_wrapper/demos/ARMCM3-STM32F107-LWIP/Makefile (revision 2871)
@@ -0,0 +1,213 @@
1+##############################################################################
2+# Build global options
3+# NOTE: Can be overridden externally.
4+#
5+
6+# Compiler options here.
7+ifeq ($(USE_OPT),)
8+ USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16
9+endif
10+
11+# C++ specific options here (added to USE_OPT).
12+ifeq ($(USE_CPPOPT),)
13+ USE_CPPOPT = -fno-rtti
14+endif
15+
16+# Enable this if you want the linker to remove unused code and data
17+ifeq ($(USE_LINK_GC),)
18+ USE_LINK_GC = yes
19+endif
20+
21+# If enabled, this option allows to compile the application in THUMB mode.
22+ifeq ($(USE_THUMB),)
23+ USE_THUMB = yes
24+endif
25+
26+# Enable register caching optimization (read documentation).
27+ifeq ($(USE_CURRP_CACHING),)
28+ USE_CURRP_CACHING = no
29+endif
30+
31+#
32+# Build global options
33+##############################################################################
34+
35+##############################################################################
36+# Architecture or project specific options
37+#
38+
39+# Enable this if you really want to use the STM FWLib.
40+ifeq ($(USE_FWLIB),)
41+ USE_FWLIB = yes
42+endif
43+
44+#
45+# Architecture or project specific options
46+##############################################################################
47+
48+##############################################################################
49+# Project, sources and paths
50+#
51+
52+# Define project name here
53+PROJECT = ch
54+
55+# Define linker script file here
56+LDSCRIPT= ch.ld
57+
58+# Imported source files
59+CHIBIOS = ../..
60+include $(CHIBIOS)/boards/OLIMEX_STM32_P107/board.mk
61+include $(CHIBIOS)/os/hal/platforms/STM32/platform.mk
62+include $(CHIBIOS)/os/hal/hal.mk
63+include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32/port.mk
64+include $(CHIBIOS)/os/kernel/kernel.mk
65+include $(CHIBIOS)/test/test.mk
66+include ./lwip/lwip.mk
67+
68+# C sources that can be compiled in ARM or THUMB mode depending on the global
69+# setting.
70+CSRC = $(PORTSRC) \
71+ $(KERNSRC) \
72+ $(TESTSRC) \
73+ $(HALSRC) \
74+ $(PLATFORMSRC) \
75+ $(BOARDSRC) \
76+ $(CHIBIOS)/os/various/evtimer.c \
77+ $(CHIBIOS)/os/various/syscalls.c \
78+ $(LWNETIFSRC) \
79+ $(LWCORESRC) \
80+ $(LWIPV4SRC) \
81+ $(LWAPISRC) \
82+ ./lwip/arch/sys_arch.c \
83+ ./lwip/lwipthread.c \
84+ ./web/web.c \
85+ main.c
86+
87+# C++ sources that can be compiled in ARM or THUMB mode depending on the global
88+# setting.
89+CPPSRC =
90+
91+# C sources to be compiled in ARM mode regardless of the global setting.
92+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
93+# option that results in lower performance and larger code size.
94+ACSRC =
95+
96+# C++ sources to be compiled in ARM mode regardless of the global setting.
97+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
98+# option that results in lower performance and larger code size.
99+ACPPSRC =
100+
101+# C sources to be compiled in THUMB mode regardless of the global setting.
102+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
103+# option that results in lower performance and larger code size.
104+TCSRC =
105+
106+# C sources to be compiled in THUMB mode regardless of the global setting.
107+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
108+# option that results in lower performance and larger code size.
109+TCPPSRC =
110+
111+# List ASM source files here
112+ASMSRC = $(PORTASM)
113+
114+INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \
115+ $(HALINC) $(PLATFORMINC) $(BOARDINC) \
116+ $(CHIBIOS)/os/various \
117+ $(LWINC) ./lwip
118+
119+#
120+# Project, sources and paths
121+##############################################################################
122+
123+##############################################################################
124+# Compiler settings
125+#
126+
127+MCU = cortex-m3
128+
129+#TRGT = arm-elf-
130+TRGT = arm-none-eabi-
131+CC = $(TRGT)gcc
132+CPPC = $(TRGT)g++
133+# Enable loading with g++ only if you need C++ runtime support.
134+# NOTE: You can use C++ even without C++ support if you are careful. C++
135+# runtime support makes code size explode.
136+LD = $(TRGT)gcc
137+#LD = $(TRGT)g++
138+CP = $(TRGT)objcopy
139+AS = $(TRGT)gcc -x assembler-with-cpp
140+OD = $(TRGT)objdump
141+HEX = $(CP) -O ihex
142+BIN = $(CP) -O binary
143+
144+# ARM-specific options here
145+AOPT =
146+
147+# THUMB-specific options here
148+TOPT = -mthumb -DTHUMB
149+
150+# Define C warning options here
151+CWARN = -Wall -Wextra -Wstrict-prototypes
152+
153+# Define C++ warning options here
154+CPPWARN = -Wall -Wextra
155+
156+#
157+# Compiler settings
158+##############################################################################
159+
160+##############################################################################
161+# Start of default section
162+#
163+
164+# List all default C defines here, like -D_DEBUG=1
165+DDEFS = -DSTM32F10X_CL
166+
167+# List all default ASM defines here, like -D_DEBUG=1
168+DADEFS =
169+
170+# List all default directories to look for include files here
171+DINCDIR =
172+
173+# List the default directory to look for the libraries here
174+DLIBDIR =
175+
176+# List all default libraries here
177+DLIBS =
178+
179+#
180+# End of default section
181+##############################################################################
182+
183+##############################################################################
184+# Start of user section
185+#
186+
187+# List all user C define here, like -D_DEBUG=1
188+UDEFS =
189+
190+# Define ASM defines here
191+UADEFS =
192+
193+# List all user directories here
194+UINCDIR =
195+
196+# List the user directory to look for the libraries here
197+ULIBDIR =
198+
199+# List all user libraries here
200+ULIBS =
201+
202+#
203+# End of user defines
204+##############################################################################
205+
206+ifeq ($(USE_FWLIB),yes)
207+ include $(CHIBIOS)/ext/stm32lib/stm32lib.mk
208+ CSRC += $(STM32SRC)
209+ INCDIR += $(STM32INC)
210+ USE_OPT += -DUSE_STDPERIPH_DRIVER
211+endif
212+
213+include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk
--- branches/stm32_ethernet_wrapper/demos/ARMCM3-STM32F107-LWIP/chconf.h (nonexistent)
+++ branches/stm32_ethernet_wrapper/demos/ARMCM3-STM32F107-LWIP/chconf.h (revision 2871)
@@ -0,0 +1,513 @@
1+/*
2+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
3+ 2011 Giovanni Di Sirio.
4+
5+ This file is part of ChibiOS/RT.
6+
7+ ChibiOS/RT is free software; you can redistribute it and/or modify
8+ it under the terms of the GNU General Public License as published by
9+ the Free Software Foundation; either version 3 of the License, or
10+ (at your option) any later version.
11+
12+ ChibiOS/RT is distributed in the hope that it will be useful,
13+ but WITHOUT ANY WARRANTY; without even the implied warranty of
14+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15+ GNU General Public License for more details.
16+
17+ You should have received a copy of the GNU General Public License
18+ along with this program. If not, see <http://www.gnu.org/licenses/>.
19+*/
20+
21+/**
22+ * @file templates/chconf.h
23+ * @brief Configuration file template.
24+ * @details A copy of this file must be placed in each project directory, it
25+ * contains the application specific kernel settings.
26+ *
27+ * @addtogroup config
28+ * @details Kernel related settings and hooks.
29+ * @{
30+ */
31+
32+#ifndef _CHCONF_H_
33+#define _CHCONF_H_
34+
35+/*===========================================================================*/
36+/* Kernel parameters. */
37+/*===========================================================================*/
38+
39+/**
40+ * @brief System tick frequency.
41+ * @details Frequency of the system timer that drives the system ticks. This
42+ * setting also defines the system tick time unit.
43+ */
44+#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__)
45+#define CH_FREQUENCY 1000
46+#endif
47+
48+/**
49+ * @brief Round robin interval.
50+ * @details This constant is the number of system ticks allowed for the
51+ * threads before preemption occurs. Setting this value to zero
52+ * disables the preemption for threads with equal priority and the
53+ * round robin becomes cooperative. Note that higher priority
54+ * threads can still preempt, the kernel is always preemptive.
55+ *
56+ * @note Disabling the round robin preemption makes the kernel more compact
57+ * and generally faster.
58+ */
59+#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__)
60+#define CH_TIME_QUANTUM 20
61+#endif
62+
63+/**
64+ * @brief Nested locks.
65+ * @details If enabled then the use of nested @p chSysLock() / @p chSysUnlock()
66+ * operations is allowed.<br>
67+ * For performance and code size reasons the recommended setting
68+ * is to leave this option disabled.<br>
69+ * You may use this option if you need to merge ChibiOS/RT with
70+ * external libraries that require nested lock/unlock operations.
71+ *
72+ * @note The default is @p FALSE.
73+ */
74+#if !defined(CH_USE_NESTED_LOCKS) || defined(__DOXYGEN__)
75+#define CH_USE_NESTED_LOCKS FALSE
76+#endif
77+
78+/**
79+ * @brief Managed RAM size.
80+ * @details Size of the RAM area to be managed by the OS. If set to zero
81+ * then the whole available RAM is used. The core memory is made
82+ * available to the heap allocator and/or can be used directly through
83+ * the simplified core memory allocator.
84+ *
85+ * @note In order to let the OS manage the whole RAM the linker script must
86+ * provide the @p __heap_base__ and @p __heap_end__ symbols.
87+ * @note Requires @p CH_USE_COREMEM.
88+ */
89+#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__)
90+#define CH_MEMCORE_SIZE 0
91+#endif
92+
93+/*===========================================================================*/
94+/* Performance options. */
95+/*===========================================================================*/
96+
97+/**
98+ * @brief OS optimization.
99+ * @details If enabled then time efficient rather than space efficient code
100+ * is used when two possible implementations exist.
101+ *
102+ * @note This is not related to the compiler optimization options.
103+ * @note The default is @p TRUE.
104+ */
105+#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__)
106+#define CH_OPTIMIZE_SPEED TRUE
107+#endif
108+
109+/**
110+ * @brief Exotic optimization.
111+ * @details If defined then a CPU register is used as storage for the global
112+ * @p currp variable. Caching this variable in a register greatly
113+ * improves both space and time OS efficiency. A side effect is that
114+ * one less register has to be saved during the context switch
115+ * resulting in lower RAM usage and faster context switch.
116+ *
117+ * @note This option is only usable with the GCC compiler and is only useful
118+ * on processors with many registers like ARM cores.
119+ * @note If this option is enabled then ALL the libraries linked to the
120+ * ChibiOS/RT code <b>must</b> be recompiled with the GCC option @p
121+ * -ffixed-@<reg@>.
122+ * @note This option must be enabled in the Makefile, it is listed here for
123+ * documentation only.
124+ */
125+#if defined(__DOXYGEN__)
126+#define CH_CURRP_REGISTER_CACHE "reg"
127+#endif
128+
129+/*===========================================================================*/
130+/* Subsystem options. */
131+/*===========================================================================*/
132+
133+/**
134+ * @brief Threads registry APIs.
135+ * @details If enabled then the registry APIs are included in the kernel.
136+ *
137+ * @note The default is @p TRUE.
138+ */
139+#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__)
140+#define CH_USE_REGISTRY TRUE
141+#endif
142+
143+/**
144+ * @brief Threads synchronization APIs.
145+ * @details If enabled then the @p chThdWait() function is included in
146+ * the kernel.
147+ *
148+ * @note The default is @p TRUE.
149+ */
150+#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__)
151+#define CH_USE_WAITEXIT TRUE
152+#endif
153+
154+/**
155+ * @brief Semaphores APIs.
156+ * @details If enabled then the Semaphores APIs are included in the kernel.
157+ *
158+ * @note The default is @p TRUE.
159+ */
160+#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__)
161+#define CH_USE_SEMAPHORES TRUE
162+#endif
163+
164+/**
165+ * @brief Semaphores queuing mode.
166+ * @details If enabled then the threads are enqueued on semaphores by
167+ * priority rather than in FIFO order.
168+ *
169+ * @note The default is @p FALSE. Enable this if you have special requirements.
170+ * @note Requires @p CH_USE_SEMAPHORES.
171+ */
172+#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__)
173+#define CH_USE_SEMAPHORES_PRIORITY FALSE
174+#endif
175+
176+/**
177+ * @brief Atomic semaphore API.
178+ * @details If enabled then the semaphores the @p chSemSignalWait() API
179+ * is included in the kernel.
180+ *
181+ * @note The default is @p TRUE.
182+ * @note Requires @p CH_USE_SEMAPHORES.
183+ */
184+#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__)
185+#define CH_USE_SEMSW TRUE
186+#endif
187+
188+/**
189+ * @brief Mutexes APIs.
190+ * @details If enabled then the mutexes APIs are included in the kernel.
191+ *
192+ * @note The default is @p TRUE.
193+ */
194+#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__)
195+#define CH_USE_MUTEXES TRUE
196+#endif
197+
198+/**
199+ * @brief Conditional Variables APIs.
200+ * @details If enabled then the conditional variables APIs are included
201+ * in the kernel.
202+ *
203+ * @note The default is @p TRUE.
204+ * @note Requires @p CH_USE_MUTEXES.
205+ */
206+#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__)
207+#define CH_USE_CONDVARS TRUE
208+#endif
209+
210+/**
211+ * @brief Conditional Variables APIs with timeout.
212+ * @details If enabled then the conditional variables APIs with timeout
213+ * specification are included in the kernel.
214+ *
215+ * @note The default is @p TRUE.
216+ * @note Requires @p CH_USE_CONDVARS.
217+ */
218+#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__)
219+#define CH_USE_CONDVARS_TIMEOUT TRUE
220+#endif
221+
222+/**
223+ * @brief Events Flags APIs.
224+ * @details If enabled then the event flags APIs are included in the kernel.
225+ *
226+ * @note The default is @p TRUE.
227+ */
228+#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__)
229+#define CH_USE_EVENTS TRUE
230+#endif
231+
232+/**
233+ * @brief Events Flags APIs with timeout.
234+ * @details If enabled then the events APIs with timeout specification
235+ * are included in the kernel.
236+ *
237+ * @note The default is @p TRUE.
238+ * @note Requires @p CH_USE_EVENTS.
239+ */
240+#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__)
241+#define CH_USE_EVENTS_TIMEOUT TRUE
242+#endif
243+
244+/**
245+ * @brief Synchronous Messages APIs.
246+ * @details If enabled then the synchronous messages APIs are included
247+ * in the kernel.
248+ *
249+ * @note The default is @p TRUE.
250+ */
251+#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__)
252+#define CH_USE_MESSAGES TRUE
253+#endif
254+
255+/**
256+ * @brief Synchronous Messages queuing mode.
257+ * @details If enabled then messages are served by priority rather than in
258+ * FIFO order.
259+ *
260+ * @note The default is @p FALSE. Enable this if you have special requirements.
261+ * @note Requires @p CH_USE_MESSAGES.
262+ */
263+#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__)
264+#define CH_USE_MESSAGES_PRIORITY FALSE
265+#endif
266+
267+/**
268+ * @brief Mailboxes APIs.
269+ * @details If enabled then the asynchronous messages (mailboxes) APIs are
270+ * included in the kernel.
271+ *
272+ * @note The default is @p TRUE.
273+ * @note Requires @p CH_USE_SEMAPHORES.
274+ */
275+#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__)
276+#define CH_USE_MAILBOXES TRUE
277+#endif
278+
279+/**
280+ * @brief I/O Queues APIs.
281+ * @details If enabled then the I/O queues APIs are included in the kernel.
282+ *
283+ * @note The default is @p TRUE.
284+ * @note Requires @p CH_USE_SEMAPHORES.
285+ */
286+#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__)
287+#define CH_USE_QUEUES TRUE
288+#endif
289+
290+/**
291+ * @brief Core Memory Manager APIs.
292+ * @details If enabled then the core memory manager APIs are included
293+ * in the kernel.
294+ *
295+ * @note The default is @p TRUE.
296+ */
297+#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__)
298+#define CH_USE_MEMCORE TRUE
299+#endif
300+
301+/**
302+ * @brief Heap Allocator APIs.
303+ * @details If enabled then the memory heap allocator APIs are included
304+ * in the kernel.
305+ *
306+ * @note The default is @p TRUE.
307+ * @note Requires @p CH_USE_COREMEM and either @p CH_USE_MUTEXES or
308+ * @p CH_USE_SEMAPHORES.
309+ * @note Mutexes are recommended.
310+ */
311+#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__)
312+#define CH_USE_HEAP TRUE
313+#endif
314+
315+/**
316+ * @brief C-runtime allocator.
317+ * @details If enabled the the heap allocator APIs just wrap the C-runtime
318+ * @p malloc() and @p free() functions.
319+ *
320+ * @note The default is @p FALSE.
321+ * @note Requires @p CH_USE_HEAP.
322+ * @note The C-runtime may or may not require @p CH_USE_COREMEM, see the
323+ * appropriate documentation.
324+ */
325+#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__)
326+#define CH_USE_MALLOC_HEAP FALSE
327+#endif
328+
329+/**
330+ * @brief Memory Pools Allocator APIs.
331+ * @details If enabled then the memory pools allocator APIs are included
332+ * in the kernel.
333+ *
334+ * @note The default is @p TRUE.
335+ */
336+#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__)
337+#define CH_USE_MEMPOOLS TRUE
338+#endif
339+
340+/**
341+ * @brief Dynamic Threads APIs.
342+ * @details If enabled then the dynamic threads creation APIs are included
343+ * in the kernel.
344+ *
345+ * @note The default is @p TRUE.
346+ * @note Requires @p CH_USE_WAITEXIT.
347+ * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS.
348+ */
349+#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__)
350+#define CH_USE_DYNAMIC TRUE
351+#endif
352+
353+/*===========================================================================*/
354+/* Debug options. */
355+/*===========================================================================*/
356+
357+/**
358+ * @brief Debug option, parameters checks.
359+ * @details If enabled then the checks on the API functions input
360+ * parameters are activated.
361+ *
362+ * @note The default is @p FALSE.
363+ */
364+#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__)
365+#define CH_DBG_ENABLE_CHECKS TRUE
366+#endif
367+
368+/**
369+ * @brief Debug option, consistency checks.
370+ * @details If enabled then all the assertions in the kernel code are
371+ * activated. This includes consistency checks inside the kernel,
372+ * runtime anomalies and port-defined checks.
373+ *
374+ * @note The default is @p FALSE.
375+ */
376+#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__)
377+#define CH_DBG_ENABLE_ASSERTS TRUE
378+#endif
379+
380+/**
381+ * @brief Debug option, trace buffer.
382+ * @details If enabled then the context switch circular trace buffer is
383+ * activated.
384+ *
385+ * @note The default is @p FALSE.
386+ */
387+#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__)
388+#define CH_DBG_ENABLE_TRACE FALSE
389+#endif
390+
391+/**
392+ * @brief Debug option, stack checks.
393+ * @details If enabled then a runtime stack check is performed.
394+ *
395+ * @note The default is @p FALSE.
396+ * @note The stack check is performed in a architecture/port dependent way.
397+ * It may not be implemented or some ports.
398+ * @note The default failure mode is to halt the system with the global
399+ * @p panic_msg variable set to @p NULL.
400+ */
401+#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__)
402+#define CH_DBG_ENABLE_STACK_CHECK TRUE
403+#endif
404+
405+/**
406+ * @brief Debug option, stacks initialization.
407+ * @details If enabled then the threads working area is filled with a byte
408+ * value when a thread is created. This can be useful for the
409+ * runtime measurement of the used stack.
410+ *
411+ * @note The default is @p FALSE.
412+ */
413+#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__)
414+#define CH_DBG_FILL_THREADS TRUE
415+#endif
416+
417+/**
418+ * @brief Debug option, threads profiling.
419+ * @details If enabled then a field is added to the @p Thread structure that
420+ * counts the system ticks occurred while executing the thread.
421+ *
422+ * @note The default is @p TRUE.
423+ * @note This debug option is defaulted to TRUE because it is required by
424+ * some test cases into the test suite.
425+ */
426+#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__)
427+#define CH_DBG_THREADS_PROFILING TRUE
428+#endif
429+
430+/*===========================================================================*/
431+/* Kernel hooks. */
432+/*===========================================================================*/
433+
434+/**
435+ * @brief Threads descriptor structure extension.
436+ * @details User fields added to the end of the @p Thread structure.
437+ */
438+#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__)
439+#define THREAD_EXT_FIELDS \
440+struct { \
441+ /* Add threads custom fields here.*/ \
442+ /* Space for the LWIP sys_timeouts structure.*/ \
443+ void *p_lwipspace[1]; \
444+};
445+#endif
446+
447+/**
448+ * @brief Threads initialization hook.
449+ * @details User initialization code added to the @p chThdInit() API.
450+ *
451+ * @note It is invoked from within @p chThdInit() and implicitily from all
452+ * the threads creation APIs.
453+ */
454+#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__)
455+#define THREAD_EXT_INIT_HOOK(tp) { \
456+ /* Add threads initialization code here.*/ \
457+ (tp)->p_lwipspace[0] = NULL; \
458+}
459+#endif
460+
461+/**
462+ * @brief Threads finalization hook.
463+ * @details User finalization code added to the @p chThdExit() API.
464+ *
465+ * @note It is inserted into lock zone.
466+ * @note It is also invoked when the threads simply return in order to
467+ * terminate.
468+ */
469+#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__)
470+#define THREAD_EXT_EXIT_HOOK(tp) { \
471+ /* Add threads finalization code here.*/ \
472+}
473+#endif
474+
475+/**
476+ * @brief Idle Loop hook.
477+ * @details This hook is continuously invoked by the idle thread loop.
478+ */
479+#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__)
480+#define IDLE_LOOP_HOOK() { \
481+ /* Idle loop code here.*/ \
482+}
483+#endif
484+
485+/**
486+ * @brief System tick event hook.
487+ * @details This hook is invoked in the system tick handler immediately
488+ * after processing the virtual timers queue.
489+ */
490+#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__)
491+#define SYSTEM_TICK_EVENT_HOOK() { \
492+ /* System tick event code here.*/ \
493+}
494+#endif
495+
496+/**
497+ * @brief System halt hook.
498+ * @details This hook is invoked in case to a system halting error before
499+ * the system is halted.
500+ */
501+#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__)
502+#define SYSTEM_HALT_HOOK() { \
503+ /* System halt code here.*/ \
504+}
505+#endif
506+
507+/*===========================================================================*/
508+/* Port-specific settings (override port settings defaulted in chcore.h). */
509+/*===========================================================================*/
510+
511+#endif /* _CHCONF_H_ */
512+
513+/** @} */
--- branches/stm32_ethernet_wrapper/demos/ARMCM3-STM32F107-LWIP/halconf.h (nonexistent)
+++ branches/stm32_ethernet_wrapper/demos/ARMCM3-STM32F107-LWIP/halconf.h (revision 2871)
@@ -0,0 +1,281 @@
1+/*
2+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
3+ 2011 Giovanni Di Sirio.
4+
5+ This file is part of ChibiOS/RT.
6+
7+ ChibiOS/RT is free software; you can redistribute it and/or modify
8+ it under the terms of the GNU General Public License as published by
9+ the Free Software Foundation; either version 3 of the License, or
10+ (at your option) any later version.
11+
12+ ChibiOS/RT is distributed in the hope that it will be useful,
13+ but WITHOUT ANY WARRANTY; without even the implied warranty of
14+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15+ GNU General Public License for more details.
16+
17+ You should have received a copy of the GNU General Public License
18+ along with this program. If not, see <http://www.gnu.org/licenses/>.
19+*/
20+
21+/**
22+ * @file templates/halconf.h
23+ * @brief HAL configuration header.
24+ * @details HAL configuration file, this file allows to enable or disable the
25+ * various device drivers from your application. You may also use
26+ * this file in order to override the device drivers default settings.
27+ *
28+ * @addtogroup HAL_CONF
29+ * @{
30+ */
31+
32+#ifndef _HALCONF_H_
33+#define _HALCONF_H_
34+
35+#include "mcuconf.h"
36+
37+/**
38+ * @brief Enables the PAL subsystem.
39+ */
40+#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__)
41+#define HAL_USE_PAL TRUE
42+#endif
43+
44+/**
45+ * @brief Enables the ADC subsystem.
46+ */
47+#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__)
48+#define HAL_USE_ADC FALSE
49+#endif
50+
51+/**
52+ * @brief Enables the CAN subsystem.
53+ */
54+#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__)
55+#define HAL_USE_CAN FALSE
56+#endif
57+
58+/**
59+ * @brief Enables the GPT subsystem.
60+ */
61+#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__)
62+#define HAL_USE_GPT FALSE
63+#endif
64+
65+/**
66+ * @brief Enables the I2C subsystem.
67+ */
68+#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__)
69+#define HAL_USE_I2C FALSE
70+#endif
71+
72+/**
73+ * @brief Enables the MAC subsystem.
74+ */
75+#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__)
76+#define HAL_USE_MAC TRUE
77+#endif
78+
79+/**
80+ * @brief Enables the MMC_SPI subsystem.
81+ */
82+#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__)
83+#define HAL_USE_MMC_SPI FALSE
84+#endif
85+
86+/**
87+ * @brief Enables the PWM subsystem.
88+ */
89+#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__)
90+#define HAL_USE_PWM FALSE
91+#endif
92+
93+/**
94+ * @brief Enables the SERIAL subsystem.
95+ */
96+#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__)
97+#define HAL_USE_SERIAL TRUE
98+#endif
99+
100+/**
101+ * @brief Enables the SERIAL over USB subsystem.
102+ */
103+#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__)
104+#define HAL_USE_SERIAL_USB FALSE
105+#endif
106+
107+/**
108+ * @brief Enables the SPI subsystem.
109+ */
110+#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__)
111+#define HAL_USE_SPI FALSE
112+#endif
113+
114+/**
115+ * @brief Enables the UART subsystem.
116+ */
117+#if !defined(HAL_USE_UART) || defined(__DOXYGEN__)
118+#define HAL_USE_UART FALSE
119+#endif
120+
121+/**
122+ * @brief Enables the USB subsystem.
123+ */
124+#if !defined(HAL_USE_USB) || defined(__DOXYGEN__)
125+#define HAL_USE_USB FALSE
126+#endif
127+
128+/*===========================================================================*/
129+/* ADC driver related settings. */
130+/*===========================================================================*/
131+
132+/**
133+ * @brief Enables synchronous APIs.
134+ * @note Disabling this option saves both code and data space.
135+ */
136+#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__)
137+#define ADC_USE_WAIT TRUE
138+#endif
139+
140+/**
141+ * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs.
142+ * @note Disabling this option saves both code and data space.
143+ */
144+#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
145+#define ADC_USE_MUTUAL_EXCLUSION TRUE
146+#endif
147+
148+/*===========================================================================*/
149+/* CAN driver related settings. */
150+/*===========================================================================*/
151+
152+/**
153+ * @brief Sleep mode related APIs inclusion switch.
154+ */
155+#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__)
156+#define CAN_USE_SLEEP_MODE TRUE
157+#endif
158+
159+/*===========================================================================*/
160+/* I2C driver related settings. */
161+/*===========================================================================*/
162+
163+/**
164+ * @brief Enables the mutual exclusion APIs on the I2C bus.
165+ */
166+#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
167+#define I2C_USE_MUTUAL_EXCLUSION TRUE
168+#endif
169+
170+/*===========================================================================*/
171+/* MAC driver related settings. */
172+/*===========================================================================*/
173+
174+/*===========================================================================*/
175+/* MMC_SPI driver related settings. */
176+/*===========================================================================*/
177+
178+/**
179+ * @brief Block size for MMC transfers.
180+ */
181+#if !defined(MMC_SECTOR_SIZE) || defined(__DOXYGEN__)
182+#define MMC_SECTOR_SIZE 512
183+#endif
184+
185+/**
186+ * @brief Delays insertions.
187+ * @details If enabled this options inserts delays into the MMC waiting
188+ * routines releasing some extra CPU time for the threads with
189+ * lower priority, this may slow down the driver a bit however.
190+ * This option is recommended also if the SPI driver does not
191+ * use a DMA channel and heavily loads the CPU.
192+ */
193+#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__)
194+#define MMC_NICE_WAITING TRUE
195+#endif
196+
197+/**
198+ * @brief Number of positive insertion queries before generating the
199+ * insertion event.
200+ */
201+#if !defined(MMC_POLLING_INTERVAL) || defined(__DOXYGEN__)
202+#define MMC_POLLING_INTERVAL 10
203+#endif
204+
205+/**
206+ * @brief Interval, in milliseconds, between insertion queries.
207+ */
208+#if !defined(MMC_POLLING_DELAY) || defined(__DOXYGEN__)
209+#define MMC_POLLING_DELAY 10
210+#endif
211+
212+/**
213+ * @brief Uses the SPI polled API for small data transfers.
214+ * @details Polled transfers usually improve performance because it
215+ * saves two context switches and interrupt servicing. Note
216+ * that this option has no effect on large transfers which
217+ * are always performed using DMAs/IRQs.
218+ */
219+#if !defined(MMC_USE_SPI_POLLING) || defined(__DOXYGEN__)
220+#define MMC_USE_SPI_POLLING TRUE
221+#endif
222+
223+/*===========================================================================*/
224+/* PAL driver related settings. */
225+/*===========================================================================*/
226+
227+/*===========================================================================*/
228+/* PWM driver related settings. */
229+/*===========================================================================*/
230+
231+/*===========================================================================*/
232+/* SERIAL driver related settings. */
233+/*===========================================================================*/
234+
235+/**
236+ * @brief Default bit rate.
237+ * @details Configuration parameter, this is the baud rate selected for the
238+ * default configuration.
239+ */
240+#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__)
241+#define SERIAL_DEFAULT_BITRATE 38400
242+#endif
243+
244+/**
245+ * @brief Serial buffers size.
246+ * @details Configuration parameter, you can change the depth of the queue
247+ * buffers depending on the requirements of your application.
248+ * @note The default is 64 bytes for both the transmission and receive
249+ * buffers.
250+ */
251+#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__)
252+#define SERIAL_BUFFERS_SIZE 16
253+#endif
254+
255+/*===========================================================================*/
256+/* SPI driver related settings. */
257+/*===========================================================================*/
258+
259+/**
260+ * @brief Enables synchronous APIs.
261+ * @note Disabling this option saves both code and data space.
262+ */
263+#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__)
264+#define SPI_USE_WAIT TRUE
265+#endif
266+
267+/**
268+ * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs.
269+ * @note Disabling this option saves both code and data space.
270+ */
271+#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
272+#define SPI_USE_MUTUAL_EXCLUSION TRUE
273+#endif
274+
275+/*===========================================================================*/
276+/* UART driver related settings. */
277+/*===========================================================================*/
278+
279+#endif /* _HALCONF_H_ */
280+
281+/** @} */
--- branches/stm32_ethernet_wrapper/demos/ARMCM3-STM32F107-LWIP/lwipopts.h (nonexistent)
+++ branches/stm32_ethernet_wrapper/demos/ARMCM3-STM32F107-LWIP/lwipopts.h (revision 2871)
@@ -0,0 +1,1801 @@
1+/*
2+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
3+ * All rights reserved.
4+ *
5+ * Redistribution and use in source and binary forms, with or without modification,
6+ * are permitted provided that the following conditions are met:
7+ *
8+ * 1. Redistributions of source code must retain the above copyright notice,
9+ * this list of conditions and the following disclaimer.
10+ * 2. Redistributions in binary form must reproduce the above copyright notice,
11+ * this list of conditions and the following disclaimer in the documentation
12+ * and/or other materials provided with the distribution.
13+ * 3. The name of the author may not be used to endorse or promote products
14+ * derived from this software without specific prior written permission.
15+ *
16+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
17+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
19+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
20+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
21+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
23+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
24+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
25+ * OF SUCH DAMAGE.
26+ *
27+ * This file is part of the lwIP TCP/IP stack.
28+ *
29+ * Author: Adam Dunkels <adam@sics.se>
30+ *
31+ */
32+#ifndef __LWIPOPT_H__
33+#define __LWIPOPT_H__
34+
35+
36+/*
37+ -----------------------------------------------
38+ ---------- Platform specific locking ----------
39+ -----------------------------------------------
40+*/
41+
42+/**
43+ * SYS_LIGHTWEIGHT_PROT==1: if you want inter-task protection for certain
44+ * critical regions during buffer allocation, deallocation and memory
45+ * allocation and deallocation.
46+ */
47+#ifndef SYS_LIGHTWEIGHT_PROT
48+#define SYS_LIGHTWEIGHT_PROT 0
49+#endif
50+
51+/**
52+ * NO_SYS==1: Provides VERY minimal functionality. Otherwise,
53+ * use lwIP facilities.
54+ */
55+#ifndef NO_SYS
56+#define NO_SYS 0
57+#endif
58+
59+/**
60+ * MEMCPY: override this if you have a faster implementation at hand than the
61+ * one included in your C library
62+ */
63+#ifndef MEMCPY
64+#define MEMCPY(dst,src,len) memcpy(dst,src,len)
65+#endif
66+
67+/**
68+ * SMEMCPY: override this with care! Some compilers (e.g. gcc) can inline a
69+ * call to memcpy() if the length is known at compile time and is small.
70+ */
71+#ifndef SMEMCPY
72+#define SMEMCPY(dst,src,len) memcpy(dst,src,len)
73+#endif
74+
75+/*
76+ ------------------------------------
77+ ---------- Memory options ----------
78+ ------------------------------------
79+*/
80+/**
81+ * MEM_LIBC_MALLOC==1: Use malloc/free/realloc provided by your C-library
82+ * instead of the lwip internal allocator. Can save code size if you
83+ * already use it.
84+ */
85+#ifndef MEM_LIBC_MALLOC
86+#define MEM_LIBC_MALLOC 0
87+#endif
88+
89+/**
90+* MEMP_MEM_MALLOC==1: Use mem_malloc/mem_free instead of the lwip pool allocator.
91+* Especially useful with MEM_LIBC_MALLOC but handle with care regarding execution
92+* speed and usage from interrupts!
93+*/
94+#ifndef MEMP_MEM_MALLOC
95+#define MEMP_MEM_MALLOC 0
96+#endif
97+
98+/**
99+ * MEM_ALIGNMENT: should be set to the alignment of the CPU
100+ * 4 byte alignment -> #define MEM_ALIGNMENT 4
101+ * 2 byte alignment -> #define MEM_ALIGNMENT 2
102+ */
103+#ifndef MEM_ALIGNMENT
104+#define MEM_ALIGNMENT 4
105+#endif
106+
107+/**
108+ * MEM_SIZE: the size of the heap memory. If the application will send
109+ * a lot of data that needs to be copied, this should be set high.
110+ */
111+#ifndef MEM_SIZE
112+ #define MEM_SIZE 1600
113+#endif
114+
115+/**
116+ * MEMP_OVERFLOW_CHECK: memp overflow protection reserves a configurable
117+ * amount of bytes before and after each memp element in every pool and fills
118+ * it with a prominent default value.
119+ * MEMP_OVERFLOW_CHECK == 0 no checking
120+ * MEMP_OVERFLOW_CHECK == 1 checks each element when it is freed
121+ * MEMP_OVERFLOW_CHECK >= 2 checks each element in every pool every time
122+ * memp_malloc() or memp_free() is called (useful but slow!)
123+ */
124+#ifndef MEMP_OVERFLOW_CHECK
125+#define MEMP_OVERFLOW_CHECK 2
126+#endif
127+
128+/**
129+ * MEMP_SANITY_CHECK==1: run a sanity check after each memp_free() to make
130+ * sure that there are no cycles in the linked lists.
131+ */
132+#ifndef MEMP_SANITY_CHECK
133+#define MEMP_SANITY_CHECK 1
134+#endif
135+
136+/**
137+ * MEM_USE_POOLS==1: Use an alternative to malloc() by allocating from a set
138+ * of memory pools of various sizes. When mem_malloc is called, an element of
139+ * the smallest pool that can provide the length needed is returned.
140+ * To use this, MEMP_USE_CUSTOM_POOLS also has to be enabled.
141+ */
142+#ifndef MEM_USE_POOLS
143+#define MEM_USE_POOLS 0
144+#endif
145+
146+/**
147+ * MEM_USE_POOLS_TRY_BIGGER_POOL==1: if one malloc-pool is empty, try the next
148+ * bigger pool - WARNING: THIS MIGHT WASTE MEMORY but it can make a system more
149+ * reliable. */
150+#ifndef MEM_USE_POOLS_TRY_BIGGER_POOL
151+#define MEM_USE_POOLS_TRY_BIGGER_POOL 0
152+#endif
153+
154+/**
155+ * MEMP_USE_CUSTOM_POOLS==1: whether to include a user file lwippools.h
156+ * that defines additional pools beyond the "standard" ones required
157+ * by lwIP. If you set this to 1, you must have lwippools.h in your
158+ * inlude path somewhere.
159+ */
160+#ifndef MEMP_USE_CUSTOM_POOLS
161+#define MEMP_USE_CUSTOM_POOLS 0
162+#endif
163+
164+/**
165+ * Set this to 1 if you want to free PBUF_RAM pbufs (or call mem_free()) from
166+ * interrupt context (or another context that doesn't allow waiting for a
167+ * semaphore).
168+ * If set to 1, mem_malloc will be protected by a semaphore and SYS_ARCH_PROTECT,
169+ * while mem_free will only use SYS_ARCH_PROTECT. mem_malloc SYS_ARCH_UNPROTECTs
170+ * with each loop so that mem_free can run.
171+ *
172+ * ATTENTION: As you can see from the above description, this leads to dis-/
173+ * enabling interrupts often, which can be slow! Also, on low memory, mem_malloc
174+ * can need longer.
175+ *
176+ * If you don't want that, at least for NO_SYS=0, you can still use the following
177+ * functions to enqueue a deallocation call which then runs in the tcpip_thread
178+ * context:
179+ * - pbuf_free_callback(p);
180+ * - mem_free_callback(m);
181+ */
182+#ifndef LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT
183+#define LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT 0
184+#endif
185+
186+/*
187+ ------------------------------------------------
188+ ---------- Internal Memory Pool Sizes ----------
189+ ------------------------------------------------
190+*/
191+/**
192+ * MEMP_NUM_PBUF: the number of memp struct pbufs (used for PBUF_ROM and PBUF_REF).
193+ * If the application sends a lot of data out of ROM (or other static memory),
194+ * this should be set high.
195+ */
196+#ifndef MEMP_NUM_PBUF
197+#define MEMP_NUM_PBUF 16
198+#endif
199+
200+/**
201+ * MEMP_NUM_RAW_PCB: Number of raw connection PCBs
202+ * (requires the LWIP_RAW option)
203+ */
204+#ifndef MEMP_NUM_RAW_PCB
205+#define MEMP_NUM_RAW_PCB 4
206+#endif
207+
208+/**
209+ * MEMP_NUM_UDP_PCB: the number of UDP protocol control blocks. One
210+ * per active UDP "connection".
211+ * (requires the LWIP_UDP option)
212+ */
213+#ifndef MEMP_NUM_UDP_PCB
214+#define MEMP_NUM_UDP_PCB 4
215+#endif
216+
217+/**
218+ * MEMP_NUM_TCP_PCB: the number of simulatenously active TCP connections.
219+ * (requires the LWIP_TCP option)
220+ */
221+#ifndef MEMP_NUM_TCP_PCB
222+#define MEMP_NUM_TCP_PCB 5
223+#endif
224+
225+/**
226+ * MEMP_NUM_TCP_PCB_LISTEN: the number of listening TCP connections.
227+ * (requires the LWIP_TCP option)
228+ */
229+#ifndef MEMP_NUM_TCP_PCB_LISTEN
230+#define MEMP_NUM_TCP_PCB_LISTEN 8
231+#endif
232+
233+/**
234+ * MEMP_NUM_TCP_SEG: the number of simultaneously queued TCP segments.
235+ * (requires the LWIP_TCP option)
236+ */
237+#ifndef MEMP_NUM_TCP_SEG
238+#define MEMP_NUM_TCP_SEG 16
239+#endif
240+
241+/**
242+ * MEMP_NUM_REASSDATA: the number of simultaneously IP packets queued for
243+ * reassembly (whole packets, not fragments!)
244+ */
245+#ifndef MEMP_NUM_REASSDATA
246+#define MEMP_NUM_REASSDATA 5
247+#endif
248+
249+/**
250+ * MEMP_NUM_ARP_QUEUE: the number of simulateously queued outgoing
251+ * packets (pbufs) that are waiting for an ARP request (to resolve
252+ * their destination address) to finish.
253+ * (requires the ARP_QUEUEING option)
254+ */
255+#ifndef MEMP_NUM_ARP_QUEUE
256+#define MEMP_NUM_ARP_QUEUE 30
257+#endif
258+
259+/**
260+ * MEMP_NUM_IGMP_GROUP: The number of multicast groups whose network interfaces
261+ * can be members et the same time (one per netif - allsystems group -, plus one
262+ * per netif membership).
263+ * (requires the LWIP_IGMP option)
264+ */
265+#ifndef MEMP_NUM_IGMP_GROUP
266+#define MEMP_NUM_IGMP_GROUP 8
267+#endif
268+
269+/**
270+ * MEMP_NUM_SYS_TIMEOUT: the number of simulateously active timeouts.
271+ * (requires NO_SYS==0)
272+ */
273+#ifndef MEMP_NUM_SYS_TIMEOUT
274+#define MEMP_NUM_SYS_TIMEOUT (4 + LWIP_DHCP + LWIP_DNS)
275+#endif
276+
277+/**
278+ * MEMP_NUM_NETBUF: the number of struct netbufs.
279+ * (only needed if you use the sequential API, like api_lib.c)
280+ */
281+#ifndef MEMP_NUM_NETBUF
282+#define MEMP_NUM_NETBUF 2
283+#endif
284+
285+/**
286+ * MEMP_NUM_NETCONN: the number of struct netconns.
287+ * (only needed if you use the sequential API, like api_lib.c)
288+ */
289+#ifndef MEMP_NUM_NETCONN
290+#define MEMP_NUM_NETCONN 4
291+#endif
292+
293+/**
294+ * MEMP_NUM_TCPIP_MSG_API: the number of struct tcpip_msg, which are used
295+ * for callback/timeout API communication.
296+ * (only needed if you use tcpip.c)
297+ */
298+#ifndef MEMP_NUM_TCPIP_MSG_API
299+#define MEMP_NUM_TCPIP_MSG_API 8
300+#endif
301+
302+/**
303+ * MEMP_NUM_TCPIP_MSG_INPKT: the number of struct tcpip_msg, which are used
304+ * for incoming packets.
305+ * (only needed if you use tcpip.c)
306+ */
307+#ifndef MEMP_NUM_TCPIP_MSG_INPKT
308+#define MEMP_NUM_TCPIP_MSG_INPKT 8
309+#endif
310+
311+/**
312+ * PBUF_POOL_SIZE: the number of buffers in the pbuf pool.
313+ */
314+#ifndef PBUF_POOL_SIZE
315+#define PBUF_POOL_SIZE 16
316+#endif
317+
318+/*
319+ ---------------------------------
320+ ---------- ARP options ----------
321+ ---------------------------------
322+*/
323+/**
324+ * LWIP_ARP==1: Enable ARP functionality.
325+ */
326+#ifndef LWIP_ARP
327+#define LWIP_ARP 1
328+#endif
329+
330+/**
331+ * ARP_TABLE_SIZE: Number of active MAC-IP address pairs cached.
332+ */
333+#ifndef ARP_TABLE_SIZE
334+#define ARP_TABLE_SIZE 10
335+#endif
336+
337+/**
338+ * ARP_QUEUEING==1: Outgoing packets are queued during hardware address
339+ * resolution.
340+ */
341+#ifndef ARP_QUEUEING
342+#define ARP_QUEUEING 1
343+#endif
344+
345+/**
346+ * ETHARP_TRUST_IP_MAC==1: Incoming IP packets cause the ARP table to be
347+ * updated with the source MAC and IP addresses supplied in the packet.
348+ * You may want to disable this if you do not trust LAN peers to have the
349+ * correct addresses, or as a limited approach to attempt to handle
350+ * spoofing. If disabled, lwIP will need to make a new ARP request if
351+ * the peer is not already in the ARP table, adding a little latency.
352+ */
353+#ifndef ETHARP_TRUST_IP_MAC
354+#define ETHARP_TRUST_IP_MAC 1
355+#endif
356+
357+/*
358+ --------------------------------
359+ ---------- IP options ----------
360+ --------------------------------
361+*/
362+/**
363+ * IP_FORWARD==1: Enables the ability to forward IP packets across network
364+ * interfaces. If you are going to run lwIP on a device with only one network
365+ * interface, define this to 0.
366+ */
367+#ifndef IP_FORWARD
368+#define IP_FORWARD 0
369+#endif
370+
371+/**
372+ * IP_OPTIONS_ALLOWED: Defines the behavior for IP options.
373+ * IP_OPTIONS_ALLOWED==0: All packets with IP options are dropped.
374+ * IP_OPTIONS_ALLOWED==1: IP options are allowed (but not parsed).
375+ */
376+#ifndef IP_OPTIONS_ALLOWED
377+#define IP_OPTIONS_ALLOWED 1
378+#endif
379+
380+/**
381+ * IP_REASSEMBLY==1: Reassemble incoming fragmented IP packets. Note that
382+ * this option does not affect outgoing packet sizes, which can be controlled
383+ * via IP_FRAG.
384+ */
385+#ifndef IP_REASSEMBLY
386+#define IP_REASSEMBLY 1
387+#endif
388+
389+/**
390+ * IP_FRAG==1: Fragment outgoing IP packets if their size exceeds MTU. Note
391+ * that this option does not affect incoming packet sizes, which can be
392+ * controlled via IP_REASSEMBLY.
393+ */
394+#ifndef IP_FRAG
395+#define IP_FRAG 1
396+#endif
397+
398+/**
399+ * IP_REASS_MAXAGE: Maximum time (in multiples of IP_TMR_INTERVAL - so seconds, normally)
400+ * a fragmented IP packet waits for all fragments to arrive. If not all fragments arrived
401+ * in this time, the whole packet is discarded.
402+ */
403+#ifndef IP_REASS_MAXAGE
404+#define IP_REASS_MAXAGE 3
405+#endif
406+
407+/**
408+ * IP_REASS_MAX_PBUFS: Total maximum amount of pbufs waiting to be reassembled.
409+ * Since the received pbufs are enqueued, be sure to configure
410+ * PBUF_POOL_SIZE > IP_REASS_MAX_PBUFS so that the stack is still able to receive
411+ * packets even if the maximum amount of fragments is enqueued for reassembly!
412+ */
413+#ifndef IP_REASS_MAX_PBUFS
414+#define IP_REASS_MAX_PBUFS 10
415+#endif
416+
417+/**
418+ * IP_FRAG_USES_STATIC_BUF==1: Use a static MTU-sized buffer for IP
419+ * fragmentation. Otherwise pbufs are allocated and reference the original
420+ * packet data to be fragmented.
421+ */
422+#ifndef IP_FRAG_USES_STATIC_BUF
423+#define IP_FRAG_USES_STATIC_BUF 1
424+#endif
425+
426+/**
427+ * IP_FRAG_MAX_MTU: Assumed max MTU on any interface for IP frag buffer
428+ * (requires IP_FRAG_USES_STATIC_BUF==1)
429+ */
430+#if IP_FRAG_USES_STATIC_BUF && !defined(IP_FRAG_MAX_MTU)
431+#define IP_FRAG_MAX_MTU 1500
432+#endif
433+
434+/**
435+ * IP_DEFAULT_TTL: Default value for Time-To-Live used by transport layers.
436+ */
437+#ifndef IP_DEFAULT_TTL
438+#define IP_DEFAULT_TTL 255
439+#endif
440+
441+/**
442+ * IP_SOF_BROADCAST=1: Use the SOF_BROADCAST field to enable broadcast
443+ * filter per pcb on udp and raw send operations. To enable broadcast filter
444+ * on recv operations, you also have to set IP_SOF_BROADCAST_RECV=1.
445+ */
446+#ifndef IP_SOF_BROADCAST
447+#define IP_SOF_BROADCAST 0
448+#endif
449+
450+/**
451+ * IP_SOF_BROADCAST_RECV (requires IP_SOF_BROADCAST=1) enable the broadcast
452+ * filter on recv operations.
453+ */
454+#ifndef IP_SOF_BROADCAST_RECV
455+#define IP_SOF_BROADCAST_RECV 0
456+#endif
457+
458+/*
459+ ----------------------------------
460+ ---------- ICMP options ----------
461+ ----------------------------------
462+*/
463+/**
464+ * LWIP_ICMP==1: Enable ICMP module inside the IP stack.
465+ * Be careful, disable that make your product non-compliant to RFC1122
466+ */
467+#ifndef LWIP_ICMP
468+#define LWIP_ICMP 1
469+#endif
470+
471+/**
472+ * ICMP_TTL: Default value for Time-To-Live used by ICMP packets.
473+ */
474+#ifndef ICMP_TTL
475+#define ICMP_TTL (IP_DEFAULT_TTL)
476+#endif
477+
478+/**
479+ * LWIP_BROADCAST_PING==1: respond to broadcast pings (default is unicast only)
480+ */
481+#ifndef LWIP_BROADCAST_PING
482+#define LWIP_BROADCAST_PING 0
483+#endif
484+
485+/**
486+ * LWIP_MULTICAST_PING==1: respond to multicast pings (default is unicast only)
487+ */
488+#ifndef LWIP_MULTICAST_PING
489+#define LWIP_MULTICAST_PING 0
490+#endif
491+
492+/*
493+ ---------------------------------
494+ ---------- RAW options ----------
495+ ---------------------------------
496+*/
497+/**
498+ * LWIP_RAW==1: Enable application layer to hook into the IP layer itself.
499+ */
500+#ifndef LWIP_RAW
501+#define LWIP_RAW 1
502+#endif
503+
504+/**
505+ * LWIP_RAW==1: Enable application layer to hook into the IP layer itself.
506+ */
507+#ifndef RAW_TTL
508+#define RAW_TTL (IP_DEFAULT_TTL)
509+#endif
510+
511+/*
512+ ----------------------------------
513+ ---------- DHCP options ----------
514+ ----------------------------------
515+*/
516+/**
517+ * LWIP_DHCP==1: Enable DHCP module.
518+ */
519+#ifndef LWIP_DHCP
520+#define LWIP_DHCP 0
521+#endif
522+
523+/**
524+ * DHCP_DOES_ARP_CHECK==1: Do an ARP check on the offered address.
525+ */
526+#ifndef DHCP_DOES_ARP_CHECK
527+#define DHCP_DOES_ARP_CHECK ((LWIP_DHCP) && (LWIP_ARP))
528+#endif
529+
530+/*
531+ ------------------------------------
532+ ---------- AUTOIP options ----------
533+ ------------------------------------
534+*/
535+/**
536+ * LWIP_AUTOIP==1: Enable AUTOIP module.
537+ */
538+#ifndef LWIP_AUTOIP
539+#define LWIP_AUTOIP 0
540+#endif
541+
542+/**
543+ * LWIP_DHCP_AUTOIP_COOP==1: Allow DHCP and AUTOIP to be both enabled on
544+ * the same interface at the same time.
545+ */
546+#ifndef LWIP_DHCP_AUTOIP_COOP
547+#define LWIP_DHCP_AUTOIP_COOP 0
548+#endif
549+
550+/**
551+ * LWIP_DHCP_AUTOIP_COOP_TRIES: Set to the number of DHCP DISCOVER probes
552+ * that should be sent before falling back on AUTOIP. This can be set
553+ * as low as 1 to get an AutoIP address very quickly, but you should
554+ * be prepared to handle a changing IP address when DHCP overrides
555+ * AutoIP.
556+ */
557+#ifndef LWIP_DHCP_AUTOIP_COOP_TRIES
558+#define LWIP_DHCP_AUTOIP_COOP_TRIES 9
559+#endif
560+
561+/*
562+ ----------------------------------
563+ ---------- SNMP options ----------
564+ ----------------------------------
565+*/
566+/**
567+ * LWIP_SNMP==1: Turn on SNMP module. UDP must be available for SNMP
568+ * transport.
569+ */
570+#ifndef LWIP_SNMP
571+#define LWIP_SNMP 0
572+#endif
573+
574+/**
575+ * SNMP_CONCURRENT_REQUESTS: Number of concurrent requests the module will
576+ * allow. At least one request buffer is required.
577+ */
578+#ifndef SNMP_CONCURRENT_REQUESTS
579+#define SNMP_CONCURRENT_REQUESTS 1
580+#endif
581+
582+/**
583+ * SNMP_TRAP_DESTINATIONS: Number of trap destinations. At least one trap
584+ * destination is required
585+ */
586+#ifndef SNMP_TRAP_DESTINATIONS
587+#define SNMP_TRAP_DESTINATIONS 1
588+#endif
589+
590+/**
591+ * SNMP_PRIVATE_MIB:
592+ */
593+#ifndef SNMP_PRIVATE_MIB
594+#define SNMP_PRIVATE_MIB 0
595+#endif
596+
597+/**
598+ * Only allow SNMP write actions that are 'safe' (e.g. disabeling netifs is not
599+ * a safe action and disabled when SNMP_SAFE_REQUESTS = 1).
600+ * Unsafe requests are disabled by default!
601+ */
602+#ifndef SNMP_SAFE_REQUESTS
603+#define SNMP_SAFE_REQUESTS 1
604+#endif
605+
606+/*
607+ ----------------------------------
608+ ---------- IGMP options ----------
609+ ----------------------------------
610+*/
611+/**
612+ * LWIP_IGMP==1: Turn on IGMP module.
613+ */
614+#ifndef LWIP_IGMP
615+#define LWIP_IGMP 0
616+#endif
617+
618+/*
619+ ----------------------------------
620+ ---------- DNS options -----------
621+ ----------------------------------
622+*/
623+/**
624+ * LWIP_DNS==1: Turn on DNS module. UDP must be available for DNS
625+ * transport.
626+ */
627+#ifndef LWIP_DNS
628+#define LWIP_DNS 0
629+#endif
630+
631+/** DNS maximum number of entries to maintain locally. */
632+#ifndef DNS_TABLE_SIZE
633+#define DNS_TABLE_SIZE 4
634+#endif
635+
636+/** DNS maximum host name length supported in the name table. */
637+#ifndef DNS_MAX_NAME_LENGTH
638+#define DNS_MAX_NAME_LENGTH 256
639+#endif
640+
641+/** The maximum of DNS servers */
642+#ifndef DNS_MAX_SERVERS
643+#define DNS_MAX_SERVERS 2
644+#endif
645+
646+/** DNS do a name checking between the query and the response. */
647+#ifndef DNS_DOES_NAME_CHECK
648+#define DNS_DOES_NAME_CHECK 1
649+#endif
650+
651+/** DNS use a local buffer if DNS_USES_STATIC_BUF=0, a static one if
652+ DNS_USES_STATIC_BUF=1, or a dynamic one if DNS_USES_STATIC_BUF=2.
653+ The buffer will be of size DNS_MSG_SIZE */
654+#ifndef DNS_USES_STATIC_BUF
655+#define DNS_USES_STATIC_BUF 1
656+#endif
657+
658+/** DNS message max. size. Default value is RFC compliant. */
659+#ifndef DNS_MSG_SIZE
660+#define DNS_MSG_SIZE 512
661+#endif
662+
663+/** DNS_LOCAL_HOSTLIST: Implements a local host-to-address list. If enabled,
664+ * you have to define
665+ * #define DNS_LOCAL_HOSTLIST_INIT {{"host1", 0x123}, {"host2", 0x234}}
666+ * (an array of structs name/address, where address is an u32_t in network
667+ * byte order).
668+ *
669+ * Instead, you can also use an external function:
670+ * #define DNS_LOOKUP_LOCAL_EXTERN(x) extern u32_t my_lookup_function(const char *name)
671+ * that returns the IP address or INADDR_NONE if not found.
672+ */
673+#ifndef DNS_LOCAL_HOSTLIST
674+#define DNS_LOCAL_HOSTLIST 0
675+#endif /* DNS_LOCAL_HOSTLIST */
676+
677+/** If this is turned on, the local host-list can be dynamically changed
678+ * at runtime. */
679+#ifndef DNS_LOCAL_HOSTLIST_IS_DYNAMIC
680+#define DNS_LOCAL_HOSTLIST_IS_DYNAMIC 0
681+#endif /* DNS_LOCAL_HOSTLIST_IS_DYNAMIC */
682+
683+/*
684+ ---------------------------------
685+ ---------- UDP options ----------
686+ ---------------------------------
687+*/
688+/**
689+ * LWIP_UDP==1: Turn on UDP.
690+ */
691+#ifndef LWIP_UDP
692+#define LWIP_UDP 1
693+#endif
694+
695+/**
696+ * LWIP_UDPLITE==1: Turn on UDP-Lite. (Requires LWIP_UDP)
697+ */
698+#ifndef LWIP_UDPLITE
699+#define LWIP_UDPLITE 0
700+#endif
701+
702+/**
703+ * UDP_TTL: Default Time-To-Live value.
704+ */
705+#ifndef UDP_TTL
706+#define UDP_TTL (IP_DEFAULT_TTL)
707+#endif
708+
709+/*
710+ ---------------------------------
711+ ---------- TCP options ----------
712+ ---------------------------------
713+*/
714+/**
715+ * LWIP_TCP==1: Turn on TCP.
716+ */
717+#ifndef LWIP_TCP
718+#define LWIP_TCP 1
719+#endif
720+
721+/**
722+ * TCP_TTL: Default Time-To-Live value.
723+ */
724+#ifndef TCP_TTL
725+#define TCP_TTL (IP_DEFAULT_TTL)
726+#endif
727+
728+/**
729+ * TCP_WND: The size of a TCP window. This must be at least
730+ * (2 * TCP_MSS) for things to work well
731+ */
732+#ifndef TCP_WND
733+#define TCP_WND 2048
734+#endif
735+
736+/**
737+ * TCP_MAXRTX: Maximum number of retransmissions of data segments.
738+ */
739+#ifndef TCP_MAXRTX
740+#define TCP_MAXRTX 12
741+#endif
742+
743+/**
744+ * TCP_SYNMAXRTX: Maximum number of retransmissions of SYN segments.
745+ */
746+#ifndef TCP_SYNMAXRTX
747+#define TCP_SYNMAXRTX 6
748+#endif
749+
750+/**
751+ * TCP_QUEUE_OOSEQ==1: TCP will queue segments that arrive out of order.
752+ * Define to 0 if your device is low on memory.
753+ */
754+#ifndef TCP_QUEUE_OOSEQ
755+#define TCP_QUEUE_OOSEQ (LWIP_TCP)
756+#endif
757+
758+/**
759+ * TCP_MSS: TCP Maximum segment size. (default is 128, a *very*
760+ * conservative default.)
761+ * For the receive side, this MSS is advertised to the remote side
762+ * when opening a connection. For the transmit size, this MSS sets
763+ * an upper limit on the MSS advertised by the remote host.
764+ */
765+#ifndef TCP_MSS
766+#define TCP_MSS 128
767+#endif
768+
769+/**
770+ * TCP_CALCULATE_EFF_SEND_MSS: "The maximum size of a segment that TCP really
771+ * sends, the 'effective send MSS,' MUST be the smaller of the send MSS (which
772+ * reflects the available reassembly buffer size at the remote host) and the
773+ * largest size permitted by the IP layer" (RFC 1122)
774+ * Setting this to 1 enables code that checks TCP_MSS against the MTU of the
775+ * netif used for a connection and limits the MSS if it would be too big otherwise.
776+ */
777+#ifndef TCP_CALCULATE_EFF_SEND_MSS
778+#define TCP_CALCULATE_EFF_SEND_MSS 1
779+#endif
780+
781+
782+/**
783+ * TCP_SND_BUF: TCP sender buffer space (bytes).
784+ */
785+#ifndef TCP_SND_BUF
786+#define TCP_SND_BUF 256
787+#endif
788+
789+/**
790+ * TCP_SND_QUEUELEN: TCP sender buffer space (pbufs). This must be at least
791+ * as much as (2 * TCP_SND_BUF/TCP_MSS) for things to work.
792+ */
793+#ifndef TCP_SND_QUEUELEN
794+#define TCP_SND_QUEUELEN (4 * (TCP_SND_BUF/TCP_MSS))
795+#endif
796+
797+/**
798+ * TCP_SNDLOWAT: TCP writable space (bytes). This must be less than or equal
799+ * to TCP_SND_BUF. It is the amount of space which must be available in the
800+ * TCP snd_buf for select to return writable.
801+ */
802+#ifndef TCP_SNDLOWAT
803+#define TCP_SNDLOWAT (TCP_SND_BUF/2)
804+#endif
805+
806+/**
807+ * TCP_LISTEN_BACKLOG: Enable the backlog option for tcp listen pcb.
808+ */
809+#ifndef TCP_LISTEN_BACKLOG
810+#define TCP_LISTEN_BACKLOG 0
811+#endif
812+
813+/**
814+ * The maximum allowed backlog for TCP listen netconns.
815+ * This backlog is used unless another is explicitly specified.
816+ * 0xff is the maximum (u8_t).
817+ */
818+#ifndef TCP_DEFAULT_LISTEN_BACKLOG
819+#define TCP_DEFAULT_LISTEN_BACKLOG 0xff
820+#endif
821+
822+/**
823+ * LWIP_TCP_TIMESTAMPS==1: support the TCP timestamp option.
824+ */
825+#ifndef LWIP_TCP_TIMESTAMPS
826+#define LWIP_TCP_TIMESTAMPS 0
827+#endif
828+
829+/**
830+ * TCP_WND_UPDATE_THRESHOLD: difference in window to trigger an
831+ * explicit window update
832+ */
833+#ifndef TCP_WND_UPDATE_THRESHOLD
834+#define TCP_WND_UPDATE_THRESHOLD (TCP_WND / 4)
835+#endif
836+
837+/**
838+ * LWIP_EVENT_API and LWIP_CALLBACK_API: Only one of these should be set to 1.
839+ * LWIP_EVENT_API==1: The user defines lwip_tcp_event() to receive all
840+ * events (accept, sent, etc) that happen in the system.
841+ * LWIP_CALLBACK_API==1: The PCB callback function is called directly
842+ * for the event.
843+ */
844+//#define LWIP_EVENT_API
845+
846+/*
847+ ----------------------------------
848+ ---------- Pbuf options ----------
849+ ----------------------------------
850+*/
851+/**
852+ * PBUF_LINK_HLEN: the number of bytes that should be allocated for a
853+ * link level header. The default is 14, the standard value for
854+ * Ethernet.
855+ */
856+#ifndef PBUF_LINK_HLEN
857+#define PBUF_LINK_HLEN 14
858+#endif
859+
860+/**
861+ * PBUF_POOL_BUFSIZE: the size of each pbuf in the pbuf pool. The default is
862+ * designed to accomodate single full size TCP frame in one pbuf, including
863+ * TCP_MSS, IP header, and link header.
864+ */
865+#ifndef PBUF_POOL_BUFSIZE
866+#define PBUF_POOL_BUFSIZE LWIP_MEM_ALIGN_SIZE(TCP_MSS+40+PBUF_LINK_HLEN)
867+#endif
868+
869+/*
870+ ------------------------------------------------
871+ ---------- Network Interfaces options ----------
872+ ------------------------------------------------
873+*/
874+/**
875+ * LWIP_NETIF_HOSTNAME==1: use DHCP_OPTION_HOSTNAME with netif's hostname
876+ * field.
877+ */
878+#ifndef LWIP_NETIF_HOSTNAME
879+#define LWIP_NETIF_HOSTNAME 0
880+#endif
881+
882+/**
883+ * LWIP_NETIF_API==1: Support netif api (in netifapi.c)
884+ */
885+#ifndef LWIP_NETIF_API
886+#define LWIP_NETIF_API 0
887+#endif
888+
889+/**
890+ * LWIP_NETIF_STATUS_CALLBACK==1: Support a callback function whenever an interface
891+ * changes its up/down status (i.e., due to DHCP IP acquistion)
892+ */
893+#ifndef LWIP_NETIF_STATUS_CALLBACK
894+#define LWIP_NETIF_STATUS_CALLBACK 0
895+#endif
896+
897+/**
898+ * LWIP_NETIF_LINK_CALLBACK==1: Support a callback function from an interface
899+ * whenever the link changes (i.e., link down)
900+ */
901+#ifndef LWIP_NETIF_LINK_CALLBACK
902+#define LWIP_NETIF_LINK_CALLBACK 0
903+#endif
904+
905+/**
906+ * LWIP_NETIF_HWADDRHINT==1: Cache link-layer-address hints (e.g. table
907+ * indices) in struct netif. TCP and UDP can make use of this to prevent
908+ * scanning the ARP table for every sent packet. While this is faster for big
909+ * ARP tables or many concurrent connections, it might be counterproductive
910+ * if you have a tiny ARP table or if there never are concurrent connections.
911+ */
912+#ifndef LWIP_NETIF_HWADDRHINT
913+#define LWIP_NETIF_HWADDRHINT 0
914+#endif
915+
916+/**
917+ * LWIP_NETIF_LOOPBACK==1: Support sending packets with a destination IP
918+ * address equal to the netif IP address, looping them back up the stack.
919+ */
920+#ifndef LWIP_NETIF_LOOPBACK
921+#define LWIP_NETIF_LOOPBACK 0
922+#endif
923+
924+/**
925+ * LWIP_LOOPBACK_MAX_PBUFS: Maximum number of pbufs on queue for loopback
926+ * sending for each netif (0 = disabled)
927+ */
928+#ifndef LWIP_LOOPBACK_MAX_PBUFS
929+#define LWIP_LOOPBACK_MAX_PBUFS 0
930+#endif
931+
932+/**
933+ * LWIP_NETIF_LOOPBACK_MULTITHREADING: Indicates whether threading is enabled in
934+ * the system, as netifs must change how they behave depending on this setting
935+ * for the LWIP_NETIF_LOOPBACK option to work.
936+ * Setting this is needed to avoid reentering non-reentrant functions like
937+ * tcp_input().
938+ * LWIP_NETIF_LOOPBACK_MULTITHREADING==1: Indicates that the user is using a
939+ * multithreaded environment like tcpip.c. In this case, netif->input()
940+ * is called directly.
941+ * LWIP_NETIF_LOOPBACK_MULTITHREADING==0: Indicates a polling (or NO_SYS) setup.
942+ * The packets are put on a list and netif_poll() must be called in
943+ * the main application loop.
944+ */
945+#ifndef LWIP_NETIF_LOOPBACK_MULTITHREADING
946+#define LWIP_NETIF_LOOPBACK_MULTITHREADING (!NO_SYS)
947+#endif
948+
949+/**
950+ * LWIP_NETIF_TX_SINGLE_PBUF: if this is set to 1, lwIP tries to put all data
951+ * to be sent into one single pbuf. This is for compatibility with DMA-enabled
952+ * MACs that do not support scatter-gather.
953+ * Beware that this might involve CPU-memcpy before transmitting that would not
954+ * be needed without this flag! Use this only if you need to!
955+ *
956+ * @todo: TCP and IP-frag do not work with this, yet:
957+ */
958+#ifndef LWIP_NETIF_TX_SINGLE_PBUF
959+#define LWIP_NETIF_TX_SINGLE_PBUF 0
960+#endif /* LWIP_NETIF_TX_SINGLE_PBUF */
961+
962+/*
963+ ------------------------------------
964+ ---------- LOOPIF options ----------
965+ ------------------------------------
966+*/
967+/**
968+ * LWIP_HAVE_LOOPIF==1: Support loop interface (127.0.0.1) and loopif.c
969+ */
970+#ifndef LWIP_HAVE_LOOPIF
971+#define LWIP_HAVE_LOOPIF 0
972+#endif
973+
974+/*
975+ ------------------------------------
976+ ---------- SLIPIF options ----------
977+ ------------------------------------
978+*/
979+/**
980+ * LWIP_HAVE_SLIPIF==1: Support slip interface and slipif.c
981+ */
982+#ifndef LWIP_HAVE_SLIPIF
983+#define LWIP_HAVE_SLIPIF 0
984+#endif
985+
986+/*
987+ ------------------------------------
988+ ---------- Thread options ----------
989+ ------------------------------------
990+*/
991+/**
992+ * TCPIP_THREAD_NAME: The name assigned to the main tcpip thread.
993+ */
994+#ifndef TCPIP_THREAD_NAME
995+#define TCPIP_THREAD_NAME "tcpip_thread"
996+#endif
997+
998+/**
999+ * TCPIP_THREAD_STACKSIZE: The stack size used by the main tcpip thread.
1000+ * The stack size value itself is platform-dependent, but is passed to
1001+ * sys_thread_new() when the thread is created.
1002+ */
1003+#ifndef TCPIP_THREAD_STACKSIZE
1004+#define TCPIP_THREAD_STACKSIZE 2048
1005+#endif
1006+
1007+/**
1008+ * TCPIP_THREAD_PRIO: The priority assigned to the main tcpip thread.
1009+ * The priority value itself is platform-dependent, but is passed to
1010+ * sys_thread_new() when the thread is created.
1011+ */
1012+#ifndef TCPIP_THREAD_PRIO
1013+#define TCPIP_THREAD_PRIO (LOWPRIO + 1)
1014+#endif
1015+
1016+/**
1017+ * TCPIP_MBOX_SIZE: The mailbox size for the tcpip thread messages
1018+ * The queue size value itself is platform-dependent, but is passed to
1019+ * sys_mbox_new() when tcpip_init is called.
1020+ */
1021+#ifndef TCPIP_MBOX_SIZE
1022+#define TCPIP_MBOX_SIZE 4
1023+#endif
1024+
1025+/**
1026+ * SLIPIF_THREAD_NAME: The name assigned to the slipif_loop thread.
1027+ */
1028+#ifndef SLIPIF_THREAD_NAME
1029+#define SLIPIF_THREAD_NAME "slipif_loop"
1030+#endif
1031+
1032+/**
1033+ * SLIP_THREAD_STACKSIZE: The stack size used by the slipif_loop thread.
1034+ * The stack size value itself is platform-dependent, but is passed to
1035+ * sys_thread_new() when the thread is created.
1036+ */
1037+#ifndef SLIPIF_THREAD_STACKSIZE
1038+#define SLIPIF_THREAD_STACKSIZE 1024
1039+#endif
1040+
1041+/**
1042+ * SLIPIF_THREAD_PRIO: The priority assigned to the slipif_loop thread.
1043+ * The priority value itself is platform-dependent, but is passed to
1044+ * sys_thread_new() when the thread is created.
1045+ */
1046+#ifndef SLIPIF_THREAD_PRIO
1047+#define SLIPIF_THREAD_PRIO (LOWPRIO + 1)
1048+#endif
1049+
1050+/**
1051+ * PPP_THREAD_NAME: The name assigned to the pppMain thread.
1052+ */
1053+#ifndef PPP_THREAD_NAME
1054+#define PPP_THREAD_NAME "pppMain"
1055+#endif
1056+
1057+/**
1058+ * PPP_THREAD_STACKSIZE: The stack size used by the pppMain thread.
1059+ * The stack size value itself is platform-dependent, but is passed to
1060+ * sys_thread_new() when the thread is created.
1061+ */
1062+#ifndef PPP_THREAD_STACKSIZE
1063+#define PPP_THREAD_STACKSIZE 1024
1064+#endif
1065+
1066+/**
1067+ * PPP_THREAD_PRIO: The priority assigned to the pppMain thread.
1068+ * The priority value itself is platform-dependent, but is passed to
1069+ * sys_thread_new() when the thread is created.
1070+ */
1071+#ifndef PPP_THREAD_PRIO
1072+#define PPP_THREAD_PRIO (LOWPRIO + 1)
1073+#endif
1074+
1075+/**
1076+ * DEFAULT_THREAD_NAME: The name assigned to any other lwIP thread.
1077+ */
1078+#ifndef DEFAULT_THREAD_NAME
1079+#define DEFAULT_THREAD_NAME "lwIP"
1080+#endif
1081+
1082+/**
1083+ * DEFAULT_THREAD_STACKSIZE: The stack size used by any other lwIP thread.
1084+ * The stack size value itself is platform-dependent, but is passed to
1085+ * sys_thread_new() when the thread is created.
1086+ */
1087+#ifndef DEFAULT_THREAD_STACKSIZE
1088+#define DEFAULT_THREAD_STACKSIZE 1024
1089+#endif
1090+
1091+/**
1092+ * DEFAULT_THREAD_PRIO: The priority assigned to any other lwIP thread.
1093+ * The priority value itself is platform-dependent, but is passed to
1094+ * sys_thread_new() when the thread is created.
1095+ */
1096+#ifndef DEFAULT_THREAD_PRIO
1097+#define DEFAULT_THREAD_PRIO (LOWPRIO + 1)
1098+#endif
1099+
1100+/**
1101+ * DEFAULT_RAW_RECVMBOX_SIZE: The mailbox size for the incoming packets on a
1102+ * NETCONN_RAW. The queue size value itself is platform-dependent, but is passed
1103+ * to sys_mbox_new() when the recvmbox is created.
1104+ */
1105+#ifndef DEFAULT_RAW_RECVMBOX_SIZE
1106+#define DEFAULT_RAW_RECVMBOX_SIZE 4
1107+#endif
1108+
1109+/**
1110+ * DEFAULT_UDP_RECVMBOX_SIZE: The mailbox size for the incoming packets on a
1111+ * NETCONN_UDP. The queue size value itself is platform-dependent, but is passed
1112+ * to sys_mbox_new() when the recvmbox is created.
1113+ */
1114+#ifndef DEFAULT_UDP_RECVMBOX_SIZE
1115+#define DEFAULT_UDP_RECVMBOX_SIZE 4
1116+#endif
1117+
1118+/**
1119+ * DEFAULT_TCP_RECVMBOX_SIZE: The mailbox size for the incoming packets on a
1120+ * NETCONN_TCP. The queue size value itself is platform-dependent, but is passed
1121+ * to sys_mbox_new() when the recvmbox is created.
1122+ */
1123+#ifndef DEFAULT_TCP_RECVMBOX_SIZE
1124+#define DEFAULT_TCP_RECVMBOX_SIZE 40
1125+#endif
1126+
1127+/**
1128+ * DEFAULT_ACCEPTMBOX_SIZE: The mailbox size for the incoming connections.
1129+ * The queue size value itself is platform-dependent, but is passed to
1130+ * sys_mbox_new() when the acceptmbox is created.
1131+ */
1132+#ifndef DEFAULT_ACCEPTMBOX_SIZE
1133+#define DEFAULT_ACCEPTMBOX_SIZE 4
1134+#endif
1135+
1136+/*
1137+ ----------------------------------------------
1138+ ---------- Sequential layer options ----------
1139+ ----------------------------------------------
1140+*/
1141+/**
1142+ * LWIP_TCPIP_CORE_LOCKING: (EXPERIMENTAL!)
1143+ * Don't use it if you're not an active lwIP project member
1144+ */
1145+#ifndef LWIP_TCPIP_CORE_LOCKING
1146+#define LWIP_TCPIP_CORE_LOCKING 0
1147+#endif
1148+
1149+/**
1150+ * LWIP_NETCONN==1: Enable Netconn API (require to use api_lib.c)
1151+ */
1152+#ifndef LWIP_NETCONN
1153+#define LWIP_NETCONN 1
1154+#endif
1155+
1156+/*
1157+ ------------------------------------
1158+ ---------- Socket options ----------
1159+ ------------------------------------
1160+*/
1161+/**
1162+ * LWIP_SOCKET==1: Enable Socket API (require to use sockets.c)
1163+ */
1164+#ifndef LWIP_SOCKET
1165+#define LWIP_SOCKET 1
1166+#endif
1167+
1168+/**
1169+ * LWIP_COMPAT_SOCKETS==1: Enable BSD-style sockets functions names.
1170+ * (only used if you use sockets.c)
1171+ */
1172+#ifndef LWIP_COMPAT_SOCKETS
1173+#define LWIP_COMPAT_SOCKETS 1
1174+#endif
1175+
1176+/**
1177+ * LWIP_POSIX_SOCKETS_IO_NAMES==1: Enable POSIX-style sockets functions names.
1178+ * Disable this option if you use a POSIX operating system that uses the same
1179+ * names (read, write & close). (only used if you use sockets.c)
1180+ */
1181+#ifndef LWIP_POSIX_SOCKETS_IO_NAMES
1182+#define LWIP_POSIX_SOCKETS_IO_NAMES 1
1183+#endif
1184+
1185+/**
1186+ * LWIP_TCP_KEEPALIVE==1: Enable TCP_KEEPIDLE, TCP_KEEPINTVL and TCP_KEEPCNT
1187+ * options processing. Note that TCP_KEEPIDLE and TCP_KEEPINTVL have to be set
1188+ * in seconds. (does not require sockets.c, and will affect tcp.c)
1189+ */
1190+#ifndef LWIP_TCP_KEEPALIVE
1191+#define LWIP_TCP_KEEPALIVE 0
1192+#endif
1193+
1194+/**
1195+ * LWIP_SO_RCVTIMEO==1: Enable SO_RCVTIMEO processing.
1196+ */
1197+#ifndef LWIP_SO_RCVTIMEO
1198+#define LWIP_SO_RCVTIMEO 0
1199+#endif
1200+
1201+/**
1202+ * LWIP_SO_RCVBUF==1: Enable SO_RCVBUF processing.
1203+ */
1204+#ifndef LWIP_SO_RCVBUF
1205+#define LWIP_SO_RCVBUF 0
1206+#endif
1207+
1208+/**
1209+ * If LWIP_SO_RCVBUF is used, this is the default value for recv_bufsize.
1210+ */
1211+#ifndef RECV_BUFSIZE_DEFAULT
1212+#define RECV_BUFSIZE_DEFAULT INT_MAX
1213+#endif
1214+
1215+/**
1216+ * SO_REUSE==1: Enable SO_REUSEADDR and SO_REUSEPORT options. DO NOT USE!
1217+ */
1218+#ifndef SO_REUSE
1219+#define SO_REUSE 0
1220+#endif
1221+
1222+/*
1223+ ----------------------------------------
1224+ ---------- Statistics options ----------
1225+ ----------------------------------------
1226+*/
1227+/**
1228+ * LWIP_STATS==1: Enable statistics collection in lwip_stats.
1229+ */
1230+#ifndef LWIP_STATS
1231+#define LWIP_STATS 1
1232+#endif
1233+
1234+#if LWIP_STATS
1235+
1236+/**
1237+ * LWIP_STATS_DISPLAY==1: Compile in the statistics output functions.
1238+ */
1239+#ifndef LWIP_STATS_DISPLAY
1240+#define LWIP_STATS_DISPLAY 0
1241+#endif
1242+
1243+/**
1244+ * LINK_STATS==1: Enable link stats.
1245+ */
1246+#ifndef LINK_STATS
1247+#define LINK_STATS 1
1248+#endif
1249+
1250+/**
1251+ * ETHARP_STATS==1: Enable etharp stats.
1252+ */
1253+#ifndef ETHARP_STATS
1254+#define ETHARP_STATS (LWIP_ARP)
1255+#endif
1256+
1257+/**
1258+ * IP_STATS==1: Enable IP stats.
1259+ */
1260+#ifndef IP_STATS
1261+#define IP_STATS 1
1262+#endif
1263+
1264+/**
1265+ * IPFRAG_STATS==1: Enable IP fragmentation stats. Default is
1266+ * on if using either frag or reass.
1267+ */
1268+#ifndef IPFRAG_STATS
1269+#define IPFRAG_STATS (IP_REASSEMBLY || IP_FRAG)
1270+#endif
1271+
1272+/**
1273+ * ICMP_STATS==1: Enable ICMP stats.
1274+ */
1275+#ifndef ICMP_STATS
1276+#define ICMP_STATS 1
1277+#endif
1278+
1279+/**
1280+ * IGMP_STATS==1: Enable IGMP stats.
1281+ */
1282+#ifndef IGMP_STATS
1283+#define IGMP_STATS (LWIP_IGMP)
1284+#endif
1285+
1286+/**
1287+ * UDP_STATS==1: Enable UDP stats. Default is on if
1288+ * UDP enabled, otherwise off.
1289+ */
1290+#ifndef UDP_STATS
1291+#define UDP_STATS (LWIP_UDP)
1292+#endif
1293+
1294+/**
1295+ * TCP_STATS==1: Enable TCP stats. Default is on if TCP
1296+ * enabled, otherwise off.
1297+ */
1298+#ifndef TCP_STATS
1299+#define TCP_STATS (LWIP_TCP)
1300+#endif
1301+
1302+/**
1303+ * MEM_STATS==1: Enable mem.c stats.
1304+ */
1305+#ifndef MEM_STATS
1306+#define MEM_STATS 1
1307+#endif
1308+
1309+/**
1310+ * MEMP_STATS==1: Enable memp.c pool stats.
1311+ */
1312+#ifndef MEMP_STATS
1313+#define MEMP_STATS 1
1314+#endif
1315+
1316+/**
1317+ * SYS_STATS==1: Enable system stats (sem and mbox counts, etc).
1318+ */
1319+#ifndef SYS_STATS
1320+#define SYS_STATS 1
1321+#endif
1322+
1323+#else
1324+
1325+#define LINK_STATS 0
1326+#define IP_STATS 0
1327+#define IPFRAG_STATS 0
1328+#define ICMP_STATS 0
1329+#define IGMP_STATS 0
1330+#define UDP_STATS 0
1331+#define TCP_STATS 0
1332+#define MEM_STATS 0
1333+#define MEMP_STATS 0
1334+#define SYS_STATS 0
1335+#define LWIP_STATS_DISPLAY 0
1336+
1337+#endif /* LWIP_STATS */
1338+
1339+/*
1340+ ---------------------------------
1341+ ---------- PPP options ----------
1342+ ---------------------------------
1343+*/
1344+/**
1345+ * PPP_SUPPORT==1: Enable PPP.
1346+ */
1347+#ifndef PPP_SUPPORT
1348+#define PPP_SUPPORT 0
1349+#endif
1350+
1351+/**
1352+ * PPPOE_SUPPORT==1: Enable PPP Over Ethernet
1353+ */
1354+#ifndef PPPOE_SUPPORT
1355+#define PPPOE_SUPPORT 0
1356+#endif
1357+
1358+/**
1359+ * PPPOS_SUPPORT==1: Enable PPP Over Serial
1360+ */
1361+#ifndef PPPOS_SUPPORT
1362+#define PPPOS_SUPPORT PPP_SUPPORT
1363+#endif
1364+
1365+#if PPP_SUPPORT
1366+
1367+/**
1368+ * NUM_PPP: Max PPP sessions.
1369+ */
1370+#ifndef NUM_PPP
1371+#define NUM_PPP 1
1372+#endif
1373+
1374+/**
1375+ * PAP_SUPPORT==1: Support PAP.
1376+ */
1377+#ifndef PAP_SUPPORT
1378+#define PAP_SUPPORT 0
1379+#endif
1380+
1381+/**
1382+ * CHAP_SUPPORT==1: Support CHAP.
1383+ */
1384+#ifndef CHAP_SUPPORT
1385+#define CHAP_SUPPORT 0
1386+#endif
1387+
1388+/**
1389+ * MSCHAP_SUPPORT==1: Support MSCHAP. CURRENTLY NOT SUPPORTED! DO NOT SET!
1390+ */
1391+#ifndef MSCHAP_SUPPORT
1392+#define MSCHAP_SUPPORT 0
1393+#endif
1394+
1395+/**
1396+ * CBCP_SUPPORT==1: Support CBCP. CURRENTLY NOT SUPPORTED! DO NOT SET!
1397+ */
1398+#ifndef CBCP_SUPPORT
1399+#define CBCP_SUPPORT 0
1400+#endif
1401+
1402+/**
1403+ * CCP_SUPPORT==1: Support CCP. CURRENTLY NOT SUPPORTED! DO NOT SET!
1404+ */
1405+#ifndef CCP_SUPPORT
1406+#define CCP_SUPPORT 0
1407+#endif
1408+
1409+/**
1410+ * VJ_SUPPORT==1: Support VJ header compression.
1411+ */
1412+#ifndef VJ_SUPPORT
1413+#define VJ_SUPPORT 0
1414+#endif
1415+
1416+/**
1417+ * MD5_SUPPORT==1: Support MD5 (see also CHAP).
1418+ */
1419+#ifndef MD5_SUPPORT
1420+#define MD5_SUPPORT 0
1421+#endif
1422+
1423+/*
1424+ * Timeouts
1425+ */
1426+#ifndef FSM_DEFTIMEOUT
1427+#define FSM_DEFTIMEOUT 6 /* Timeout time in seconds */
1428+#endif
1429+
1430+#ifndef FSM_DEFMAXTERMREQS
1431+#define FSM_DEFMAXTERMREQS 2 /* Maximum Terminate-Request transmissions */
1432+#endif
1433+
1434+#ifndef FSM_DEFMAXCONFREQS
1435+#define FSM_DEFMAXCONFREQS 10 /* Maximum Configure-Request transmissions */
1436+#endif
1437+
1438+#ifndef FSM_DEFMAXNAKLOOPS
1439+#define FSM_DEFMAXNAKLOOPS 5 /* Maximum number of nak loops */
1440+#endif
1441+
1442+#ifndef UPAP_DEFTIMEOUT
1443+#define UPAP_DEFTIMEOUT 6 /* Timeout (seconds) for retransmitting req */
1444+#endif
1445+
1446+#ifndef UPAP_DEFREQTIME
1447+#define UPAP_DEFREQTIME 30 /* Time to wait for auth-req from peer */
1448+#endif
1449+
1450+#ifndef CHAP_DEFTIMEOUT
1451+#define CHAP_DEFTIMEOUT 6 /* Timeout time in seconds */
1452+#endif
1453+
1454+#ifndef CHAP_DEFTRANSMITS
1455+#define CHAP_DEFTRANSMITS 10 /* max # times to send challenge */
1456+#endif
1457+
1458+/* Interval in seconds between keepalive echo requests, 0 to disable. */
1459+#ifndef LCP_ECHOINTERVAL
1460+#define LCP_ECHOINTERVAL 0
1461+#endif
1462+
1463+/* Number of unanswered echo requests before failure. */
1464+#ifndef LCP_MAXECHOFAILS
1465+#define LCP_MAXECHOFAILS 3
1466+#endif
1467+
1468+/* Max Xmit idle time (in jiffies) before resend flag char. */
1469+#ifndef PPP_MAXIDLEFLAG
1470+#define PPP_MAXIDLEFLAG 100
1471+#endif
1472+
1473+/*
1474+ * Packet sizes
1475+ *
1476+ * Note - lcp shouldn't be allowed to negotiate stuff outside these
1477+ * limits. See lcp.h in the pppd directory.
1478+ * (XXX - these constants should simply be shared by lcp.c instead
1479+ * of living in lcp.h)
1480+ */
1481+#define PPP_MTU 1500 /* Default MTU (size of Info field) */
1482+#ifndef PPP_MAXMTU
1483+/* #define PPP_MAXMTU 65535 - (PPP_HDRLEN + PPP_FCSLEN) */
1484+#define PPP_MAXMTU 1500 /* Largest MTU we allow */
1485+#endif
1486+#define PPP_MINMTU 64
1487+#define PPP_MRU 1500 /* default MRU = max length of info field */
1488+#define PPP_MAXMRU 1500 /* Largest MRU we allow */
1489+#ifndef PPP_DEFMRU
1490+#define PPP_DEFMRU 296 /* Try for this */
1491+#endif
1492+#define PPP_MINMRU 128 /* No MRUs below this */
1493+
1494+
1495+#define MAXNAMELEN 256 /* max length of hostname or name for auth */
1496+#define MAXSECRETLEN 256 /* max length of password or secret */
1497+
1498+#endif /* PPP_SUPPORT */
1499+
1500+/*
1501+ --------------------------------------
1502+ ---------- Checksum options ----------
1503+ --------------------------------------
1504+*/
1505+/**
1506+ * CHECKSUM_GEN_IP==1: Generate checksums in software for outgoing IP packets.
1507+ */
1508+#ifndef CHECKSUM_GEN_IP
1509+#define CHECKSUM_GEN_IP 0
1510+#endif
1511+
1512+/**
1513+ * CHECKSUM_GEN_UDP==1: Generate checksums in software for outgoing UDP packets.
1514+ */
1515+#ifndef CHECKSUM_GEN_UDP
1516+#define CHECKSUM_GEN_UDP 0
1517+#endif
1518+
1519+/**
1520+ * CHECKSUM_GEN_TCP==1: Generate checksums in software for outgoing TCP packets.
1521+ */
1522+#ifndef CHECKSUM_GEN_TCP
1523+#define CHECKSUM_GEN_TCP 0
1524+#endif
1525+
1526+/**
1527+ * CHECKSUM_CHECK_IP==1: Check checksums in software for incoming IP packets.
1528+ */
1529+#ifndef CHECKSUM_CHECK_IP
1530+#define CHECKSUM_CHECK_IP 0
1531+#endif
1532+
1533+/**
1534+ * CHECKSUM_CHECK_UDP==1: Check checksums in software for incoming UDP packets.
1535+ */
1536+#ifndef CHECKSUM_CHECK_UDP
1537+#define CHECKSUM_CHECK_UDP 0
1538+#endif
1539+
1540+/**
1541+ * CHECKSUM_CHECK_TCP==1: Check checksums in software for incoming TCP packets.
1542+ */
1543+#ifndef CHECKSUM_CHECK_TCP
1544+#define CHECKSUM_CHECK_TCP 0
1545+#endif
1546+
1547+/*
1548+ ---------------------------------------
1549+ ---------- Debugging options ----------
1550+ ---------------------------------------
1551+*/
1552+/**
1553+ * LWIP_DBG_MIN_LEVEL: After masking, the value of the debug is
1554+ * compared against this value. If it is smaller, then debugging
1555+ * messages are written.
1556+ */
1557+#ifndef LWIP_DBG_MIN_LEVEL
1558+#define LWIP_DBG_MIN_LEVEL LWIP_DBG_LEVEL_OFF
1559+#endif
1560+
1561+/**
1562+ * LWIP_DBG_TYPES_ON: A mask that can be used to globally enable/disable
1563+ * debug messages of certain types.
1564+ */
1565+#ifndef LWIP_DBG_TYPES_ON
1566+#define LWIP_DBG_TYPES_ON LWIP_DBG_ON
1567+#endif
1568+
1569+/**
1570+ * ETHARP_DEBUG: Enable debugging in etharp.c.
1571+ */
1572+#ifndef ETHARP_DEBUG
1573+#define ETHARP_DEBUG LWIP_DBG_OFF
1574+#endif
1575+
1576+/**
1577+ * NETIF_DEBUG: Enable debugging in netif.c.
1578+ */
1579+#ifndef NETIF_DEBUG
1580+#define NETIF_DEBUG LWIP_DBG_OFF
1581+#endif
1582+
1583+/**
1584+ * PBUF_DEBUG: Enable debugging in pbuf.c.
1585+ */
1586+#ifndef PBUF_DEBUG
1587+#define PBUF_DEBUG LWIP_DBG_OFF
1588+#endif
1589+
1590+/**
1591+ * API_LIB_DEBUG: Enable debugging in api_lib.c.
1592+ */
1593+#ifndef API_LIB_DEBUG
1594+#define API_LIB_DEBUG LWIP_DBG_OFF
1595+#endif
1596+
1597+/**
1598+ * API_MSG_DEBUG: Enable debugging in api_msg.c.
1599+ */
1600+#ifndef API_MSG_DEBUG
1601+#define API_MSG_DEBUG LWIP_DBG_OFF
1602+#endif
1603+
1604+/**
1605+ * SOCKETS_DEBUG: Enable debugging in sockets.c.
1606+ */
1607+#ifndef SOCKETS_DEBUG
1608+#define SOCKETS_DEBUG LWIP_DBG_OFF
1609+#endif
1610+
1611+/**
1612+ * ICMP_DEBUG: Enable debugging in icmp.c.
1613+ */
1614+#ifndef ICMP_DEBUG
1615+#define ICMP_DEBUG LWIP_DBG_OFF
1616+#endif
1617+
1618+/**
1619+ * IGMP_DEBUG: Enable debugging in igmp.c.
1620+ */
1621+#ifndef IGMP_DEBUG
1622+#define IGMP_DEBUG LWIP_DBG_OFF
1623+#endif
1624+
1625+/**
1626+ * INET_DEBUG: Enable debugging in inet.c.
1627+ */
1628+#ifndef INET_DEBUG
1629+#define INET_DEBUG LWIP_DBG_OFF
1630+#endif
1631+
1632+/**
1633+ * IP_DEBUG: Enable debugging for IP.
1634+ */
1635+#ifndef IP_DEBUG
1636+#define IP_DEBUG LWIP_DBG_OFF
1637+#endif
1638+
1639+/**
1640+ * IP_REASS_DEBUG: Enable debugging in ip_frag.c for both frag & reass.
1641+ */
1642+#ifndef IP_REASS_DEBUG
1643+#define IP_REASS_DEBUG LWIP_DBG_OFF
1644+#endif
1645+
1646+/**
1647+ * RAW_DEBUG: Enable debugging in raw.c.
1648+ */
1649+#ifndef RAW_DEBUG
1650+#define RAW_DEBUG LWIP_DBG_OFF
1651+#endif
1652+
1653+/**
1654+ * MEM_DEBUG: Enable debugging in mem.c.
1655+ */
1656+#ifndef MEM_DEBUG
1657+#define MEM_DEBUG LWIP_DBG_OFF
1658+#endif
1659+
1660+/**
1661+ * MEMP_DEBUG: Enable debugging in memp.c.
1662+ */
1663+#ifndef MEMP_DEBUG
1664+#define MEMP_DEBUG LWIP_DBG_OFF
1665+#endif
1666+
1667+/**
1668+ * SYS_DEBUG: Enable debugging in sys.c.
1669+ */
1670+#ifndef SYS_DEBUG
1671+#define SYS_DEBUG LWIP_DBG_OFF
1672+#endif
1673+
1674+/**
1675+ * TCP_DEBUG: Enable debugging for TCP.
1676+ */
1677+#ifndef TCP_DEBUG
1678+#define TCP_DEBUG LWIP_DBG_OFF
1679+#endif
1680+
1681+/**
1682+ * TCP_INPUT_DEBUG: Enable debugging in tcp_in.c for incoming debug.
1683+ */
1684+#ifndef TCP_INPUT_DEBUG
1685+#define TCP_INPUT_DEBUG LWIP_DBG_OFF
1686+#endif
1687+
1688+/**
1689+ * TCP_FR_DEBUG: Enable debugging in tcp_in.c for fast retransmit.
1690+ */
1691+#ifndef TCP_FR_DEBUG
1692+#define TCP_FR_DEBUG LWIP_DBG_OFF
1693+#endif
1694+
1695+/**
1696+ * TCP_RTO_DEBUG: Enable debugging in TCP for retransmit
1697+ * timeout.
1698+ */
1699+#ifndef TCP_RTO_DEBUG
1700+#define TCP_RTO_DEBUG LWIP_DBG_OFF
1701+#endif
1702+
1703+/**
1704+ * TCP_CWND_DEBUG: Enable debugging for TCP congestion window.
1705+ */
1706+#ifndef TCP_CWND_DEBUG
1707+#define TCP_CWND_DEBUG LWIP_DBG_OFF
1708+#endif
1709+
1710+/**
1711+ * TCP_WND_DEBUG: Enable debugging in tcp_in.c for window updating.
1712+ */
1713+#ifndef TCP_WND_DEBUG
1714+#define TCP_WND_DEBUG LWIP_DBG_OFF
1715+#endif
1716+
1717+/**
1718+ * TCP_OUTPUT_DEBUG: Enable debugging in tcp_out.c output functions.
1719+ */
1720+#ifndef TCP_OUTPUT_DEBUG
1721+#define TCP_OUTPUT_DEBUG LWIP_DBG_OFF
1722+#endif
1723+
1724+/**
1725+ * TCP_RST_DEBUG: Enable debugging for TCP with the RST message.
1726+ */
1727+#ifndef TCP_RST_DEBUG
1728+#define TCP_RST_DEBUG LWIP_DBG_OFF
1729+#endif
1730+
1731+/**
1732+ * TCP_QLEN_DEBUG: Enable debugging for TCP queue lengths.
1733+ */
1734+#ifndef TCP_QLEN_DEBUG
1735+#define TCP_QLEN_DEBUG LWIP_DBG_OFF
1736+#endif
1737+
1738+/**
1739+ * UDP_DEBUG: Enable debugging in UDP.
1740+ */
1741+#ifndef UDP_DEBUG
1742+#define UDP_DEBUG LWIP_DBG_OFF
1743+#endif
1744+
1745+/**
1746+ * TCPIP_DEBUG: Enable debugging in tcpip.c.
1747+ */
1748+#ifndef TCPIP_DEBUG
1749+#define TCPIP_DEBUG LWIP_DBG_OFF
1750+#endif
1751+
1752+/**
1753+ * PPP_DEBUG: Enable debugging for PPP.
1754+ */
1755+#ifndef PPP_DEBUG
1756+#define PPP_DEBUG LWIP_DBG_OFF
1757+#endif
1758+
1759+/**
1760+ * SLIP_DEBUG: Enable debugging in slipif.c.
1761+ */
1762+#ifndef SLIP_DEBUG
1763+#define SLIP_DEBUG LWIP_DBG_OFF
1764+#endif
1765+
1766+/**
1767+ * DHCP_DEBUG: Enable debugging in dhcp.c.
1768+ */
1769+#ifndef DHCP_DEBUG
1770+#define DHCP_DEBUG LWIP_DBG_OFF
1771+#endif
1772+
1773+/**
1774+ * AUTOIP_DEBUG: Enable debugging in autoip.c.
1775+ */
1776+#ifndef AUTOIP_DEBUG
1777+#define AUTOIP_DEBUG LWIP_DBG_OFF
1778+#endif
1779+
1780+/**
1781+ * SNMP_MSG_DEBUG: Enable debugging for SNMP messages.
1782+ */
1783+#ifndef SNMP_MSG_DEBUG
1784+#define SNMP_MSG_DEBUG LWIP_DBG_OFF
1785+#endif
1786+
1787+/**
1788+ * SNMP_MIB_DEBUG: Enable debugging for SNMP MIBs.
1789+ */
1790+#ifndef SNMP_MIB_DEBUG
1791+#define SNMP_MIB_DEBUG LWIP_DBG_OFF
1792+#endif
1793+
1794+/**
1795+ * DNS_DEBUG: Enable debugging for DNS.
1796+ */
1797+#ifndef DNS_DEBUG
1798+#define DNS_DEBUG LWIP_DBG_OFF
1799+#endif
1800+
1801+#endif /* __LWIPOPT_H__ */
--- branches/stm32_ethernet_wrapper/demos/ARMCM3-STM32F107-LWIP/main.c (nonexistent)
+++ branches/stm32_ethernet_wrapper/demos/ARMCM3-STM32F107-LWIP/main.c (revision 2871)
@@ -0,0 +1,88 @@
1+/*
2+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
3+ 2011 Giovanni Di Sirio.
4+
5+ This file is part of ChibiOS/RT.
6+
7+ ChibiOS/RT is free software; you can redistribute it and/or modify
8+ it under the terms of the GNU General Public License as published by
9+ the Free Software Foundation; either version 3 of the License, or
10+ (at your option) any later version.
11+
12+ ChibiOS/RT is distributed in the hope that it will be useful,
13+ but WITHOUT ANY WARRANTY; without even the implied warranty of
14+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15+ GNU General Public License for more details.
16+
17+ You should have received a copy of the GNU General Public License
18+ along with this program. If not, see <http://www.gnu.org/licenses/>.
19+*/
20+
21+#include "ch.h"
22+#include "hal.h"
23+#include "test.h"
24+#include "lwip/lwipthread.h"
25+#include "web/web.h"
26+
27+/*
28+ * Green LED blinker thread, times are in milliseconds.
29+ */
30+static WORKING_AREA(waThread1, 128);
31+static msg_t Thread1(void *arg) {
32+
33+ (void)arg;
34+ while (TRUE) {
35+ palClearPad(GPIOC, GPIOC_LED_STATUS1);
36+ chThdSleepMilliseconds(500);
37+ palSetPad(GPIOC, GPIOC_LED_STATUS1);
38+ chThdSleepMilliseconds(500);
39+ }
40+}
41+
42+/*
43+ * Application entry point.
44+ */
45+int main(void) {
46+
47+ /*
48+ * System initializations.
49+ * - HAL initialization, this also initializes the configured device drivers
50+ * and performs the board-specific initializations.
51+ * - Kernel initialization, the main() function becomes a thread and the
52+ * RTOS is active.
53+ */
54+ halInit();
55+ chSysInit();
56+
57+ /*
58+ * Activates the serial driver 2 using the driver default configuration.
59+ */
60+ sdStart(&SD3, NULL);
61+
62+ /*
63+ * Creates the blinker thread.
64+ */
65+ chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL);
66+
67+ /*
68+ * Creates the LWIP threads (it changes priority internally).
69+ */
70+ chThdCreateStatic(wa_lwip_thread, LWIP_THREAD_STACK_SIZE, NORMALPRIO + 1,
71+ lwip_thread, NULL);
72+
73+ /*
74+ * Creates the HTTP thread (it changes priority internally).
75+ */
76+ //chThdCreateStatic(wa_http_server, sizeof(wa_http_server), NORMALPRIO + 1,
77+ // http_server, NULL);
78+
79+ /*
80+ * Normal main() thread activity, in this demo it does nothing except
81+ * sleeping in a loop and check the button state.
82+ */
83+ while (TRUE) {
84+ if (palReadPad(GPIOC, GPIOC_SWITCH_TAMPER) == 0)
85+ TestThread(&SD3);
86+ chThdSleepMilliseconds(500);
87+ }
88+}
--- branches/stm32_ethernet_wrapper/demos/ARMCM3-STM32F107-LWIP/mcuconf.h (nonexistent)
+++ branches/stm32_ethernet_wrapper/demos/ARMCM3-STM32F107-LWIP/mcuconf.h (revision 2871)
@@ -0,0 +1,165 @@
1+/*
2+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
3+ 2011 Giovanni Di Sirio.
4+
5+ This file is part of ChibiOS/RT.
6+
7+ ChibiOS/RT is free software; you can redistribute it and/or modify
8+ it under the terms of the GNU General Public License as published by
9+ the Free Software Foundation; either version 3 of the License, or
10+ (at your option) any later version.
11+
12+ ChibiOS/RT is distributed in the hope that it will be useful,
13+ but WITHOUT ANY WARRANTY; without even the implied warranty of
14+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15+ GNU General Public License for more details.
16+
17+ You should have received a copy of the GNU General Public License
18+ along with this program. If not, see <http://www.gnu.org/licenses/>.
19+*/
20+
21+/*
22+ * STM32 drivers configuration.
23+ * The following settings override the default settings present in
24+ * the various device driver implementation headers.
25+ * Note that the settings for each driver only have effect if the whole
26+ * driver is enabled in halconf.h.
27+ *
28+ * IRQ priorities:
29+ * 15...0 Lowest...Highest.
30+ *
31+ * DMA priorities:
32+ * 0...3 Lowest...Highest.
33+ */
34+
35+/*
36+ * HAL driver system settings.
37+ */
38+#define STM32_ACTIVATE_PLL1 TRUE
39+#define STM32_ACTIVATE_PLL2 TRUE
40+#define STM32_ACTIVATE_PLL3 TRUE
41+#define STM32_SW STM32_SW_PLL
42+#define STM32_PLLSRC STM32_PLLSRC_PREDIV1
43+#define STM32_PREDIV1SRC STM32_PREDIV1SRC_PLL2
44+#define STM32_PREDIV1_VALUE 5
45+#define STM32_PLLMUL_VALUE 9
46+#define STM32_PREDIV2_VALUE 5
47+#define STM32_PLL2MUL_VALUE 8
48+#define STM32_PLL3MUL_VALUE 10
49+#define STM32_HPRE STM32_HPRE_DIV1
50+#define STM32_PPRE1 STM32_PPRE1_DIV2
51+#define STM32_PPRE2 STM32_PPRE2_DIV2
52+#define STM32_ADCPRE STM32_ADCPRE_DIV4
53+#define STM32_OTGFSPRE STM32_OTGFSPRE_DIV3
54+#define STM32_MCO STM32_MCO_PLL3
55+
56+/*
57+ * ADC driver system settings.
58+ */
59+#define STM32_ADC_USE_ADC1 TRUE
60+#define STM32_ADC_ADC1_DMA_PRIORITY 3
61+#define STM32_ADC_ADC1_IRQ_PRIORITY 5
62+#define STM32_ADC_ADC1_DMA_ERROR_HOOK() chSysHalt()
63+
64+/*
65+ * CAN driver system settings.
66+ */
67+#define STM32_CAN_USE_CAN1 TRUE
68+#define STM32_CAN_CAN1_IRQ_PRIORITY 11
69+
70+/*
71+ * GPT driver system settings.
72+ */
73+#define STM32_GPT_USE_TIM1 FALSE
74+#define STM32_GPT_USE_TIM2 FALSE
75+#define STM32_GPT_USE_TIM3 FALSE
76+#define STM32_GPT_USE_TIM4 FALSE
77+#define STM32_GPT_USE_TIM5 FALSE
78+#define STM32_GPT_TIM1_IRQ_PRIORITY 7
79+#define STM32_GPT_TIM2_IRQ_PRIORITY 7
80+#define STM32_GPT_TIM3_IRQ_PRIORITY 7
81+#define STM32_GPT_TIM4_IRQ_PRIORITY 7
82+#define STM32_GPT_TIM5_IRQ_PRIORITY 7
83+
84+/*
85+ * ICU driver system settings.
86+ */
87+#define STM32_ICU_USE_TIM1 FALSE
88+#define STM32_ICU_USE_TIM2 FALSE
89+#define STM32_ICU_USE_TIM3 FALSE
90+#define STM32_ICU_USE_TIM4 TRUE
91+#define STM32_ICU_USE_TIM5 FALSE
92+#define STM32_ICU_TIM1_IRQ_PRIORITY 7
93+#define STM32_ICU_TIM2_IRQ_PRIORITY 7
94+#define STM32_ICU_TIM3_IRQ_PRIORITY 7
95+#define STM32_ICU_TIM4_IRQ_PRIORITY 7
96+#define STM32_ICU_TIM5_IRQ_PRIORITY 7
97+
98+/*
99+ * PWM driver system settings.
100+ */
101+#define STM32_PWM_USE_ADVANCED TRUE
102+#define STM32_PWM_USE_TIM1 TRUE
103+#define STM32_PWM_USE_TIM2 FALSE
104+#define STM32_PWM_USE_TIM3 FALSE
105+#define STM32_PWM_USE_TIM4 FALSE
106+#define STM32_PWM_USE_TIM5 FALSE
107+#define STM32_PWM_TIM1_IRQ_PRIORITY 7
108+#define STM32_PWM_TIM2_IRQ_PRIORITY 7
109+#define STM32_PWM_TIM3_IRQ_PRIORITY 7
110+#define STM32_PWM_TIM4_IRQ_PRIORITY 7
111+#define STM32_PWM_TIM5_IRQ_PRIORITY 7
112+
113+/*
114+ * SERIAL driver system settings.
115+ */
116+#define STM32_SERIAL_USE_USART1 FALSE
117+#define STM32_SERIAL_USE_USART2 FALSE
118+#define STM32_SERIAL_USE_USART3 TRUE
119+#define STM32_SERIAL_USE_UART4 FALSE
120+#define STM32_SERIAL_USE_UART5 FALSE
121+#define STM32_SERIAL_USART1_PRIORITY 12
122+#define STM32_SERIAL_USART2_PRIORITY 12
123+#define STM32_SERIAL_USART3_PRIORITY 12
124+#define STM32_SERIAL_UART4_PRIORITY 12
125+#define STM32_SERIAL_UART5_PRIORITY 12
126+
127+/*
128+ * SPI driver system settings.
129+ */
130+#define STM32_SPI_USE_SPI1 FALSE
131+#define STM32_SPI_USE_SPI2 FALSE
132+#define STM32_SPI_USE_SPI3 TRUE
133+#define STM32_SPI_SPI1_DMA_PRIORITY 2
134+#define STM32_SPI_SPI2_DMA_PRIORITY 2
135+#define STM32_SPI_SPI3_DMA_PRIORITY 2
136+#define STM32_SPI_SPI1_IRQ_PRIORITY 10
137+#define STM32_SPI_SPI2_IRQ_PRIORITY 10
138+#define STM32_SPI_SPI3_IRQ_PRIORITY 10
139+#define STM32_SPI_SPI1_DMA_ERROR_HOOK() chSysHalt()
140+#define STM32_SPI_SPI2_DMA_ERROR_HOOK() chSysHalt()
141+#define STM32_SPI_SPI3_DMA_ERROR_HOOK() chSysHalt()
142+
143+/*
144+ * UART driver system settings.
145+ */
146+#define STM32_UART_USE_USART1 FALSE
147+#define STM32_UART_USE_USART2 TRUE
148+#define STM32_UART_USE_USART3 FALSE
149+#define STM32_UART_USART1_IRQ_PRIORITY 12
150+#define STM32_UART_USART2_IRQ_PRIORITY 12
151+#define STM32_UART_USART3_IRQ_PRIORITY 12
152+#define STM32_UART_USART1_DMA_PRIORITY 0
153+#define STM32_UART_USART2_DMA_PRIORITY 0
154+#define STM32_UART_USART3_DMA_PRIORITY 0
155+#define STM32_UART_USART1_DMA_ERROR_HOOK() chSysHalt()
156+#define STM32_UART_USART2_DMA_ERROR_HOOK() chSysHalt()
157+#define STM32_UART_USART3_DMA_ERROR_HOOK() chSysHalt()
158+
159+/*
160+ * USB driver system settings.
161+ */
162+#define STM32_USB_USE_USB1 TRUE
163+#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE
164+#define STM32_USB_USB1_HP_IRQ_PRIORITY 6
165+#define STM32_USB_USB1_LP_IRQ_PRIORITY 14
--- branches/stm32_ethernet_wrapper/demos/ARMCM3-STM32F107-LWIP/readme.txt (nonexistent)
+++ branches/stm32_ethernet_wrapper/demos/ARMCM3-STM32F107-LWIP/readme.txt (revision 2871)
@@ -0,0 +1,36 @@
1+*****************************************************************************
2+** ChibiOS/RT port for ARM-Cortex-M3 STM32F107. **
3+*****************************************************************************
4+
5+** TARGET **
6+
7+The demo runs on an Olimex STM32-P107 board.
8+
9+** The Demo **
10+
11+The demo flashes the board LED using a thread, by pressing the button located
12+on the board the test procedure is activated with output on the serial port
13+SD3 (USART3).
14+The demo also starts the ethernet driver using the IP address configured in
15+lwipthread.h.
16+
17+** Build Procedure **
18+
19+The demo has been tested by using the free Codesourcery GCC-based toolchain.
20+Just modify the TRGT line in the makefile in order to use different GCC ports.
21+The demo requires the lwip 1.4.0.rc1 stack, which is included in ./ext and
22+should be extracted to ./ext/lwip
23+Additionally, the demo requires the ST firmware library, which is included in
24+./ext
25+
26+** Notes **
27+
28+Some files used by the demo are not part of ChibiOS/RT but are copyright of
29+ST Microelectronics and are licensed under a different license.
30+Also note that not all the files present in the ST library are distribited
31+with ChibiOS/RT, you can find the whole library on the ST web site:
32+
33+ http://www.st.com
34+
35+The lwIP stack also has its own license, please read the info into the included
36+lwIP distribution files.
--- branches/stm32_ethernet_wrapper/demos/ARMCM3-STM32F107-LWIP/stm32f10x_conf.h (nonexistent)
+++ branches/stm32_ethernet_wrapper/demos/ARMCM3-STM32F107-LWIP/stm32f10x_conf.h (revision 2871)
@@ -0,0 +1,80 @@
1+/**
2+ ******************************************************************************
3+ * @file CAN/LoopBack/stm32f10x_conf.h
4+ * @author MCD Application Team
5+ * @version V3.3.0
6+ * @date 04/16/2010
7+ * @brief Library configuration file.
8+ ******************************************************************************
9+ * @copy
10+ *
11+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
12+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
13+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
14+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
15+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
16+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
17+ *
18+ * <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>
19+ */
20+
21+/* Define to prevent recursive inclusion -------------------------------------*/
22+#ifndef __STM32F10x_CONF_H
23+#define __STM32F10x_CONF_H
24+
25+//#include "ch.h"
26+//#include "hal.h"
27+
28+/* Includes ------------------------------------------------------------------*/
29+/* Uncomment the line below to enable peripheral header file inclusion */
30+/* #include "stm32f10x_adc.h" */
31+/* #include "stm32f10x_bkp.h" */
32+/* #include "stm32f10x_can.h" */
33+/* #include "stm32f10x_cec.h" */
34+/* #include "stm32f10x_crc.h" */
35+/* #include "stm32f10x_dac.h" */
36+/* #include "stm32f10x_dbgmcu.h" */
37+/* #include "stm32f10x_dma.h" */
38+/* #include "stm32f10x_exti.h" */
39+/* #include "stm32f10x_flash.h" */
40+/* #include "stm32f10x_fsmc.h" */
41+/* #include "stm32f10x_gpio.h" */
42+/* #include "stm32f10x_i2c.h" */
43+/* #include "stm32f10x_iwdg.h" */
44+/* #include "stm32f10x_pwr.h" */
45+/* #include "stm32f10x_rcc.h" */
46+/* #include "stm32f10x_rtc.h" */
47+/* #include "stm32f10x_sdio.h" */
48+/* #include "stm32f10x_spi.h" */
49+/* #include "stm32f10x_tim.h" */
50+/* #include "stm32f10x_usart.h" */
51+/* #include "stm32f10x_wwdg.h" */
52+/* #include "misc.h" */ /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
53+
54+/* Exported types ------------------------------------------------------------*/
55+/* Exported constants --------------------------------------------------------*/
56+/* Uncomment the line below to expanse the "assert_param" macro in the
57+ Standard Peripheral Library drivers code */
58+/* #define USE_FULL_ASSERT 1 */
59+
60+/* Exported macro ------------------------------------------------------------*/
61+#ifdef USE_FULL_ASSERT
62+
63+/**
64+ * @brief The assert_param macro is used for function's parameters check.
65+ * @param expr: If expr is false, it calls assert_failed function
66+ * which reports the name of the source file and the source
67+ * line number of the call that failed.
68+ * If expr is true, it returns no value.
69+ * @retval None
70+ */
71+ #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
72+/* Exported functions ------------------------------------------------------- */
73+ void assert_failed(uint8_t* file, uint32_t line);
74+#else
75+ #define assert_param(expr) ((void)0)
76+#endif /* USE_FULL_ASSERT */
77+
78+#endif /* __STM32F10x_CONF_H */
79+
80+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
--- branches/stm32_ethernet_wrapper/os/hal/platforms/STM32/mac_lld.c (nonexistent)
+++ branches/stm32_ethernet_wrapper/os/hal/platforms/STM32/mac_lld.c (revision 2871)
@@ -0,0 +1,471 @@
1+/*
2+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.
3+
4+ This file is part of ChibiOS/RT.
5+
6+ ChibiOS/RT is free software; you can redistribute it and/or modify
7+ it under the terms of the GNU General Public License as published by
8+ the Free Software Foundation; either version 3 of the License, or
9+ (at your option) any later version.
10+
11+ ChibiOS/RT is distributed in the hope that it will be useful,
12+ but WITHOUT ANY WARRANTY; without even the implied warranty of
13+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14+ GNU General Public License for more details.
15+
16+ You should have received a copy of the GNU General Public License
17+ along with this program. If not, see <http://www.gnu.org/licenses/>.
18+
19+ ---
20+
21+ A special exception to the GPL can be applied should you wish to distribute
22+ a combined work that includes ChibiOS/RT, without being obliged to provide
23+ the source code for any proprietary components. See the file exception.txt
24+ for full details of how and when the exception can be applied.
25+*/
26+
27+/**
28+ * @file STM32/mac_lld.c
29+ * @brief STM32 low level MAC driver code.
30+ * @addtogroup STM32_MAC
31+ * @{
32+ */
33+
34+#include <string.h>
35+
36+#include "ch.h"
37+#include "hal.h"
38+#include "stm32_eth.h"
39+
40+#if HAL_USE_MAC || defined(__DOXYGEN__)
41+
42+/*===========================================================================*/
43+/* Driver exported variables. */
44+/*===========================================================================*/
45+
46+/**
47+ * @brief Ethernet driver 1.
48+ */
49+MACDriver ETH1;
50+
51+/*===========================================================================*/
52+/* Driver local variables. */
53+/*===========================================================================*/
54+
55+#ifndef __DOXYGEN__
56+static bool_t link_up;
57+
58+static uint8_t default_mac[] = {0xAA, 0x55, 0x13, 0x37, 0x01, 0x10};
59+
60+#define MAC_RX_DESCRIPTORS 4
61+#define MAC_TX_DESCRIPTORS 2
62+#define MAC_RECEIVE_BUFFERS_SIZE (MAC_BUFFERS_SIZE)
63+#define MAC_TRANSMIT_BUFFERS_SIZE (MAC_BUFFERS_SIZE)
64+
65+/* Descriptors */
66+static ETH_DMADESCTypeDef rd[MAC_RX_DESCRIPTORS] __attribute__((aligned(4)));
67+static ETH_DMADESCTypeDef td[MAC_TX_DESCRIPTORS] __attribute__((aligned(4)));
68+
69+/* Buffers */
70+static uint8_t rb[MAC_RX_DESCRIPTORS * MAC_RECEIVE_BUFFERS_SIZE] __attribute__((aligned(4)));
71+static uint8_t tb[MAC_TX_DESCRIPTORS * MAC_TRANSMIT_BUFFERS_SIZE] __attribute__((aligned(4)));
72+
73+/* Defined in ST ETH library: */
74+extern ETH_DMADESCTypeDef *DMATxDescToSet;
75+extern ETH_DMADESCTypeDef *DMARxDescToGet;
76+
77+#endif
78+
79+/*===========================================================================*/
80+/* Driver local functions. */
81+/*===========================================================================*/
82+static void configure_eth_struct(void) {
83+ static ETH_InitTypeDef ethinit;
84+
85+ /* Call this to avoid having to configure all members */
86+ ETH_StructInit(&ethinit);
87+
88+ /* MAC */
89+ ethinit.ETH_AutoNegotiation = ETH_AutoNegotiation_Enable;
90+ ethinit.ETH_LoopbackMode = ETH_LoopbackMode_Disable;
91+ ethinit.ETH_RetryTransmission = ETH_RetryTransmission_Disable;
92+ ethinit.ETH_AutomaticPadCRCStrip = ETH_AutomaticPadCRCStrip_Disable;
93+ ethinit.ETH_ReceiveAll = ETH_ReceiveAll_Disable;
94+ ethinit.ETH_BroadcastFramesReception = ETH_BroadcastFramesReception_Enable;
95+ ethinit.ETH_PromiscuousMode = ETH_PromiscuousMode_Disable;
96+ ethinit.ETH_MulticastFramesFilter = ETH_MulticastFramesFilter_Perfect;
97+ ethinit.ETH_UnicastFramesFilter = ETH_UnicastFramesFilter_Perfect;
98+ ethinit.ETH_ChecksumOffload = ETH_ChecksumOffload_Enable;
99+
100+ /* DMA */
101+ /* Use store & forward mode because checksum offloading is enabled */
102+ ethinit.ETH_DropTCPIPChecksumErrorFrame = ETH_DropTCPIPChecksumErrorFrame_Enable;
103+ ethinit.ETH_ReceiveStoreForward = ETH_ReceiveStoreForward_Enable;
104+ ethinit.ETH_TransmitStoreForward = ETH_TransmitStoreForward_Enable;
105+
106+ ethinit.ETH_ForwardErrorFrames = ETH_ForwardErrorFrames_Disable;
107+ ethinit.ETH_ForwardUndersizedGoodFrames = ETH_ForwardUndersizedGoodFrames_Disable;
108+ ethinit.ETH_SecondFrameOperate = ETH_SecondFrameOperate_Enable;
109+ ethinit.ETH_AddressAlignedBeats = ETH_AddressAlignedBeats_Enable;
110+ ethinit.ETH_FixedBurst = ETH_FixedBurst_Enable;
111+ ethinit.ETH_RxDMABurstLength = ETH_RxDMABurstLength_32Beat;
112+ ethinit.ETH_TxDMABurstLength = ETH_TxDMABurstLength_32Beat;
113+ ethinit.ETH_DMAArbitration = ETH_DMAArbitration_RoundRobin_RxTx_2_1;
114+
115+ /* Discover PHY Address */
116+ uint16_t phyaddr;
117+ for (phyaddr = 0; phyaddr < 32; phyaddr++) {
118+ if ((ETH_ReadPHYRegister(phyaddr, 0x02) == 0x0006) &&
119+ ((ETH_ReadPHYRegister(phyaddr, 0x03) & 0xFFF0) == 0x1c50))
120+ {
121+ break;
122+ }
123+ }
124+
125+ /* Configure Ethernet Peripheral */
126+ if (phyaddr < 32) {
127+ link_up = ETH_Init(&ethinit, phyaddr);
128+ }
129+ else {
130+ link_up = 0;
131+ chSysHalt();
132+ }
133+}
134+
135+/*===========================================================================*/
136+/* Driver interrupt handlers. */
137+/*===========================================================================*/
138+
139+/**
140+ * @brief Ethernet Global Interrupt IRQ handler.
141+ */
142+CH_IRQ_HANDLER(Vector134) {
143+ uint32_t dmasr;
144+
145+ CH_IRQ_PROLOGUE();
146+
147+ dmasr = ETH->DMASR;
148+ ETH->DMASR = dmasr; /* Clear status bits */
149+
150+ if (dmasr & ETH_DMA_IT_R) {
151+ /* Data Received */
152+ chSysLockFromIsr();
153+ chSemResetI(&ETH1.rdsem, 0);
154+#if CH_USE_EVENTS
155+ chEvtBroadcastI(&ETH1.rdevent);
156+#endif
157+ chSysUnlockFromIsr();
158+ }
159+
160+ if (dmasr & ETH_DMA_IT_T) {
161+ /* Data Transmitted */
162+ chSysLockFromIsr();
163+ chSemResetI(&ETH1.tdsem, 0);
164+ chSysUnlockFromIsr();
165+ }
166+
167+ CH_IRQ_EPILOGUE();
168+}
169+
170+/*===========================================================================*/
171+/* Driver exported functions. */
172+/*===========================================================================*/
173+
174+/**
175+ * @brief Low level MAC initialization.
176+ */
177+void mac_lld_init(void) {
178+
179+ macObjectInit(&ETH1);
180+
181+ /* Use MII Mode */
182+// AFIO->MAPR &= ~(AFIO_MAPR_MII_RMII_SEL);
183+ //Use RMII Mode
184+ AFIO->MAPR |= (AFIO_MAPR_MII_RMII_SEL);
185+
186+ /* Enable Ethernet Peripheral Clock */
187+ RCC->AHBENR |= RCC_AHBENR_ETHMACEN | RCC_AHBENR_ETHMACTXEN | RCC_AHBENR_ETHMACRXEN;
188+
189+ /* Reset Ethernet on AHB Bus */
190+ ETH_DeInit();
191+
192+ ETH_SoftwareReset();
193+ while(ETH_GetSoftwareResetStatus() == SET);
194+
195+ /* Set MAC Address */
196+ mac_lld_set_address(&ETH1, default_mac);
197+
198+ /* Fills ethernet config struct and calls ETH_Init() */
199+ configure_eth_struct();
200+
201+ /* Initialize Tx & Rx Descriptors list: Chain mode */
202+ ETH_DMATxDescChainInit(td, tb, MAC_TX_DESCRIPTORS);
203+ ETH_DMARxDescChainInit(rd, rb, MAC_RX_DESCRIPTORS);
204+
205+ /* Enable Ethernet Rx Interrupt */
206+ ETH_DMAITConfig(ETH_DMA_IT_NIS | ETH_DMA_IT_R, ENABLE);
207+ int i;
208+ for (i = 0; i < MAC_RX_DESCRIPTORS; i++) {
209+ ETH_DMARxDescReceiveITConfig(&rd[i], ENABLE);
210+ }
211+
212+ /* Enable checksum insertion for Tx frames */
213+ for (i = 0; i < MAC_TX_DESCRIPTORS; i++) {
214+ ETH_DMATxDescChecksumInsertionConfig(&td[i], ETH_DMATxDesc_ChecksumTCPUDPICMPFull);
215+ }
216+
217+ /* Enable MAC and DMA transmission and reception */
218+ ETH_Start();
219+
220+ /* Enable the Ethernet global interrupt */
221+ NVICEnableVector(ETH_IRQn,
222+ CORTEX_PRIORITY_MASK(STM32_ETH1_IRQ_PRIORITY));
223+}
224+
225+/**
226+ * @brief Low level MAC address setup.
227+ *
228+ * @param[in] macp pointer to the @p MACDriver object
229+ * @param[in] p pointer to a six bytes buffer containing the MAC address. If
230+ * this parameter is set to @p NULL then a system default MAC is
231+ * used. The MAC address must be aligned with the most significant
232+ * byte first.
233+ */
234+void mac_lld_set_address(MACDriver *macp, const uint8_t *p) {
235+
236+ (void)macp;
237+ ETH_MACAddressConfig(ETH_MAC_Address0, (uint8_t*)p);
238+}
239+
240+/**
241+ * @brief Returns a transmission descriptor.
242+ * @details One of the available transmission descriptors is locked and
243+ * returned.
244+ *
245+ * @param[in] macp pointer to the @p MACDriver object
246+ * @param[out] tdp pointer to a @p MACTransmitDescriptor structure
247+ * @return The operation status.
248+ * @retval RDY_OK the descriptor was obtained.
249+ * @retval RDY_TIMEOUT descriptor not available.
250+ */
251+msg_t max_lld_get_transmit_descriptor(MACDriver *macp,
252+ MACTransmitDescriptor *tdp) {
253+ MACDescriptor *mdp;
254+ (void)macp;
255+
256+ if (!link_up)
257+ return RDY_TIMEOUT;
258+
259+ chSysLock();
260+
261+ /* Get Current Tx buffer */
262+ mdp = DMATxDescToSet;
263+
264+ /* Ensure that descriptor isn't owned by the Ethernet DMA */
265+ if ((mdp->Status & ETH_DMATxDesc_OWN) != (uint32_t)RESET) {
266+ chSysUnlock();
267+ return RDY_TIMEOUT;
268+ }
269+
270+ //TODO: Buffer should be marked as "locked"
271+
272+ /* Configure next Tx buffer (Chained mode) */
273+ DMATxDescToSet = (ETH_DMADESCTypeDef*)(DMATxDescToSet->Buffer2NextDescAddr);
274+
275+ chSysUnlock();
276+
277+ /* Set the buffer size and configuration */
278+ tdp->offset = 0;
279+ tdp->size = MAC_TRANSMIT_BUFFERS_SIZE;
280+ tdp->physdesc = mdp;
281+ return RDY_OK;
282+}
283+
284+/**
285+ * @brief Writes to a transmit descriptor's stream.
286+ *
287+ * @param[in] tdp pointer to a @p MACTransmitDescriptor structure
288+ * @param[in] buf pointer to the buffer containing the data to be written
289+ * @param[in] size number of bytes to be written
290+ * @return The number of bytes written into the descriptor's stream, this
291+ * value can be less than the amount specified in the parameter
292+ * @p size if the maximum frame size is reached.
293+ */
294+size_t mac_lld_write_transmit_descriptor(MACTransmitDescriptor *tdp,
295+ uint8_t *buf,
296+ size_t size) {
297+
298+ chDbgAssert(!(tdp->physdesc->Status & ETH_DMARxDesc_OWN),
299+ "mac_lld_release_receive_descriptor(), #1",
300+ "attempt to write descriptor already owned by DMA");
301+
302+ if (size > tdp->size - tdp->offset)
303+ size = tdp->size - tdp->offset;
304+ if (size > 0) {
305+ memcpy((uint8_t *)(tdp->physdesc->Buffer1Addr) +
306+ tdp->offset,
307+ buf, size);
308+ tdp->offset += size;
309+ }
310+ return size;
311+}
312+
313+/**
314+ * @brief Releases a transmit descriptor and starts the transmission of the
315+ * enqueued data as a single frame.
316+ *
317+ * @param[in] tdp the pointer to the @p MACTransmitDescriptor structure
318+ */
319+void mac_lld_release_transmit_descriptor(MACTransmitDescriptor *tdp) {
320+ chDbgAssert(!(tdp->physdesc->Status & ETH_DMARxDesc_OWN),
321+ "mac_lld_release_receive_descriptor(), #1",
322+ "attempt to release descriptor already owned by DMA");
323+
324+ chSysLock();
325+
326+ /* Set frame length: bits[12:0] */
327+ tdp->physdesc->ControlBufferSize = (tdp->offset & ETH_DMATxDesc_TBS1);
328+
329+ /* Set the last segment and first segment bits (frame xmit in one descriptor) */
330+ tdp->physdesc->Status |= ETH_DMATxDesc_LS | ETH_DMATxDesc_FS;
331+
332+ /* Enable interrupt on completion */
333+ tdp->physdesc->Status |= ETH_DMATxDesc_IC;
334+
335+ /* Give buffer back to the DMA */
336+ tdp->physdesc->Status |= ETH_DMATxDesc_OWN;
337+
338+ /* Clear unavailable flag & resume transmission */
339+ //TODO: the following check for DMASR_TBUS doesn't work
340+//if ((ETH->DMASR & ETH_DMASR_TBUS) != (uint32_t)RESET) {
341+ ETH->DMASR = ETH_DMASR_TBUS;
342+ ETH->DMATPDR = 0;
343+//}
344+ chSysUnlock();
345+}
346+
347+/**
348+ * @brief Returns a receive descriptor.
349+ *
350+ * @param[in] macp pointer to the @p MACDriver object
351+ * @param[out] rdp pointer to a @p MACReceiveDescriptor structure
352+ * @return The operation status.
353+ * @retval RDY_OK the descriptor was obtained.
354+ * @retval RDY_TIMEOUT descriptor not available.
355+ */
356+msg_t max_lld_get_receive_descriptor(MACDriver *macp,
357+ MACReceiveDescriptor *rdp) {
358+ MACDescriptor *mdp;
359+ (void)macp;
360+
361+ chSysLock();
362+
363+ /* Get current Rx Buffer */
364+ mdp = DMARxDescToGet;
365+
366+ /* Check if owned by the Ethernet DMA */
367+ if ((mdp->Status & ETH_DMARxDesc_OWN) != (uint32_t)RESET) {
368+ //TODO: The following check for DMASR_RBUS doesn't seem to work
369+// if ((ETH->DMASR & ETH_DMASR_RBUS) != (uint32_t)RESET) {
370+ /* Clear RBUS Ethernet DMA Flag */
371+ ETH->DMASR = ETH_DMASR_RBUS;
372+ /* Resume DMA Operation */
373+ ETH->DMARPDR = 0;
374+// }
375+ /* Return error (owned by DMA) */
376+ chSysUnlock();
377+ return RDY_TIMEOUT;
378+ }
379+
380+ if (((mdp->Status & ETH_DMARxDesc_ES) == (uint32_t)RESET) &&
381+ ((mdp->Status & ETH_DMARxDesc_LS) != (uint32_t)RESET) &&
382+ ((mdp->Status & ETH_DMARxDesc_FS) != (uint32_t)RESET))
383+ {
384+ rdp->offset = 0;
385+
386+ /* Frame Length of received packet - 4 bytes of CRC */
387+ rdp->size = ((mdp->Status & ETH_DMARxDesc_FL) >> 16) - 4;
388+
389+ rdp->physdesc = mdp;
390+
391+ /* Configure next Rx buffer (Chain mode) */
392+ DMARxDescToGet = (ETH_DMADESCTypeDef*)(DMARxDescToGet->Buffer2NextDescAddr);
393+
394+ chSysUnlock();
395+ return RDY_OK;
396+ }
397+
398+ chSysUnlock();
399+ return RDY_TIMEOUT;
400+}
401+
402+/**
403+ * @brief Reads from a receive descriptor's stream.
404+ *
405+ * @param[in] rdp pointer to a @p MACReceiveDescriptor structure
406+ * @param[in] buf pointer to the buffer that will receive the read data
407+ * @param[in] size number of bytes to be read
408+ * @return The number of bytes read from the descriptor's stream, this
409+ * value can be less than the amount specified in the parameter
410+ * @p size if there are no more bytes to read.
411+ */
412+size_t mac_lld_read_receive_descriptor(MACReceiveDescriptor *rdp,
413+ uint8_t *buf,
414+ size_t size) {
415+ if (size > rdp->size - rdp->offset)
416+ size = rdp->size - rdp->offset;
417+
418+ if (size > 0) {
419+ uint8_t *src = (uint8_t *)(rdp->physdesc->Buffer1Addr) +
420+ rdp->offset;
421+ memcpy(buf, src, size);
422+ rdp->offset += size;
423+ }
424+
425+ return size;
426+}
427+
428+/**
429+ * @brief Releases a receive descriptor.
430+ * @details The descriptor and its buffer are made available for more incoming
431+ * frames.
432+ *
433+ * @param[in] rdp the pointer to the @p MACReceiveDescriptor structure
434+ */
435+void mac_lld_release_receive_descriptor(MACReceiveDescriptor *rdp) {
436+ MACDescriptor *mdp;
437+
438+ mdp = rdp->physdesc;
439+ chDbgAssert(!(mdp->Status & ETH_DMARxDesc_OWN),
440+ "mac_lld_release_receive_descriptor(), #1",
441+ "attempt to release descriptor already owned by DMA");
442+
443+ /* Give buffer back to the Ethernet DMA */
444+ mdp->Status = ETH_DMARxDesc_OWN;
445+
446+ //TODO: Is this even necessary? DMA should resume when next frame is
447+ // received automatically.
448+ if ((ETH->DMASR & ETH_DMASR_RBUS) != (uint32_t)RESET) {
449+ ETH->DMASR = ETH_DMASR_RBUS;
450+ ETH->DMARPDR = 0;
451+ }
452+}
453+
454+/**
455+ * @brief Updates and returns the link status.
456+ *
457+ * @param[in] macp pointer to the @p MACDriver object
458+ * @return The link status.
459+ * @retval TRUE if the link is active.
460+ * @retval FALSE if the link is down.
461+ */
462+bool_t mac_lld_poll_link_status(MACDriver *macp) {
463+ (void)macp;
464+ //TODO: If link down, then attempt to bring link back up
465+ //NOTE: The ST libs attempt to bring link up within ETH_Init()
466+ return link_up;
467+}
468+
469+#endif /* CH_HAL_USE_MAC */
470+
471+/** @} */
--- branches/stm32_ethernet_wrapper/os/hal/platforms/STM32/mac_lld.h (nonexistent)
+++ branches/stm32_ethernet_wrapper/os/hal/platforms/STM32/mac_lld.h (revision 2871)
@@ -0,0 +1,166 @@
1+/*
2+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.
3+
4+ This file is part of ChibiOS/RT.
5+
6+ ChibiOS/RT is free software; you can redistribute it and/or modify
7+ it under the terms of the GNU General Public License as published by
8+ the Free Software Foundation; either version 3 of the License, or
9+ (at your option) any later version.
10+
11+ ChibiOS/RT is distributed in the hope that it will be useful,
12+ but WITHOUT ANY WARRANTY; without even the implied warranty of
13+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14+ GNU General Public License for more details.
15+
16+ You should have received a copy of the GNU General Public License
17+ along with this program. If not, see <http://www.gnu.org/licenses/>.
18+
19+ ---
20+
21+ A special exception to the GPL can be applied should you wish to distribute
22+ a combined work that includes ChibiOS/RT, without being obliged to provide
23+ the source code for any proprietary components. See the file exception.txt
24+ for full details of how and when the exception can be applied.
25+*/
26+
27+/**
28+ * @file STM32/mac_lld.h
29+ * @brief STM32 low level MAC driver header.
30+ * @addtogroup STM32_MAC
31+ * @{
32+ */
33+
34+#ifndef _MAC_LLD_H_
35+#define _MAC_LLD_H_
36+
37+#if HAL_USE_MAC || defined(__DOXYGEN__)
38+
39+/*
40+ * Note: Currently this MAC driver is dependent on the STM32 Ethernet code
41+ * library.
42+ */
43+#include "stm32_eth.h"
44+
45+/*===========================================================================*/
46+/* Driver constants. */
47+/*===========================================================================*/
48+
49+/*===========================================================================*/
50+/* Driver pre-compile time settings. */
51+/*===========================================================================*/
52+
53+/**
54+ * @brief Number of available transmit buffers.
55+ */
56+#if !defined(MAC_TRANSMIT_BUFFERS) || defined(__DOXYGEN__)
57+#define MAC_TRANSMIT_BUFFERS 2
58+#endif
59+
60+/**
61+ * @brief Number of available receive buffers.
62+ */
63+#if !defined(MAC_RECEIVE_BUFFERS) || defined(__DOXYGEN__)
64+#define MAC_RECEIVE_BUFFERS 4
65+#endif
66+
67+/**
68+ * @brief Maximum supported frame size.
69+ */
70+#if !defined(MAC_BUFFERS_SIZE) || defined(__DOXYGEN__)
71+#define MAC_BUFFERS_SIZE 1520
72+#endif
73+
74+/**
75+ * @brief ETH1 interrupt priority level setting.
76+ */
77+#if !defined(STM32_ETH1_IRQ_PRIORITY) || defined(__DOXYGEN__)
78+#define STM32_ETH1_IRQ_PRIORITY 13
79+#endif
80+
81+/*===========================================================================*/
82+/* Derived constants and error checks. */
83+/*===========================================================================*/
84+
85+/*===========================================================================*/
86+/* Driver data structures and types. */
87+/*===========================================================================*/
88+
89+/**
90+ * @brief Structure representing a Frame.
91+ */
92+typedef ETH_DMADESCTypeDef MACDescriptor;
93+
94+/**
95+ * @brief Structure representing a MAC driver.
96+ */
97+typedef struct {
98+ Semaphore tdsem; /**< Transmit semaphore. */
99+ Semaphore rdsem; /**< Receive semaphore. */
100+#if CH_USE_EVENTS
101+ EventSource rdevent; /**< Receive event source. */
102+#endif
103+ /* End of the mandatory fields.*/
104+} MACDriver;
105+
106+/**
107+ * @brief Structure representing a transmit descriptor.
108+ */
109+typedef struct {
110+ size_t offset; /**< Current write offset. */
111+ size_t size; /**< Available space size. */
112+ /* End of the mandatory fields.*/
113+ MACDescriptor *physdesc; /**< Pointer to the physical
114+ descriptor. */
115+} MACTransmitDescriptor;
116+
117+/**
118+ * @brief Structure representing a receive descriptor.
119+ */
120+typedef struct {
121+ size_t offset; /**< Current read offset. */
122+ size_t size; /**< Available data size. */
123+ /* End of the mandatory fields.*/
124+ MACDescriptor *physdesc; /**< Pointer to the first descriptor
125+ of the buffers chain. */
126+} MACReceiveDescriptor;
127+
128+/*===========================================================================*/
129+/* Driver macros. */
130+/*===========================================================================*/
131+
132+/*===========================================================================*/
133+/* External declarations. */
134+/*===========================================================================*/
135+
136+#if !defined(__DOXYGEN__)
137+extern MACDriver ETH1;
138+#endif
139+
140+#ifdef __cplusplus
141+extern "C" {
142+#endif
143+ void mac_lld_init(void);
144+ void mac_lld_set_address(MACDriver *macp, const uint8_t *p);
145+ msg_t max_lld_get_transmit_descriptor(MACDriver *macp,
146+ MACTransmitDescriptor *tdp);
147+ size_t mac_lld_write_transmit_descriptor(MACTransmitDescriptor *tdp,
148+ uint8_t *buf,
149+ size_t size);
150+ void mac_lld_release_transmit_descriptor(MACTransmitDescriptor *tdp);
151+ msg_t max_lld_get_receive_descriptor(MACDriver *macp,
152+ MACReceiveDescriptor *rdp);
153+ size_t mac_lld_read_receive_descriptor(MACReceiveDescriptor *rdp,
154+ uint8_t *buf,
155+ size_t size);
156+ void mac_lld_release_receive_descriptor(MACReceiveDescriptor *rdp);
157+ bool_t mac_lld_poll_link_status(MACDriver *macp);
158+#ifdef __cplusplus
159+}
160+#endif
161+
162+#endif /* CH_HAL_USE_MAC */
163+
164+#endif /* _MAC_LLD_H_ */
165+
166+/** @} */
--- branches/stm32_ethernet_wrapper/os/hal/platforms/STM32/stm32_eth.c (nonexistent)
+++ branches/stm32_ethernet_wrapper/os/hal/platforms/STM32/stm32_eth.c (revision 2871)
@@ -0,0 +1,3066 @@
1+/**
2+ ******************************************************************************
3+ * @file stm32_eth.c
4+ * @author MCD Application Team
5+ * @version V1.1.0
6+ * @date 11/20/2009
7+ * @brief This file provides all the ETH firmware functions.
8+ ******************************************************************************
9+ * @copy
10+ *
11+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
12+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
13+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
14+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
15+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
16+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
17+ *
18+ * <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2>
19+ */
20+
21+/* Includes ------------------------------------------------------------------*/
22+#include "stm32_eth.h"
23+#include "stm32f10x_rcc.h"
24+
25+/** @addtogroup STM32_ETH_Driver
26+ * @brief ETH driver modules
27+ * @{
28+ */
29+
30+/** @defgroup ETH_Private_TypesDefinitions
31+ * @{
32+ */
33+/**
34+ * @}
35+ */
36+
37+
38+/** @defgroup ETH_Private_Defines
39+ * @{
40+ */
41+/* Global pointers on Tx and Rx descriptor used to track transmit and receive descriptors */
42+ETH_DMADESCTypeDef *DMATxDescToSet;
43+ETH_DMADESCTypeDef *DMARxDescToGet;
44+ETH_DMADESCTypeDef *DMAPTPTxDescToSet;
45+ETH_DMADESCTypeDef *DMAPTPRxDescToGet;
46+
47+/* ETHERNET MAC address offsets */
48+#define ETH_MAC_ADDR_HBASE (ETH_MAC_BASE + 0x40) /* ETHERNET MAC address high offset */
49+#define ETH_MAC_ADDR_LBASE (ETH_MAC_BASE + 0x44) /* ETHERNET MAC address low offset */
50+
51+/* ETHERNET MACMIIAR register Mask */
52+#define MACMIIAR_CR_MASK ((uint32_t)0xFFFFFFE3)
53+
54+/* ETHERNET MACCR register Mask */
55+#define MACCR_CLEAR_MASK ((uint32_t)0xFF20810F)
56+
57+/* ETHERNET MACFCR register Mask */
58+#define MACFCR_CLEAR_MASK ((uint32_t)0x0000FF41)
59+
60+/* ETHERNET DMAOMR register Mask */
61+#define DMAOMR_CLEAR_MASK ((uint32_t)0xF8DE3F23)
62+
63+/* ETHERNET Remote Wake-up frame register length */
64+#define ETH_WAKEUP_REGISTER_LENGTH 8
65+
66+/* ETHERNET Missed frames counter Shift */
67+#define ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT 17
68+
69+/* ETHERNET DMA Tx descriptors Collision Count Shift */
70+#define ETH_DMATXDESC_COLLISION_COUNTSHIFT 3
71+
72+/* ETHERNET DMA Tx descriptors Buffer2 Size Shift */
73+#define ETH_DMATXDESC_BUFFER2_SIZESHIFT 16
74+
75+/* ETHERNET DMA Rx descriptors Frame Length Shift */
76+#define ETH_DMARXDESC_FRAME_LENGTHSHIFT 16
77+
78+/* ETHERNET DMA Rx descriptors Buffer2 Size Shift */
79+#define ETH_DMARXDESC_BUFFER2_SIZESHIFT 16
80+
81+/* ETHERNET errors */
82+#define ETH_ERROR ((uint32_t)0)
83+#define ETH_SUCCESS ((uint32_t)1)
84+/**
85+ * @}
86+ */
87+
88+/** @defgroup ETH_Private_Macros
89+ * @{
90+ */
91+/**
92+ * @}
93+ */
94+
95+/** @defgroup ETH_Private_Variables
96+ * @{
97+ */
98+/**
99+ * @}
100+ */
101+
102+/** @defgroup ETH_Private_FunctionPrototypes
103+ * @{
104+ */
105+
106+#ifndef USE_Delay
107+static void ETH_Delay(__IO uint32_t nCount);
108+#endif /* USE_Delay*/
109+
110+/**
111+ * @}
112+ */
113+
114+/** @defgroup ETH_Private_Functions
115+ * @{
116+ */
117+
118+/**
119+ * @brief Deinitializes the ETHERNET peripheral registers to their default reset values.
120+ * @param None
121+ * @retval None
122+ */
123+void ETH_DeInit(void)
124+{
125+ RCC_AHBPeriphResetCmd(RCC_AHBPeriph_ETH_MAC, ENABLE);
126+ RCC_AHBPeriphResetCmd(RCC_AHBPeriph_ETH_MAC, DISABLE);
127+}
128+
129+/**
130+ * @brief Initializes the ETHERNET peripheral according to the specified
131+ * parameters in the ETH_InitStruct .
132+ * @param ETH_InitStruct: pointer to a ETH_InitTypeDef structure that contains
133+ * the configuration information for the specified ETHERNET peripheral.
134+ * @param PHYAddress: external PHY address
135+ * @retval ETH_ERROR: Ethernet initialization failed
136+ * ETH_SUCCESS: Ethernet successfully initialized
137+ */
138+uint32_t ETH_Init(ETH_InitTypeDef* ETH_InitStruct, uint16_t PHYAddress)
139+{
140+ uint32_t RegValue = 0, tmpreg = 0;
141+ __IO uint32_t i = 0;
142+ RCC_ClocksTypeDef rcc_clocks;
143+ uint32_t hclk = 60000000;
144+ __IO uint32_t timeout = 0;
145+ /* Check the parameters */
146+ /* MAC --------------------------*/
147+ assert_param(IS_ETH_AUTONEGOTIATION(ETH_InitStruct->ETH_AutoNegotiation));
148+ assert_param(IS_ETH_WATCHDOG(ETH_InitStruct->ETH_Watchdog));
149+ assert_param(IS_ETH_JABBER(ETH_InitStruct->ETH_Jabber));
150+ assert_param(IS_ETH_INTER_FRAME_GAP(ETH_InitStruct->ETH_InterFrameGap));
151+ assert_param(IS_ETH_CARRIER_SENSE(ETH_InitStruct->ETH_CarrierSense));
152+ assert_param(IS_ETH_SPEED(ETH_InitStruct->ETH_Speed));
153+ assert_param(IS_ETH_RECEIVE_OWN(ETH_InitStruct->ETH_ReceiveOwn));
154+ assert_param(IS_ETH_LOOPBACK_MODE(ETH_InitStruct->ETH_LoopbackMode));
155+ assert_param(IS_ETH_DUPLEX_MODE(ETH_InitStruct->ETH_Mode));
156+ assert_param(IS_ETH_CHECKSUM_OFFLOAD(ETH_InitStruct->ETH_ChecksumOffload));
157+ assert_param(IS_ETH_RETRY_TRANSMISSION(ETH_InitStruct->ETH_RetryTransmission));
158+ assert_param(IS_ETH_AUTOMATIC_PADCRC_STRIP(ETH_InitStruct->ETH_AutomaticPadCRCStrip));
159+ assert_param(IS_ETH_BACKOFF_LIMIT(ETH_InitStruct->ETH_BackOffLimit));
160+ assert_param(IS_ETH_DEFERRAL_CHECK(ETH_InitStruct->ETH_DeferralCheck));
161+ assert_param(IS_ETH_RECEIVE_ALL(ETH_InitStruct->ETH_ReceiveAll));
162+ assert_param(IS_ETH_SOURCE_ADDR_FILTER(ETH_InitStruct->ETH_SourceAddrFilter));
163+ assert_param(IS_ETH_CONTROL_FRAMES(ETH_InitStruct->ETH_PassControlFrames));
164+ assert_param(IS_ETH_BROADCAST_FRAMES_RECEPTION(ETH_InitStruct->ETH_BroadcastFramesReception));
165+ assert_param(IS_ETH_DESTINATION_ADDR_FILTER(ETH_InitStruct->ETH_DestinationAddrFilter));
166+ assert_param(IS_ETH_PROMISCUOUS_MODE(ETH_InitStruct->ETH_PromiscuousMode));
167+ assert_param(IS_ETH_MULTICAST_FRAMES_FILTER(ETH_InitStruct->ETH_MulticastFramesFilter));
168+ assert_param(IS_ETH_UNICAST_FRAMES_FILTER(ETH_InitStruct->ETH_UnicastFramesFilter));
169+ assert_param(IS_ETH_PAUSE_TIME(ETH_InitStruct->ETH_PauseTime));
170+ assert_param(IS_ETH_ZEROQUANTA_PAUSE(ETH_InitStruct->ETH_ZeroQuantaPause));
171+ assert_param(IS_ETH_PAUSE_LOW_THRESHOLD(ETH_InitStruct->ETH_PauseLowThreshold));
172+ assert_param(IS_ETH_UNICAST_PAUSE_FRAME_DETECT(ETH_InitStruct->ETH_UnicastPauseFrameDetect));
173+ assert_param(IS_ETH_RECEIVE_FLOWCONTROL(ETH_InitStruct->ETH_ReceiveFlowControl));
174+ assert_param(IS_ETH_TRANSMIT_FLOWCONTROL(ETH_InitStruct->ETH_TransmitFlowControl));
175+ assert_param(IS_ETH_VLAN_TAG_COMPARISON(ETH_InitStruct->ETH_VLANTagComparison));
176+ assert_param(IS_ETH_VLAN_TAG_IDENTIFIER(ETH_InitStruct->ETH_VLANTagIdentifier));
177+ /* DMA --------------------------*/
178+ assert_param(IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(ETH_InitStruct->ETH_DropTCPIPChecksumErrorFrame));
179+ assert_param(IS_ETH_RECEIVE_STORE_FORWARD(ETH_InitStruct->ETH_ReceiveStoreForward));
180+ assert_param(IS_ETH_FLUSH_RECEIVE_FRAME(ETH_InitStruct->ETH_FlushReceivedFrame));
181+ assert_param(IS_ETH_TRANSMIT_STORE_FORWARD(ETH_InitStruct->ETH_TransmitStoreForward));
182+ assert_param(IS_ETH_TRANSMIT_THRESHOLD_CONTROL(ETH_InitStruct->ETH_TransmitThresholdControl));
183+ assert_param(IS_ETH_FORWARD_ERROR_FRAMES(ETH_InitStruct->ETH_ForwardErrorFrames));
184+ assert_param(IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(ETH_InitStruct->ETH_ForwardUndersizedGoodFrames));
185+ assert_param(IS_ETH_RECEIVE_THRESHOLD_CONTROL(ETH_InitStruct->ETH_ReceiveThresholdControl));
186+ assert_param(IS_ETH_SECOND_FRAME_OPERATE(ETH_InitStruct->ETH_SecondFrameOperate));
187+ assert_param(IS_ETH_ADDRESS_ALIGNED_BEATS(ETH_InitStruct->ETH_AddressAlignedBeats));
188+ assert_param(IS_ETH_FIXED_BURST(ETH_InitStruct->ETH_FixedBurst));
189+ assert_param(IS_ETH_RXDMA_BURST_LENGTH(ETH_InitStruct->ETH_RxDMABurstLength));
190+ assert_param(IS_ETH_TXDMA_BURST_LENGTH(ETH_InitStruct->ETH_TxDMABurstLength));
191+ assert_param(IS_ETH_DMA_DESC_SKIP_LENGTH(ETH_InitStruct->ETH_DescriptorSkipLength));
192+ assert_param(IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(ETH_InitStruct->ETH_DMAArbitration));
193+ /*-------------------------------- MAC Config ------------------------------*/
194+ /*---------------------- ETHERNET MACMIIAR Configuration -------------------*/
195+ /* Get the ETHERNET MACMIIAR value */
196+ tmpreg = ETH->MACMIIAR;
197+ /* Clear CSR Clock Range CR[2:0] bits */
198+ tmpreg &= MACMIIAR_CR_MASK;
199+ /* Get hclk frequency value */
200+ RCC_GetClocksFreq(&rcc_clocks);
201+ hclk = rcc_clocks.HCLK_Frequency;
202+ /* Set CR bits depending on hclk value */
203+ if((hclk >= 20000000)&&(hclk < 35000000))
204+ {
205+ /* CSR Clock Range between 20-35 MHz */
206+ tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div16;
207+ }
208+ else if((hclk >= 35000000)&&(hclk < 60000000))
209+ {
210+ /* CSR Clock Range between 35-60 MHz */
211+ tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div26;
212+ }
213+ else /* ((hclk >= 60000000)&&(hclk <= 72000000)) */
214+ {
215+ /* CSR Clock Range between 60-72 MHz */
216+ tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div42;
217+ }
218+ /* Write to ETHERNET MAC MIIAR: Configure the ETHERNET CSR Clock Range */
219+ ETH->MACMIIAR = (uint32_t)tmpreg;
220+ /*-------------------- PHY initialization and configuration ----------------*/
221+ /* Put the PHY in reset mode */
222+ if(!(ETH_WritePHYRegister(PHYAddress, PHY_BCR, PHY_Reset)))
223+ {
224+ /* Return ERROR in case of write timeout */
225+ return ETH_ERROR;
226+ }
227+
228+ /* Delay to assure PHY reset */
229+ _eth_delay_(PHY_ResetDelay);
230+
231+
232+ if(ETH_InitStruct->ETH_AutoNegotiation != ETH_AutoNegotiation_Disable)
233+ {
234+ /* We wait for linked satus... */
235+ do
236+ {
237+ timeout++;
238+ } while (!(ETH_ReadPHYRegister(PHYAddress, PHY_BSR) & PHY_Linked_Status) && (timeout < PHY_READ_TO));
239+ /* Return ERROR in case of timeout */
240+ if(timeout == PHY_READ_TO)
241+ {
242+ return ETH_ERROR;
243+ }
244+ /* Reset Timeout counter */
245+ timeout = 0;
246+
247+ /* Enable Auto-Negotiation */
248+ if(!(ETH_WritePHYRegister(PHYAddress, PHY_BCR, PHY_AutoNegotiation)))
249+ {
250+ /* Return ERROR in case of write timeout */
251+ return ETH_ERROR;
252+ }
253+
254+ /* Wait until the autonegotiation will be completed */
255+ do
256+ {
257+ timeout++;
258+ } while (!(ETH_ReadPHYRegister(PHYAddress, PHY_BSR) & PHY_AutoNego_Complete) && (timeout < (uint32_t)PHY_READ_TO));
259+ /* Return ERROR in case of timeout */
260+ if(timeout == PHY_READ_TO)
261+ {
262+ return ETH_ERROR;
263+ }
264+ /* Reset Timeout counter */
265+ timeout = 0;
266+
267+ /* Read the result of the autonegotiation */
268+ RegValue = ETH_ReadPHYRegister(PHYAddress, PHY_SR);
269+
270+ /* Configure the MAC with the Duplex Mode fixed by the autonegotiation process */
271+ if((RegValue & PHY_Duplex_Status) != (uint32_t)RESET)
272+ {
273+ /* Set Ethernet duplex mode to FullDuplex following the autonegotiation */
274+ ETH_InitStruct->ETH_Mode = ETH_Mode_FullDuplex;
275+
276+ }
277+ else
278+ {
279+ /* Set Ethernet duplex mode to HalfDuplex following the autonegotiation */
280+ ETH_InitStruct->ETH_Mode = ETH_Mode_HalfDuplex;
281+ }
282+ /* Configure the MAC with the speed fixed by the autonegotiation process */
283+ if(RegValue & PHY_Speed_Status)
284+ {
285+ /* Set Ethernet speed to 10M following the autonegotiation */
286+ ETH_InitStruct->ETH_Speed = ETH_Speed_10M;
287+ }
288+ else
289+ {
290+ /* Set Ethernet speed to 100M following the autonegotiation */
291+ ETH_InitStruct->ETH_Speed = ETH_Speed_100M;
292+ }
293+ }
294+ else
295+ {
296+ if(!ETH_WritePHYRegister(PHYAddress, PHY_BCR, ((uint16_t)(ETH_InitStruct->ETH_Mode >> 3) |
297+ (uint16_t)(ETH_InitStruct->ETH_Speed >> 1))))
298+ {
299+ /* Return ERROR in case of write timeout */
300+ return ETH_ERROR;
301+ }
302+ /* Delay to assure PHY configuration */
303+ _eth_delay_(PHY_ConfigDelay);
304+
305+ }
306+ /*------------------------ ETHERNET MACCR Configuration --------------------*/
307+ /* Get the ETHERNET MACCR value */
308+ tmpreg = ETH->MACCR;
309+ /* Clear WD, PCE, PS, TE and RE bits */
310+ tmpreg &= MACCR_CLEAR_MASK;
311+ /* Set the WD bit according to ETH_Watchdog value */
312+ /* Set the JD: bit according to ETH_Jabber value */
313+ /* Set the IFG bit according to ETH_InterFrameGap value */
314+ /* Set the DCRS bit according to ETH_CarrierSense value */
315+ /* Set the FES bit according to ETH_Speed value */
316+ /* Set the DO bit according to ETH_ReceiveOwn value */
317+ /* Set the LM bit according to ETH_LoopbackMode value */
318+ /* Set the DM bit according to ETH_Mode value */
319+ /* Set the IPC bit according to ETH_ChecksumOffload value */
320+ /* Set the DR bit according to ETH_RetryTransmission value */
321+ /* Set the ACS bit according to ETH_AutomaticPadCRCStrip value */
322+ /* Set the BL bit according to ETH_BackOffLimit value */
323+ /* Set the DC bit according to ETH_DeferralCheck value */
324+ tmpreg |= (uint32_t)(ETH_InitStruct->ETH_Watchdog |
325+ ETH_InitStruct->ETH_Jabber |
326+ ETH_InitStruct->ETH_InterFrameGap |
327+ ETH_InitStruct->ETH_CarrierSense |
328+ ETH_InitStruct->ETH_Speed |
329+ ETH_InitStruct->ETH_ReceiveOwn |
330+ ETH_InitStruct->ETH_LoopbackMode |
331+ ETH_InitStruct->ETH_Mode |
332+ ETH_InitStruct->ETH_ChecksumOffload |
333+ ETH_InitStruct->ETH_RetryTransmission |
334+ ETH_InitStruct->ETH_AutomaticPadCRCStrip |
335+ ETH_InitStruct->ETH_BackOffLimit |
336+ ETH_InitStruct->ETH_DeferralCheck);
337+ /* Write to ETHERNET MACCR */
338+ ETH->MACCR = (uint32_t)tmpreg;
339+
340+ /*----------------------- ETHERNET MACFFR Configuration --------------------*/
341+ /* Set the RA bit according to ETH_ReceiveAll value */
342+ /* Set the SAF and SAIF bits according to ETH_SourceAddrFilter value */
343+ /* Set the PCF bit according to ETH_PassControlFrames value */
344+ /* Set the DBF bit according to ETH_BroadcastFramesReception value */
345+ /* Set the DAIF bit according to ETH_DestinationAddrFilter value */
346+ /* Set the PR bit according to ETH_PromiscuousMode value */
347+ /* Set the PM, HMC and HPF bits according to ETH_MulticastFramesFilter value */
348+ /* Set the HUC and HPF bits according to ETH_UnicastFramesFilter value */
349+ /* Write to ETHERNET MACFFR */
350+ ETH->MACFFR = (uint32_t)(ETH_InitStruct->ETH_ReceiveAll |
351+ ETH_InitStruct->ETH_SourceAddrFilter |
352+ ETH_InitStruct->ETH_PassControlFrames |
353+ ETH_InitStruct->ETH_BroadcastFramesReception |
354+ ETH_InitStruct->ETH_DestinationAddrFilter |
355+ ETH_InitStruct->ETH_PromiscuousMode |
356+ ETH_InitStruct->ETH_MulticastFramesFilter |
357+ ETH_InitStruct->ETH_UnicastFramesFilter);
358+ /*--------------- ETHERNET MACHTHR and MACHTLR Configuration ---------------*/
359+ /* Write to ETHERNET MACHTHR */
360+ ETH->MACHTHR = (uint32_t)ETH_InitStruct->ETH_HashTableHigh;
361+ /* Write to ETHERNET MACHTLR */
362+ ETH->MACHTLR = (uint32_t)ETH_InitStruct->ETH_HashTableLow;
363+ /*----------------------- ETHERNET MACFCR Configuration --------------------*/
364+ /* Get the ETHERNET MACFCR value */
365+ tmpreg = ETH->MACFCR;
366+ /* Clear xx bits */
367+ tmpreg &= MACFCR_CLEAR_MASK;
368+
369+ /* Set the PT bit according to ETH_PauseTime value */
370+ /* Set the DZPQ bit according to ETH_ZeroQuantaPause value */
371+ /* Set the PLT bit according to ETH_PauseLowThreshold value */
372+ /* Set the UP bit according to ETH_UnicastPauseFrameDetect value */
373+ /* Set the RFE bit according to ETH_ReceiveFlowControl value */
374+ /* Set the TFE bit according to ETH_TransmitFlowControl value */
375+ tmpreg |= (uint32_t)((ETH_InitStruct->ETH_PauseTime << 16) |
376+ ETH_InitStruct->ETH_ZeroQuantaPause |
377+ ETH_InitStruct->ETH_PauseLowThreshold |
378+ ETH_InitStruct->ETH_UnicastPauseFrameDetect |
379+ ETH_InitStruct->ETH_ReceiveFlowControl |
380+ ETH_InitStruct->ETH_TransmitFlowControl);
381+ /* Write to ETHERNET MACFCR */
382+ ETH->MACFCR = (uint32_t)tmpreg;
383+ /*----------------------- ETHERNET MACVLANTR Configuration -----------------*/
384+ /* Set the ETV bit according to ETH_VLANTagComparison value */
385+ /* Set the VL bit according to ETH_VLANTagIdentifier value */
386+ ETH->MACVLANTR = (uint32_t)(ETH_InitStruct->ETH_VLANTagComparison |
387+ ETH_InitStruct->ETH_VLANTagIdentifier);
388+
389+ /*-------------------------------- DMA Config ------------------------------*/
390+ /*----------------------- ETHERNET DMAOMR Configuration --------------------*/
391+ /* Get the ETHERNET DMAOMR value */
392+ tmpreg = ETH->DMAOMR;
393+ /* Clear xx bits */
394+ tmpreg &= DMAOMR_CLEAR_MASK;
395+
396+ /* Set the DT bit according to ETH_DropTCPIPChecksumErrorFrame value */
397+ /* Set the RSF bit according to ETH_ReceiveStoreForward value */
398+ /* Set the DFF bit according to ETH_FlushReceivedFrame value */
399+ /* Set the TSF bit according to ETH_TransmitStoreForward value */
400+ /* Set the TTC bit according to ETH_TransmitThresholdControl value */
401+ /* Set the FEF bit according to ETH_ForwardErrorFrames value */
402+ /* Set the FUF bit according to ETH_ForwardUndersizedGoodFrames value */
403+ /* Set the RTC bit according to ETH_ReceiveThresholdControl value */
404+ /* Set the OSF bit according to ETH_SecondFrameOperate value */
405+ tmpreg |= (uint32_t)(ETH_InitStruct->ETH_DropTCPIPChecksumErrorFrame |
406+ ETH_InitStruct->ETH_ReceiveStoreForward |
407+ ETH_InitStruct->ETH_FlushReceivedFrame |
408+ ETH_InitStruct->ETH_TransmitStoreForward |
409+ ETH_InitStruct->ETH_TransmitThresholdControl |
410+ ETH_InitStruct->ETH_ForwardErrorFrames |
411+ ETH_InitStruct->ETH_ForwardUndersizedGoodFrames |
412+ ETH_InitStruct->ETH_ReceiveThresholdControl |
413+ ETH_InitStruct->ETH_SecondFrameOperate);
414+ /* Write to ETHERNET DMAOMR */
415+ ETH->DMAOMR = (uint32_t)tmpreg;
416+
417+ /*----------------------- ETHERNET DMABMR Configuration --------------------*/
418+ /* Set the AAL bit according to ETH_AddressAlignedBeats value */
419+ /* Set the FB bit according to ETH_FixedBurst value */
420+ /* Set the RPBL and 4*PBL bits according to ETH_RxDMABurstLength value */
421+ /* Set the PBL and 4*PBL bits according to ETH_TxDMABurstLength value */
422+ /* Set the DSL bit according to ETH_DesciptorSkipLength value */
423+ /* Set the PR and DA bits according to ETH_DMAArbitration value */
424+ ETH->DMABMR = (uint32_t)(ETH_InitStruct->ETH_AddressAlignedBeats |
425+ ETH_InitStruct->ETH_FixedBurst |
426+ ETH_InitStruct->ETH_RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */
427+ ETH_InitStruct->ETH_TxDMABurstLength |
428+ (ETH_InitStruct->ETH_DescriptorSkipLength << 2) |
429+ ETH_InitStruct->ETH_DMAArbitration |
430+ ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */
431+ /* Return Ethernet configuration success */
432+ return ETH_SUCCESS;
433+}
434+
435+/**
436+ * @brief Fills each ETH_InitStruct member with its default value.
437+ * @param ETH_InitStruct: pointer to a ETH_InitTypeDef structure which will be initialized.
438+ * @retval None
439+ */
440+void ETH_StructInit(ETH_InitTypeDef* ETH_InitStruct)
441+{
442+ /* ETH_InitStruct members default value */
443+ /*------------------------ MAC -----------------------------------*/
444+ ETH_InitStruct->ETH_AutoNegotiation = ETH_AutoNegotiation_Disable;
445+ ETH_InitStruct->ETH_Watchdog = ETH_Watchdog_Enable;
446+ ETH_InitStruct->ETH_Jabber = ETH_Jabber_Enable;
447+ ETH_InitStruct->ETH_InterFrameGap = ETH_InterFrameGap_96Bit;
448+ ETH_InitStruct->ETH_CarrierSense = ETH_CarrierSense_Enable;
449+ ETH_InitStruct->ETH_Speed = ETH_Speed_10M;
450+ ETH_InitStruct->ETH_ReceiveOwn = ETH_ReceiveOwn_Enable;
451+ ETH_InitStruct->ETH_LoopbackMode = ETH_LoopbackMode_Disable;
452+ ETH_InitStruct->ETH_Mode = ETH_Mode_HalfDuplex;
453+ ETH_InitStruct->ETH_ChecksumOffload = ETH_ChecksumOffload_Disable;
454+ ETH_InitStruct->ETH_RetryTransmission = ETH_RetryTransmission_Enable;
455+ ETH_InitStruct->ETH_AutomaticPadCRCStrip = ETH_AutomaticPadCRCStrip_Disable;
456+ ETH_InitStruct->ETH_BackOffLimit = ETH_BackOffLimit_10;
457+ ETH_InitStruct->ETH_DeferralCheck = ETH_DeferralCheck_Disable;
458+ ETH_InitStruct->ETH_ReceiveAll = ETH_ReceiveAll_Disable;
459+ ETH_InitStruct->ETH_SourceAddrFilter = ETH_SourceAddrFilter_Disable;
460+ ETH_InitStruct->ETH_PassControlFrames = ETH_PassControlFrames_BlockAll;
461+ ETH_InitStruct->ETH_BroadcastFramesReception = ETH_BroadcastFramesReception_Disable;
462+ ETH_InitStruct->ETH_DestinationAddrFilter = ETH_DestinationAddrFilter_Normal;
463+ ETH_InitStruct->ETH_PromiscuousMode = ETH_PromiscuousMode_Disable;
464+ ETH_InitStruct->ETH_MulticastFramesFilter = ETH_MulticastFramesFilter_Perfect;
465+ ETH_InitStruct->ETH_UnicastFramesFilter = ETH_UnicastFramesFilter_Perfect;
466+ ETH_InitStruct->ETH_HashTableHigh = 0x0;
467+ ETH_InitStruct->ETH_HashTableLow = 0x0;
468+ ETH_InitStruct->ETH_PauseTime = 0x0;
469+ ETH_InitStruct->ETH_ZeroQuantaPause = ETH_ZeroQuantaPause_Disable;
470+ ETH_InitStruct->ETH_PauseLowThreshold = ETH_PauseLowThreshold_Minus4;
471+ ETH_InitStruct->ETH_UnicastPauseFrameDetect = ETH_UnicastPauseFrameDetect_Disable;
472+ ETH_InitStruct->ETH_ReceiveFlowControl = ETH_ReceiveFlowControl_Disable;
473+ ETH_InitStruct->ETH_TransmitFlowControl = ETH_TransmitFlowControl_Disable;
474+ ETH_InitStruct->ETH_VLANTagComparison = ETH_VLANTagComparison_16Bit;
475+ ETH_InitStruct->ETH_VLANTagIdentifier = 0x0;
476+ /*------------------------ DMA -----------------------------------*/
477+ ETH_InitStruct->ETH_DropTCPIPChecksumErrorFrame = ETH_DropTCPIPChecksumErrorFrame_Disable;
478+ ETH_InitStruct->ETH_ReceiveStoreForward = ETH_ReceiveStoreForward_Enable;
479+ ETH_InitStruct->ETH_FlushReceivedFrame = ETH_FlushReceivedFrame_Disable;
480+ ETH_InitStruct->ETH_TransmitStoreForward = ETH_TransmitStoreForward_Enable;
481+ ETH_InitStruct->ETH_TransmitThresholdControl = ETH_TransmitThresholdControl_64Bytes;
482+ ETH_InitStruct->ETH_ForwardErrorFrames = ETH_ForwardErrorFrames_Disable;
483+ ETH_InitStruct->ETH_ForwardUndersizedGoodFrames = ETH_ForwardUndersizedGoodFrames_Disable;
484+ ETH_InitStruct->ETH_ReceiveThresholdControl = ETH_ReceiveThresholdControl_64Bytes;
485+ ETH_InitStruct->ETH_SecondFrameOperate = ETH_SecondFrameOperate_Disable;
486+ ETH_InitStruct->ETH_AddressAlignedBeats = ETH_AddressAlignedBeats_Enable;
487+ ETH_InitStruct->ETH_FixedBurst = ETH_FixedBurst_Disable;
488+ ETH_InitStruct->ETH_RxDMABurstLength = ETH_RxDMABurstLength_1Beat;
489+ ETH_InitStruct->ETH_TxDMABurstLength = ETH_TxDMABurstLength_1Beat;
490+ ETH_InitStruct->ETH_DescriptorSkipLength = 0x0;
491+ ETH_InitStruct->ETH_DMAArbitration = ETH_DMAArbitration_RoundRobin_RxTx_1_1;
492+}
493+
494+/**
495+ * @brief Enables ENET MAC and DMA reception/transmission
496+ * @param None
497+ * @retval None
498+ */
499+void ETH_Start(void)
500+{
501+ /* Enable transmit state machine of the MAC for transmission on the MII */
502+ ETH_MACTransmissionCmd(ENABLE);
503+ /* Flush Transmit FIFO */
504+ ETH_FlushTransmitFIFO();
505+ /* Enable receive state machine of the MAC for reception from the MII */
506+ ETH_MACReceptionCmd(ENABLE);
507+
508+ /* Start DMA transmission */
509+ ETH_DMATransmissionCmd(ENABLE);
510+ /* Start DMA reception */
511+ ETH_DMAReceptionCmd(ENABLE);
512+}
513+
514+/**
515+ * @brief Transmits a packet, from application buffer, pointed by ppkt.
516+ * @param ppkt: pointer to the application's packet buffer to transmit.
517+ * @param FrameLength: Tx Packet size.
518+ * @retval ETH_ERROR: in case of Tx desc owned by DMA
519+ * ETH_SUCCESS: for correct transmission
520+ */
521+uint32_t ETH_HandleTxPkt(uint8_t *ppkt, uint16_t FrameLength)
522+{
523+ uint32_t offset = 0;
524+
525+ /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */
526+ if((DMATxDescToSet->Status & ETH_DMATxDesc_OWN) != (uint32_t)RESET)
527+ {
528+ /* Return ERROR: OWN bit set */
529+ return ETH_ERROR;
530+ }
531+
532+ /* Copy the frame to be sent into memory pointed by the current ETHERNET DMA Tx descriptor */
533+ for(offset=0; offset<FrameLength; offset++)
534+ {
535+ (*(__IO uint8_t *)((DMATxDescToSet->Buffer1Addr) + offset)) = (*(ppkt + offset));
536+ }
537+
538+ /* Setting the Frame Length: bits[12:0] */
539+ DMATxDescToSet->ControlBufferSize = (FrameLength & ETH_DMATxDesc_TBS1);
540+ /* Setting the last segment and first segment bits (in this case a frame is transmitted in one descriptor) */
541+ DMATxDescToSet->Status |= ETH_DMATxDesc_LS | ETH_DMATxDesc_FS;
542+ /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
543+ DMATxDescToSet->Status |= ETH_DMATxDesc_OWN;
544+ /* When Tx Buffer unavailable flag is set: clear it and resume transmission */
545+ if ((ETH->DMASR & ETH_DMASR_TBUS) != (uint32_t)RESET)
546+ {
547+ /* Clear TBUS ETHERNET DMA flag */
548+ ETH->DMASR = ETH_DMASR_TBUS;
549+ /* Resume DMA transmission*/
550+ ETH->DMATPDR = 0;
551+ }
552+
553+ /* Update the ETHERNET DMA global Tx descriptor with next Tx decriptor */
554+ /* Chained Mode */
555+ if((DMATxDescToSet->Status & ETH_DMATxDesc_TCH) != (uint32_t)RESET)
556+ {
557+ /* Selects the next DMA Tx descriptor list for next buffer to send */
558+ DMATxDescToSet = (ETH_DMADESCTypeDef*) (DMATxDescToSet->Buffer2NextDescAddr);
559+ }
560+ else /* Ring Mode */
561+ {
562+ if((DMATxDescToSet->Status & ETH_DMATxDesc_TER) != (uint32_t)RESET)
563+ {
564+ /* Selects the first DMA Tx descriptor for next buffer to send: last Tx descriptor was used */
565+ DMATxDescToSet = (ETH_DMADESCTypeDef*) (ETH->DMATDLAR);
566+ }
567+ else
568+ {
569+ /* Selects the next DMA Tx descriptor list for next buffer to send */
570+ DMATxDescToSet = (ETH_DMADESCTypeDef*) ((uint32_t)DMATxDescToSet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2));
571+ }
572+ }
573+ /* Return SUCCESS */
574+ return ETH_SUCCESS;
575+}
576+
577+/**
578+ * @brief Receives a packet and copies it to memory pointed by ppkt.
579+ * @param ppkt: pointer to the application packet receive buffer.
580+ * @retval ETH_ERROR: if there is error in reception
581+ * framelength: received packet size if packet reception is correct
582+ */
583+uint32_t ETH_HandleRxPkt(uint8_t *ppkt)
584+{
585+ uint32_t offset = 0, framelength = 0;
586+ /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */
587+ if((DMARxDescToGet->Status & ETH_DMARxDesc_OWN) != (uint32_t)RESET)
588+ {
589+ /* Return error: OWN bit set */
590+ return ETH_ERROR;
591+ }
592+
593+ if(((DMARxDescToGet->Status & ETH_DMARxDesc_ES) == (uint32_t)RESET) &&
594+ ((DMARxDescToGet->Status & ETH_DMARxDesc_LS) != (uint32_t)RESET) &&
595+ ((DMARxDescToGet->Status & ETH_DMARxDesc_FS) != (uint32_t)RESET))
596+ {
597+ /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */
598+ framelength = ((DMARxDescToGet->Status & ETH_DMARxDesc_FL) >> ETH_DMARXDESC_FRAME_LENGTHSHIFT) - 4;
599+ /* Copy the received frame into buffer from memory pointed by the current ETHERNET DMA Rx descriptor */
600+ for(offset=0; offset<framelength; offset++)
601+ {
602+ (*(ppkt + offset)) = (*(__IO uint8_t *)((DMARxDescToGet->Buffer1Addr) + offset));
603+ }
604+ }
605+ else
606+ {
607+ /* Return ERROR */
608+ framelength = ETH_ERROR;
609+ }
610+ /* Set Own bit of the Rx descriptor Status: gives the buffer back to ETHERNET DMA */
611+ DMARxDescToGet->Status = ETH_DMARxDesc_OWN;
612+
613+ /* When Rx Buffer unavailable flag is set: clear it and resume reception */
614+ if ((ETH->DMASR & ETH_DMASR_RBUS) != (uint32_t)RESET)
615+ {
616+ /* Clear RBUS ETHERNET DMA flag */
617+ ETH->DMASR = ETH_DMASR_RBUS;
618+ /* Resume DMA reception */
619+ ETH->DMARPDR = 0;
620+ }
621+
622+ /* Update the ETHERNET DMA global Rx descriptor with next Rx decriptor */
623+ /* Chained Mode */
624+ if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RCH) != (uint32_t)RESET)
625+ {
626+ /* Selects the next DMA Rx descriptor list for next buffer to read */
627+ DMARxDescToGet = (ETH_DMADESCTypeDef*) (DMARxDescToGet->Buffer2NextDescAddr);
628+ }
629+ else /* Ring Mode */
630+ {
631+ if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RER) != (uint32_t)RESET)
632+ {
633+ /* Selects the first DMA Rx descriptor for next buffer to read: last Rx descriptor was used */
634+ DMARxDescToGet = (ETH_DMADESCTypeDef*) (ETH->DMARDLAR);
635+ }
636+ else
637+ {
638+ /* Selects the next DMA Rx descriptor list for next buffer to read */
639+ DMARxDescToGet = (ETH_DMADESCTypeDef*) ((uint32_t)DMARxDescToGet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2));
640+ }
641+ }
642+
643+ /* Return Frame Length/ERROR */
644+ return (framelength);
645+}
646+
647+/**
648+ * @brief Get the size of received the received packet.
649+ * @param None
650+ * @retval framelength: received packet size
651+ */
652+uint32_t ETH_GetRxPktSize(void)
653+{
654+ uint32_t frameLength = 0;
655+ if(((DMARxDescToGet->Status & ETH_DMARxDesc_OWN) == (uint32_t)RESET) &&
656+ ((DMARxDescToGet->Status & ETH_DMARxDesc_ES) == (uint32_t)RESET) &&
657+ ((DMARxDescToGet->Status & ETH_DMARxDesc_LS) != (uint32_t)RESET) &&
658+ ((DMARxDescToGet->Status & ETH_DMARxDesc_FS) != (uint32_t)RESET))
659+ {
660+ /* Get the size of the packet: including 4 bytes of the CRC */
661+ frameLength = ETH_GetDMARxDescFrameLength(DMARxDescToGet);
662+ }
663+
664+ /* Return Frame Length */
665+ return frameLength;
666+}
667+
668+/**
669+ * @brief Drop a Received packet (too small packet, etc...)
670+ * @param None
671+ * @retval None
672+ */
673+void ETH_DropRxPkt(void)
674+{
675+ /* Set Own bit of the Rx descriptor Status: gives the buffer back to ETHERNET DMA */
676+ DMARxDescToGet->Status = ETH_DMARxDesc_OWN;
677+ /* Chained Mode */
678+ if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RCH) != (uint32_t)RESET)
679+ {
680+ /* Selects the next DMA Rx descriptor list for next buffer read */
681+ DMARxDescToGet = (ETH_DMADESCTypeDef*) (DMARxDescToGet->Buffer2NextDescAddr);
682+ }
683+ else /* Ring Mode */
684+ {
685+ if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RER) != (uint32_t)RESET)
686+ {
687+ /* Selects the next DMA Rx descriptor list for next buffer read: this will
688+ be the first Rx descriptor in this case */
689+ DMARxDescToGet = (ETH_DMADESCTypeDef*) (ETH->DMARDLAR);
690+ }
691+ else
692+ {
693+ /* Selects the next DMA Rx descriptor list for next buffer read */
694+ DMARxDescToGet = (ETH_DMADESCTypeDef*) ((uint32_t)DMARxDescToGet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2));
695+ }
696+ }
697+}
698+
699+/*--------------------------------- PHY ------------------------------------*/
700+/**
701+ * @brief Read a PHY register
702+ * @param PHYAddress: PHY device address, is the index of one of supported 32 PHY devices.
703+ * This parameter can be one of the following values: 0,..,31
704+ * @param PHYReg: PHY register address, is the index of one of the 32 PHY register.
705+ * This parameter can be one of the following values:
706+ * @arg PHY_BCR: Tranceiver Basic Control Register
707+ * @arg PHY_BSR: Tranceiver Basic Status Register
708+ * @arg PHY_SR : Tranceiver Status Register
709+ * @arg More PHY register could be read depending on the used PHY
710+ * @retval ETH_ERROR: in case of timeout
711+ * MAC MIIDR register value: Data read from the selected PHY register (correct read )
712+ */
713+uint16_t ETH_ReadPHYRegister(uint16_t PHYAddress, uint16_t PHYReg)
714+{
715+ uint32_t tmpreg = 0;
716+__IO uint32_t timeout = 0;
717+ /* Check the parameters */
718+ assert_param(IS_ETH_PHY_ADDRESS(PHYAddress));
719+ assert_param(IS_ETH_PHY_REG(PHYReg));
720+
721+ /* Get the ETHERNET MACMIIAR value */
722+ tmpreg = ETH->MACMIIAR;
723+ /* Keep only the CSR Clock Range CR[2:0] bits value */
724+ tmpreg &= ~MACMIIAR_CR_MASK;
725+ /* Prepare the MII address register value */
726+ tmpreg |=(((uint32_t)PHYAddress<<11) & ETH_MACMIIAR_PA); /* Set the PHY device address */
727+ tmpreg |=(((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR); /* Set the PHY register address */
728+ tmpreg &= ~ETH_MACMIIAR_MW; /* Set the read mode */
729+ tmpreg |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */
730+ /* Write the result value into the MII Address register */
731+ ETH->MACMIIAR = tmpreg;
732+ /* Check for the Busy flag */
733+ do
734+ {
735+ timeout++;
736+ tmpreg = ETH->MACMIIAR;
737+ } while ((tmpreg & ETH_MACMIIAR_MB) && (timeout < (uint32_t)PHY_READ_TO));
738+ /* Return ERROR in case of timeout */
739+ if(timeout == PHY_READ_TO)
740+ {
741+ return (uint16_t)ETH_ERROR;
742+ }
743+
744+ /* Return data register value */
745+ return (uint16_t)(ETH->MACMIIDR);
746+}
747+
748+/**
749+ * @brief Write to a PHY register
750+ * @param PHYAddress: PHY device address, is the index of one of supported 32 PHY devices.
751+ * This parameter can be one of the following values: 0,..,31
752+ * @param PHYReg: PHY register address, is the index of one of the 32 PHY register.
753+ * This parameter can be one of the following values:
754+ * @arg PHY_BCR : Tranceiver Control Register
755+ * @arg More PHY register could be written depending on the used PHY
756+ * @param PHYValue: the value to write
757+ * @retval ETH_ERROR: in case of timeout
758+ * ETH_SUCCESS: for correct write
759+ */
760+uint32_t ETH_WritePHYRegister(uint16_t PHYAddress, uint16_t PHYReg, uint16_t PHYValue)
761+{
762+ uint32_t tmpreg = 0;
763+ __IO uint32_t timeout = 0;
764+ /* Check the parameters */
765+ assert_param(IS_ETH_PHY_ADDRESS(PHYAddress));
766+ assert_param(IS_ETH_PHY_REG(PHYReg));
767+
768+ /* Get the ETHERNET MACMIIAR value */
769+ tmpreg = ETH->MACMIIAR;
770+ /* Keep only the CSR Clock Range CR[2:0] bits value */
771+ tmpreg &= ~MACMIIAR_CR_MASK;
772+ /* Prepare the MII register address value */
773+ tmpreg |=(((uint32_t)PHYAddress<<11) & ETH_MACMIIAR_PA); /* Set the PHY device address */
774+ tmpreg |=(((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR); /* Set the PHY register address */
775+ tmpreg |= ETH_MACMIIAR_MW; /* Set the write mode */
776+ tmpreg |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */
777+ /* Give the value to the MII data register */
778+ ETH->MACMIIDR = PHYValue;
779+ /* Write the result value into the MII Address register */
780+ ETH->MACMIIAR = tmpreg;
781+ /* Check for the Busy flag */
782+ do
783+ {
784+ timeout++;
785+ tmpreg = ETH->MACMIIAR;
786+ } while ((tmpreg & ETH_MACMIIAR_MB) && (timeout < (uint32_t)PHY_WRITE_TO));
787+ /* Return ERROR in case of timeout */
788+ if(timeout == PHY_WRITE_TO)
789+ {
790+ return ETH_ERROR;
791+ }
792+
793+ /* Return SUCCESS */
794+ return ETH_SUCCESS;
795+}
796+
797+/**
798+ * @brief Enables or disables the PHY loopBack mode.
799+ * @Note: Don't be confused with ETH_MACLoopBackCmd function which enables internal
800+ * loopback at MII level
801+ * @param PHYAddress: PHY device address, is the index of one of supported 32 PHY devices.
802+ * This parameter can be one of the following values:
803+ * @param NewState: new state of the PHY loopBack mode.
804+ * This parameter can be: ENABLE or DISABLE.
805+ * @retval ETH_ERROR: in case of bad PHY configuration
806+ * ETH_SUCCESS: for correct PHY configuration
807+ */
808+uint32_t ETH_PHYLoopBackCmd(uint16_t PHYAddress, FunctionalState NewState)
809+{
810+ uint16_t tmpreg = 0;
811+ /* Check the parameters */
812+ assert_param(IS_ETH_PHY_ADDRESS(PHYAddress));
813+ assert_param(IS_FUNCTIONAL_STATE(NewState));
814+
815+ /* Get the PHY configuration to update it */
816+ tmpreg = ETH_ReadPHYRegister(PHYAddress, PHY_BCR);
817+
818+ if (NewState != DISABLE)
819+ {
820+ /* Enable the PHY loopback mode */
821+ tmpreg |= PHY_Loopback;
822+ }
823+ else
824+ {
825+ /* Disable the PHY loopback mode: normal mode */
826+ tmpreg &= (uint16_t)(~(uint16_t)PHY_Loopback);
827+ }
828+ /* Update the PHY control register with the new configuration */
829+ if(ETH_WritePHYRegister(PHYAddress, PHY_BCR, tmpreg) != (uint32_t)RESET)
830+ {
831+ return ETH_SUCCESS;
832+ }
833+ else
834+ {
835+ /* Return SUCCESS */
836+ return ETH_ERROR;
837+ }
838+}
839+
840+/*--------------------------------- MAC ------------------------------------*/
841+/**
842+ * @brief Enables or disables the MAC transmission.
843+ * @param NewState: new state of the MAC transmission.
844+ * This parameter can be: ENABLE or DISABLE.
845+ * @retval None
846+ */
847+void ETH_MACTransmissionCmd(FunctionalState NewState)
848+{
849+ /* Check the parameters */
850+ assert_param(IS_FUNCTIONAL_STATE(NewState));
851+
852+ if (NewState != DISABLE)
853+ {
854+ /* Enable the MAC transmission */
855+ ETH->MACCR |= ETH_MACCR_TE;
856+ }
857+ else
858+ {
859+ /* Disable the MAC transmission */
860+ ETH->MACCR &= ~ETH_MACCR_TE;
861+ }
862+}
863+
864+/**
865+ * @brief Enables or disables the MAC reception.
866+ * @param NewState: new state of the MAC reception.
867+ * This parameter can be: ENABLE or DISABLE.
868+ * @retval None
869+ */
870+void ETH_MACReceptionCmd(FunctionalState NewState)
871+{
872+ /* Check the parameters */
873+ assert_param(IS_FUNCTIONAL_STATE(NewState));
874+
875+ if (NewState != DISABLE)
876+ {
877+ /* Enable the MAC reception */
878+ ETH->MACCR |= ETH_MACCR_RE;
879+ }
880+ else
881+ {
882+ /* Disable the MAC reception */
883+ ETH->MACCR &= ~ETH_MACCR_RE;
884+ }
885+}
886+
887+/**
888+ * @brief Checks whether the ETHERNET flow control busy bit is set or not.
889+ * @param None
890+ * @retval The new state of flow control busy status bit (SET or RESET).
891+ */
892+FlagStatus ETH_GetFlowControlBusyStatus(void)
893+{
894+ FlagStatus bitstatus = RESET;
895+ /* The Flow Control register should not be written to until this bit is cleared */
896+ if ((ETH->MACFCR & ETH_MACFCR_FCBBPA) != (uint32_t)RESET)
897+ {
898+ bitstatus = SET;
899+ }
900+ else
901+ {
902+ bitstatus = RESET;
903+ }
904+ return bitstatus;
905+}
906+
907+/**
908+ * @brief Initiate a Pause Control Frame (Full-duplex only).
909+ * @param None
910+ * @retval None
911+ */
912+void ETH_InitiatePauseControlFrame(void)
913+{
914+ /* When Set In full duplex MAC initiates pause control frame */
915+ ETH->MACFCR |= ETH_MACFCR_FCBBPA;
916+}
917+
918+/**
919+ * @brief Enables or disables the MAC BackPressure operation activation (Half-duplex only).
920+ * @param NewState: new state of the MAC BackPressure operation activation.
921+ * This parameter can be: ENABLE or DISABLE.
922+ * @retval None
923+ */
924+void ETH_BackPressureActivationCmd(FunctionalState NewState)
925+{
926+ /* Check the parameters */
927+ assert_param(IS_FUNCTIONAL_STATE(NewState));
928+
929+ if (NewState != DISABLE)
930+ {
931+ /* Activate the MAC BackPressure operation */
932+ /* In Half duplex: during backpressure, when the MAC receives a new frame,
933+ the transmitter starts sending a JAM pattern resulting in a collision */
934+ ETH->MACFCR |= ETH_MACFCR_FCBBPA;
935+ }
936+ else
937+ {
938+ /* Desactivate the MAC BackPressure operation */
939+ ETH->MACFCR &= ~ETH_MACFCR_FCBBPA;
940+ }
941+}
942+
943+/**
944+ * @brief Checks whether the specified ETHERNET MAC flag is set or not.
945+ * @param ETH_MAC_FLAG: specifies the flag to check.
946+ * This parameter can be one of the following values:
947+ * @arg ETH_MAC_FLAG_TST : Time stamp trigger flag
948+ * @arg ETH_MAC_FLAG_MMCT : MMC transmit flag
949+ * @arg ETH_MAC_FLAG_MMCR : MMC receive flag
950+ * @arg ETH_MAC_FLAG_MMC : MMC flag
951+ * @arg ETH_MAC_FLAG_PMT : PMT flag
952+ * @retval The new state of ETHERNET MAC flag (SET or RESET).
953+ */
954+FlagStatus ETH_GetMACFlagStatus(uint32_t ETH_MAC_FLAG)
955+{
956+ FlagStatus bitstatus = RESET;
957+ /* Check the parameters */
958+ assert_param(IS_ETH_MAC_GET_FLAG(ETH_MAC_FLAG));
959+ if ((ETH->MACSR & ETH_MAC_FLAG) != (uint32_t)RESET)
960+ {
961+ bitstatus = SET;
962+ }
963+ else
964+ {
965+ bitstatus = RESET;
966+ }
967+ return bitstatus;
968+}
969+
970+/**
971+ * @brief Checks whether the specified ETHERNET MAC interrupt has occurred or not.
972+ * @param ETH_MAC_IT: specifies the interrupt source to check.
973+ * This parameter can be one of the following values:
974+ * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt
975+ * @arg ETH_MAC_IT_MMCT : MMC transmit interrupt
976+ * @arg ETH_MAC_IT_MMCR : MMC receive interrupt
977+ * @arg ETH_MAC_IT_MMC : MMC interrupt
978+ * @arg ETH_MAC_IT_PMT : PMT interrupt
979+ * @retval The new state of ETHERNET MAC interrupt (SET or RESET).
980+ */
981+ITStatus ETH_GetMACITStatus(uint32_t ETH_MAC_IT)
982+{
983+ ITStatus bitstatus = RESET;
984+ /* Check the parameters */
985+ assert_param(IS_ETH_MAC_GET_IT(ETH_MAC_IT));
986+ if ((ETH->MACSR & ETH_MAC_IT) != (uint32_t)RESET)
987+ {
988+ bitstatus = SET;
989+ }
990+ else
991+ {
992+ bitstatus = RESET;
993+ }
994+ return bitstatus;
995+}
996+
997+/**
998+ * @brief Enables or disables the specified ETHERNET MAC interrupts.
999+ * @param ETH_MAC_IT: specifies the ETHERNET MAC interrupt sources to be
1000+ * enabled or disabled.
1001+ * This parameter can be any combination of the following values:
1002+ * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt
1003+ * @arg ETH_MAC_IT_PMT : PMT interrupt
1004+ * @param NewState: new state of the specified ETHERNET MAC interrupts.
1005+ * This parameter can be: ENABLE or DISABLE.
1006+ * @retval None
1007+ */
1008+void ETH_MACITConfig(uint32_t ETH_MAC_IT, FunctionalState NewState)
1009+{
1010+ /* Check the parameters */
1011+ assert_param(IS_ETH_MAC_IT(ETH_MAC_IT));
1012+ assert_param(IS_FUNCTIONAL_STATE(NewState));
1013+
1014+ if (NewState != DISABLE)
1015+ {
1016+ /* Enable the selected ETHERNET MAC interrupts */
1017+ ETH->MACIMR &= (~(uint32_t)ETH_MAC_IT);
1018+ }
1019+ else
1020+ {
1021+ /* Disable the selected ETHERNET MAC interrupts */
1022+ ETH->MACIMR |= ETH_MAC_IT;
1023+ }
1024+}
1025+
1026+/**
1027+ * @brief Configures the selected MAC address.
1028+ * @param MacAddr: The MAC addres to configure.
1029+ * This parameter can be one of the following values:
1030+ * @arg ETH_MAC_Address0 : MAC Address0
1031+ * @arg ETH_MAC_Address1 : MAC Address1
1032+ * @arg ETH_MAC_Address2 : MAC Address2
1033+ * @arg ETH_MAC_Address3 : MAC Address3
1034+ * @param Addr: Pointer on MAC address buffer data (6 bytes).
1035+ * @retval None
1036+ */
1037+void ETH_MACAddressConfig(uint32_t MacAddr, uint8_t *Addr)
1038+{
1039+ uint32_t tmpreg;
1040+ /* Check the parameters */
1041+ assert_param(IS_ETH_MAC_ADDRESS0123(MacAddr));
1042+
1043+ /* Calculate the selectecd MAC address high register */
1044+ tmpreg = ((uint32_t)Addr[5] << 8) | (uint32_t)Addr[4];
1045+ /* Load the selectecd MAC address high register */
1046+ (*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + MacAddr)) = tmpreg;
1047+ /* Calculate the selectecd MAC address low register */
1048+ tmpreg = ((uint32_t)Addr[3] << 24) | ((uint32_t)Addr[2] << 16) | ((uint32_t)Addr[1] << 8) | Addr[0];
1049+
1050+ /* Load the selectecd MAC address low register */
1051+ (*(__IO uint32_t *) (ETH_MAC_ADDR_LBASE + MacAddr)) = tmpreg;
1052+}
1053+
1054+/**
1055+ * @brief Get the selected MAC address.
1056+ * @param MacAddr: The MAC addres to return.
1057+ * This parameter can be one of the following values:
1058+ * @arg ETH_MAC_Address0 : MAC Address0
1059+ * @arg ETH_MAC_Address1 : MAC Address1
1060+ * @arg ETH_MAC_Address2 : MAC Address2
1061+ * @arg ETH_MAC_Address3 : MAC Address3
1062+ * @param Addr: Pointer on MAC address buffer data (6 bytes).
1063+ * @retval None
1064+ */
1065+void ETH_GetMACAddress(uint32_t MacAddr, uint8_t *Addr)
1066+{
1067+ uint32_t tmpreg;
1068+ /* Check the parameters */
1069+ assert_param(IS_ETH_MAC_ADDRESS0123(MacAddr));
1070+
1071+ /* Get the selectecd MAC address high register */
1072+ tmpreg =(*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + MacAddr));
1073+
1074+ /* Calculate the selectecd MAC address buffer */
1075+ Addr[5] = ((tmpreg >> 8) & (uint8_t)0xFF);
1076+ Addr[4] = (tmpreg & (uint8_t)0xFF);
1077+ /* Load the selectecd MAC address low register */
1078+ tmpreg =(*(__IO uint32_t *) (ETH_MAC_ADDR_LBASE + MacAddr));
1079+ /* Calculate the selectecd MAC address buffer */
1080+ Addr[3] = ((tmpreg >> 24) & (uint8_t)0xFF);
1081+ Addr[2] = ((tmpreg >> 16) & (uint8_t)0xFF);
1082+ Addr[1] = ((tmpreg >> 8 ) & (uint8_t)0xFF);
1083+ Addr[0] = (tmpreg & (uint8_t)0xFF);
1084+}
1085+
1086+/**
1087+ * @brief Enables or disables the Address filter module uses the specified
1088+ * ETHERNET MAC address for perfect filtering
1089+ * @param MacAddr: specifies the ETHERNET MAC address to be used for prfect filtering.
1090+ * This parameter can be one of the following values:
1091+ * @arg ETH_MAC_Address1 : MAC Address1
1092+ * @arg ETH_MAC_Address2 : MAC Address2
1093+ * @arg ETH_MAC_Address3 : MAC Address3
1094+ * @param NewState: new state of the specified ETHERNET MAC address use.
1095+ * This parameter can be: ENABLE or DISABLE.
1096+ * @retval None
1097+ */
1098+void ETH_MACAddressPerfectFilterCmd(uint32_t MacAddr, FunctionalState NewState)
1099+{
1100+ /* Check the parameters */
1101+ assert_param(IS_ETH_MAC_ADDRESS123(MacAddr));
1102+ assert_param(IS_FUNCTIONAL_STATE(NewState));
1103+
1104+ if (NewState != DISABLE)
1105+ {
1106+ /* Enable the selected ETHERNET MAC address for perfect filtering */
1107+ (*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + MacAddr)) |= ETH_MACA1HR_AE;
1108+ }
1109+ else
1110+ {
1111+ /* Disable the selected ETHERNET MAC address for perfect filtering */
1112+ (*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + MacAddr)) &=(~(uint32_t)ETH_MACA1HR_AE);
1113+ }
1114+}
1115+
1116+/**
1117+ * @brief Set the filter type for the specified ETHERNET MAC address
1118+ * @param MacAddr: specifies the ETHERNET MAC address
1119+ * This parameter can be one of the following values:
1120+ * @arg ETH_MAC_Address1 : MAC Address1
1121+ * @arg ETH_MAC_Address2 : MAC Address2
1122+ * @arg ETH_MAC_Address3 : MAC Address3
1123+ * @param Filter: specifies the used frame received field for comparaison
1124+ * This parameter can be one of the following values:
1125+ * @arg ETH_MAC_AddressFilter_SA : MAC Address is used to compare with the
1126+ * SA fields of the received frame.
1127+ * @arg ETH_MAC_AddressFilter_DA : MAC Address is used to compare with the
1128+ * DA fields of the received frame.
1129+ * @retval None
1130+ */
1131+void ETH_MACAddressFilterConfig(uint32_t MacAddr, uint32_t Filter)
1132+{
1133+ /* Check the parameters */
1134+ assert_param(IS_ETH_MAC_ADDRESS123(MacAddr));
1135+ assert_param(IS_ETH_MAC_ADDRESS_FILTER(Filter));
1136+
1137+ if (Filter != ETH_MAC_AddressFilter_DA)
1138+ {
1139+ /* The selected ETHERNET MAC address is used to compare with the SA fields of the
1140+ received frame. */
1141+ (*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + MacAddr)) |= ETH_MACA1HR_SA;
1142+ }
1143+ else
1144+ {
1145+ /* The selected ETHERNET MAC address is used to compare with the DA fields of the
1146+ received frame. */
1147+ (*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + MacAddr)) &=(~(uint32_t)ETH_MACA1HR_SA);
1148+ }
1149+}
1150+
1151+/**
1152+ * @brief Set the filter type for the specified ETHERNET MAC address
1153+ * @param MacAddr: specifies the ETHERNET MAC address
1154+ * This parameter can be one of the following values:
1155+ * @arg ETH_MAC_Address1 : MAC Address1
1156+ * @arg ETH_MAC_Address2 : MAC Address2
1157+ * @arg ETH_MAC_Address3 : MAC Address3
1158+ * @param MaskByte: specifies the used address bytes for comparaison
1159+ * This parameter can be any combination of the following values:
1160+ * @arg ETH_MAC_AddressMask_Byte6 : Mask MAC Address high reg bits [15:8].
1161+ * @arg ETH_MAC_AddressMask_Byte5 : Mask MAC Address high reg bits [7:0].
1162+ * @arg ETH_MAC_AddressMask_Byte4 : Mask MAC Address low reg bits [31:24].
1163+ * @arg ETH_MAC_AddressMask_Byte3 : Mask MAC Address low reg bits [23:16].
1164+ * @arg ETH_MAC_AddressMask_Byte2 : Mask MAC Address low reg bits [15:8].
1165+ * @arg ETH_MAC_AddressMask_Byte1 : Mask MAC Address low reg bits [7:0].
1166+ * @retval None
1167+ */
1168+void ETH_MACAddressMaskBytesFilterConfig(uint32_t MacAddr, uint32_t MaskByte)
1169+{
1170+ /* Check the parameters */
1171+ assert_param(IS_ETH_MAC_ADDRESS123(MacAddr));
1172+ assert_param(IS_ETH_MAC_ADDRESS_MASK(MaskByte));
1173+
1174+ /* Clear MBC bits in the selected MAC address high register */
1175+ (*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + MacAddr)) &=(~(uint32_t)ETH_MACA1HR_MBC);
1176+ /* Set the selected Filetr mask bytes */
1177+ (*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + MacAddr)) |= MaskByte;
1178+}
1179+/*------------------------ DMA Tx/Rx Desciptors -----------------------------*/
1180+
1181+/**
1182+ * @brief Initializes the DMA Tx descriptors in chain mode.
1183+ * @param DMATxDescTab: Pointer on the first Tx desc list
1184+ * @param TxBuff: Pointer on the first TxBuffer list
1185+ * @param TxBuffCount: Number of the used Tx desc in the list
1186+ * @retval None
1187+ */
1188+void ETH_DMATxDescChainInit(ETH_DMADESCTypeDef *DMATxDescTab, uint8_t* TxBuff, uint32_t TxBuffCount)
1189+{
1190+ uint32_t i = 0;
1191+ ETH_DMADESCTypeDef *DMATxDesc;
1192+
1193+ /* Set the DMATxDescToSet pointer with the first one of the DMATxDescTab list */
1194+ DMATxDescToSet = DMATxDescTab;
1195+ /* Fill each DMATxDesc descriptor with the right values */
1196+ for(i=0; i < TxBuffCount; i++)
1197+ {
1198+ /* Get the pointer on the ith member of the Tx Desc list */
1199+ DMATxDesc = DMATxDescTab + i;
1200+ /* Set Second Address Chained bit */
1201+ DMATxDesc->Status = ETH_DMATxDesc_TCH;
1202+
1203+ /* Set Buffer1 address pointer */
1204+ DMATxDesc->Buffer1Addr = (uint32_t)(&TxBuff[i*ETH_MAX_PACKET_SIZE]);
1205+
1206+ /* Initialize the next descriptor with the Next Desciptor Polling Enable */
1207+ if(i < (TxBuffCount-1))
1208+ {
1209+ /* Set next descriptor address register with next descriptor base address */
1210+ DMATxDesc->Buffer2NextDescAddr = (uint32_t)(DMATxDescTab+i+1);
1211+ }
1212+ else
1213+ {
1214+ /* For last descriptor, set next descriptor address register equal to the first descriptor base address */
1215+ DMATxDesc->Buffer2NextDescAddr = (uint32_t) DMATxDescTab;
1216+ }
1217+ }
1218+
1219+ /* Set Transmit Desciptor List Address Register */
1220+ ETH->DMATDLAR = (uint32_t) DMATxDescTab;
1221+}
1222+
1223+/**
1224+ * @brief Initializes the DMA Tx descriptors in ring mode.
1225+ * @param DMATxDescTab: Pointer on the first Tx desc list
1226+ * @param TxBuff1: Pointer on the first TxBuffer1 list
1227+ * @param TxBuff2: Pointer on the first TxBuffer2 list
1228+ * @param TxBuffCount: Number of the used Tx desc in the list
1229+ * Note: see decriptor skip length defined in ETH_DMA_InitStruct
1230+ * for the number of Words to skip between two unchained descriptors.
1231+ * @retval None
1232+ */
1233+void ETH_DMATxDescRingInit(ETH_DMADESCTypeDef *DMATxDescTab, uint8_t *TxBuff1, uint8_t *TxBuff2, uint32_t TxBuffCount)
1234+{
1235+ uint32_t i = 0;
1236+ ETH_DMADESCTypeDef *DMATxDesc;
1237+
1238+ /* Set the DMATxDescToSet pointer with the first one of the DMATxDescTab list */
1239+ DMATxDescToSet = DMATxDescTab;
1240+ /* Fill each DMATxDesc descriptor with the right values */
1241+ for(i=0; i < TxBuffCount; i++)
1242+ {
1243+ /* Get the pointer on the ith member of the Tx Desc list */
1244+ DMATxDesc = DMATxDescTab + i;
1245+ /* Set Buffer1 address pointer */
1246+ DMATxDesc->Buffer1Addr = (uint32_t)(&TxBuff1[i*ETH_MAX_PACKET_SIZE]);
1247+
1248+ /* Set Buffer2 address pointer */
1249+ DMATxDesc->Buffer2NextDescAddr = (uint32_t)(&TxBuff2[i*ETH_MAX_PACKET_SIZE]);
1250+
1251+ /* Set Transmit End of Ring bit for last descriptor: The DMA returns to the base
1252+ address of the list, creating a Desciptor Ring */
1253+ if(i == (TxBuffCount-1))
1254+ {
1255+ /* Set Transmit End of Ring bit */
1256+ DMATxDesc->Status = ETH_DMATxDesc_TER;
1257+ }
1258+ }
1259+
1260+ /* Set Transmit Desciptor List Address Register */
1261+ ETH->DMATDLAR = (uint32_t) DMATxDescTab;
1262+}
1263+
1264+/**
1265+ * @brief Checks whether the specified ETHERNET DMA Tx Desc flag is set or not.
1266+ * @param DMATxDesc: pointer on a DMA Tx descriptor
1267+ * @param ETH_DMATxDescFlag: specifies the flag to check.
1268+ * This parameter can be one of the following values:
1269+ * @arg ETH_DMATxDesc_OWN : OWN bit: descriptor is owned by DMA engine
1270+ * @arg ETH_DMATxDesc_IC : Interrupt on completetion
1271+ * @arg ETH_DMATxDesc_LS : Last Segment
1272+ * @arg ETH_DMATxDesc_FS : First Segment
1273+ * @arg ETH_DMATxDesc_DC : Disable CRC
1274+ * @arg ETH_DMATxDesc_DP : Disable Pad
1275+ * @arg ETH_DMATxDesc_TTSE: Transmit Time Stamp Enable
1276+ * @arg ETH_DMATxDesc_TER : Transmit End of Ring
1277+ * @arg ETH_DMATxDesc_TCH : Second Address Chained
1278+ * @arg ETH_DMATxDesc_TTSS: Tx Time Stamp Status
1279+ * @arg ETH_DMATxDesc_IHE : IP Header Error
1280+ * @arg ETH_DMATxDesc_ES : Error summary
1281+ * @arg ETH_DMATxDesc_JT : Jabber Timeout
1282+ * @arg ETH_DMATxDesc_FF : Frame Flushed: DMA/MTL flushed the frame due to SW flush
1283+ * @arg ETH_DMATxDesc_PCE : Payload Checksum Error
1284+ * @arg ETH_DMATxDesc_LCA : Loss of Carrier: carrier lost during tramsmission
1285+ * @arg ETH_DMATxDesc_NC : No Carrier: no carrier signal from the tranceiver
1286+ * @arg ETH_DMATxDesc_LCO : Late Collision: transmission aborted due to collision
1287+ * @arg ETH_DMATxDesc_EC : Excessive Collision: transmission aborted after 16 collisions
1288+ * @arg ETH_DMATxDesc_VF : VLAN Frame
1289+ * @arg ETH_DMATxDesc_CC : Collision Count
1290+ * @arg ETH_DMATxDesc_ED : Excessive Deferral
1291+ * @arg ETH_DMATxDesc_UF : Underflow Error: late data arrival from the memory
1292+ * @arg ETH_DMATxDesc_DB : Deferred Bit
1293+ * @retval The new state of ETH_DMATxDescFlag (SET or RESET).
1294+ */
1295+FlagStatus ETH_GetDMATxDescFlagStatus(ETH_DMADESCTypeDef *DMATxDesc, uint32_t ETH_DMATxDescFlag)
1296+{
1297+ FlagStatus bitstatus = RESET;
1298+ /* Check the parameters */
1299+ assert_param(IS_ETH_DMATxDESC_GET_FLAG(ETH_DMATxDescFlag));
1300+
1301+ if ((DMATxDesc->Status & ETH_DMATxDescFlag) != (uint32_t)RESET)
1302+ {
1303+ bitstatus = SET;
1304+ }
1305+ else
1306+ {
1307+ bitstatus = RESET;
1308+ }
1309+ return bitstatus;
1310+}
1311+
1312+/**
1313+ * @brief Returns the specified ETHERNET DMA Tx Desc collision count.
1314+ * @param DMATxDesc: pointer on a DMA Tx descriptor
1315+ * @retval The Transmit descriptor collision counter value.
1316+ */
1317+uint32_t ETH_GetDMATxDescCollisionCount(ETH_DMADESCTypeDef *DMATxDesc)
1318+{
1319+ /* Return the Receive descriptor frame length */
1320+ return ((DMATxDesc->Status & ETH_DMATxDesc_CC) >> ETH_DMATXDESC_COLLISION_COUNTSHIFT);
1321+}
1322+
1323+/**
1324+ * @brief Set the specified DMA Tx Desc Own bit.
1325+ * @param DMATxDesc: Pointer on a Tx desc
1326+ * @retval None
1327+ */
1328+void ETH_SetDMATxDescOwnBit(ETH_DMADESCTypeDef *DMATxDesc)
1329+{
1330+ /* Set the DMA Tx Desc Own bit */
1331+ DMATxDesc->Status |= ETH_DMATxDesc_OWN;
1332+}
1333+
1334+/**
1335+ * @brief Enables or disables the specified DMA Tx Desc Transmit interrupt.
1336+ * @param DMATxDesc: Pointer on a Tx desc
1337+ * @param NewState: new state of the DMA Tx Desc transmit interrupt.
1338+ * This parameter can be: ENABLE or DISABLE.
1339+ * @retval None
1340+ */
1341+void ETH_DMATxDescTransmitITConfig(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState)
1342+{
1343+ /* Check the parameters */
1344+ assert_param(IS_FUNCTIONAL_STATE(NewState));
1345+
1346+ if (NewState != DISABLE)
1347+ {
1348+ /* Enable the DMA Tx Desc Transmit interrupt */
1349+ DMATxDesc->Status |= ETH_DMATxDesc_IC;
1350+ }
1351+ else
1352+ {
1353+ /* Disable the DMA Tx Desc Transmit interrupt */
1354+ DMATxDesc->Status &=(~(uint32_t)ETH_DMATxDesc_IC);
1355+ }
1356+}
1357+
1358+/**
1359+ * @brief Enables or disables the specified DMA Tx Desc Transmit interrupt.
1360+ * @param DMATxDesc: Pointer on a Tx desc
1361+ * @param DMATxDesc_FrameSegment: specifies is the actual Tx desc contain last or first segment.
1362+ * This parameter can be one of the following values:
1363+ * @arg ETH_DMATxDesc_LastSegment : actual Tx desc contain last segment
1364+ * @arg ETH_DMATxDesc_FirstSegment : actual Tx desc contain first segment
1365+ * @retval None
1366+ */
1367+void ETH_DMATxDescFrameSegmentConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t DMATxDesc_FrameSegment)
1368+{
1369+ /* Check the parameters */
1370+ assert_param(IS_ETH_DMA_TXDESC_SEGMENT(DMATxDesc_FrameSegment));
1371+
1372+ /* Selects the DMA Tx Desc Frame segment */
1373+ DMATxDesc->Status |= DMATxDesc_FrameSegment;
1374+}
1375+
1376+/**
1377+ * @brief Selects the specified ETHERNET DMA Tx Desc Checksum Insertion.
1378+ * @param DMATxDesc: pointer on a DMA Tx descriptor
1379+ * @param DMATxDesc_Checksum: specifies is the DMA Tx desc checksum insertion.
1380+ * This parameter can be one of the following values:
1381+ * @arg ETH_DMATxDesc_ChecksumByPass : Checksum bypass
1382+ * @arg ETH_DMATxDesc_ChecksumIPV4Header : IPv4 header checksum
1383+ * @arg ETH_DMATxDesc_ChecksumTCPUDPICMPSegment : TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present
1384+ * @arg ETH_DMATxDesc_ChecksumTCPUDPICMPFull : TCP/UDP/ICMP checksum fully in hardware including pseudo header
1385+ * @retval None
1386+ */
1387+void ETH_DMATxDescChecksumInsertionConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t DMATxDesc_Checksum)
1388+{
1389+ /* Check the parameters */
1390+ assert_param(IS_ETH_DMA_TXDESC_CHECKSUM(DMATxDesc_Checksum));
1391+
1392+ /* Set the selected DMA Tx desc checksum insertion control */
1393+ DMATxDesc->Status |= DMATxDesc_Checksum;
1394+}
1395+
1396+/**
1397+ * @brief Enables or disables the DMA Tx Desc CRC.
1398+ * @param DMATxDesc: pointer on a DMA Tx descriptor
1399+ * @param NewState: new state of the specified DMA Tx Desc CRC.
1400+ * This parameter can be: ENABLE or DISABLE.
1401+ * @retval None
1402+ */
1403+void ETH_DMATxDescCRCCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState)
1404+{
1405+ /* Check the parameters */
1406+ assert_param(IS_FUNCTIONAL_STATE(NewState));
1407+
1408+ if (NewState != DISABLE)
1409+ {
1410+ /* Enable the selected DMA Tx Desc CRC */
1411+ DMATxDesc->Status &= (~(uint32_t)ETH_DMATxDesc_DC);
1412+ }
1413+ else
1414+ {
1415+ /* Disable the selected DMA Tx Desc CRC */
1416+ DMATxDesc->Status |= ETH_DMATxDesc_DC;
1417+ }
1418+}
1419+
1420+/**
1421+ * @brief Enables or disables the DMA Tx Desc end of ring.
1422+ * @param DMATxDesc: pointer on a DMA Tx descriptor
1423+ * @param NewState: new state of the specified DMA Tx Desc end of ring.
1424+ * This parameter can be: ENABLE or DISABLE.
1425+ * @retval None
1426+ */
1427+void ETH_DMATxDescEndOfRingCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState)
1428+{
1429+ /* Check the parameters */
1430+ assert_param(IS_FUNCTIONAL_STATE(NewState));
1431+
1432+ if (NewState != DISABLE)
1433+ {
1434+ /* Enable the selected DMA Tx Desc end of ring */
1435+ DMATxDesc->Status |= ETH_DMATxDesc_TER;
1436+ }
1437+ else
1438+ {
1439+ /* Disable the selected DMA Tx Desc end of ring */
1440+ DMATxDesc->Status &= (~(uint32_t)ETH_DMATxDesc_TER);
1441+ }
1442+}
1443+
1444+/**
1445+ * @brief Enables or disables the DMA Tx Desc second address chained.
1446+ * @param DMATxDesc: pointer on a DMA Tx descriptor
1447+ * @param NewState: new state of the specified DMA Tx Desc second address chained.
1448+ * This parameter can be: ENABLE or DISABLE.
1449+ * @retval None
1450+ */
1451+void ETH_DMATxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState)
1452+{
1453+ /* Check the parameters */
1454+ assert_param(IS_FUNCTIONAL_STATE(NewState));
1455+
1456+ if (NewState != DISABLE)
1457+ {
1458+ /* Enable the selected DMA Tx Desc second address chained */
1459+ DMATxDesc->Status |= ETH_DMATxDesc_TCH;
1460+ }
1461+ else
1462+ {
1463+ /* Disable the selected DMA Tx Desc second address chained */
1464+ DMATxDesc->Status &=(~(uint32_t)ETH_DMATxDesc_TCH);
1465+ }
1466+}
1467+
1468+/**
1469+ * @brief Enables or disables the DMA Tx Desc padding for frame shorter than 64 bytes.
1470+ * @param DMATxDesc: pointer on a DMA Tx descriptor
1471+ * @param NewState: new state of the specified DMA Tx Desc padding for frame shorter than 64 bytes.
1472+ * This parameter can be: ENABLE or DISABLE.
1473+ * @retval None
1474+ */
1475+void ETH_DMATxDescShortFramePaddingCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState)
1476+{
1477+ /* Check the parameters */
1478+ assert_param(IS_FUNCTIONAL_STATE(NewState));
1479+
1480+ if (NewState != DISABLE)
1481+ {
1482+ /* Enable the selected DMA Tx Desc padding for frame shorter than 64 bytes */
1483+ DMATxDesc->Status &= (~(uint32_t)ETH_DMATxDesc_DP);
1484+ }
1485+ else
1486+ {
1487+ /* Disable the selected DMA Tx Desc padding for frame shorter than 64 bytes*/
1488+ DMATxDesc->Status |= ETH_DMATxDesc_DP;
1489+ }
1490+}
1491+
1492+/**
1493+ * @brief Enables or disables the DMA Tx Desc time stamp.
1494+ * @param DMATxDesc: pointer on a DMA Tx descriptor
1495+ * @param NewState: new state of the specified DMA Tx Desc time stamp.
1496+ * This parameter can be: ENABLE or DISABLE.
1497+ * @retval None
1498+ */
1499+void ETH_DMATxDescTimeStampCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState)
1500+{
1501+ /* Check the parameters */
1502+ assert_param(IS_FUNCTIONAL_STATE(NewState));
1503+
1504+ if (NewState != DISABLE)
1505+ {
1506+ /* Enable the selected DMA Tx Desc time stamp */
1507+ DMATxDesc->Status |= ETH_DMATxDesc_TTSE;
1508+ }
1509+ else
1510+ {
1511+ /* Disable the selected DMA Tx Desc time stamp */
1512+ DMATxDesc->Status &=(~(uint32_t)ETH_DMATxDesc_TTSE);
1513+ }
1514+}
1515+
1516+/**
1517+ * @brief Configures the specified DMA Tx Desc buffer1 and buffer2 sizes.
1518+ * @param DMATxDesc: Pointer on a Tx desc
1519+ * @param BufferSize1: specifies the Tx desc buffer1 size.
1520+ * @param BufferSize2: specifies the Tx desc buffer2 size (put "0" if not used).
1521+ * @retval None
1522+ */
1523+void ETH_DMATxDescBufferSizeConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t BufferSize1, uint32_t BufferSize2)
1524+{
1525+ /* Check the parameters */
1526+ assert_param(IS_ETH_DMATxDESC_BUFFER_SIZE(BufferSize1));
1527+ assert_param(IS_ETH_DMATxDESC_BUFFER_SIZE(BufferSize2));
1528+
1529+ /* Set the DMA Tx Desc buffer1 and buffer2 sizes values */
1530+ DMATxDesc->ControlBufferSize |= (BufferSize1 | (BufferSize2 << ETH_DMATXDESC_BUFFER2_SIZESHIFT));
1531+}
1532+
1533+/**
1534+ * @brief Initializes the DMA Rx descriptors in chain mode.
1535+ * @param DMARxDescTab: Pointer on the first Rx desc list
1536+ * @param RxBuff: Pointer on the first RxBuffer list
1537+ * @param RxBuffCount: Number of the used Rx desc in the list
1538+ * @retval None
1539+ */
1540+void ETH_DMARxDescChainInit(ETH_DMADESCTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount)
1541+{
1542+ uint32_t i = 0;
1543+ ETH_DMADESCTypeDef *DMARxDesc;
1544+
1545+ /* Set the DMARxDescToGet pointer with the first one of the DMARxDescTab list */
1546+ DMARxDescToGet = DMARxDescTab;
1547+ /* Fill each DMARxDesc descriptor with the right values */
1548+ for(i=0; i < RxBuffCount; i++)
1549+ {
1550+ /* Get the pointer on the ith member of the Rx Desc list */
1551+ DMARxDesc = DMARxDescTab+i;
1552+ /* Set Own bit of the Rx descriptor Status */
1553+ DMARxDesc->Status = ETH_DMARxDesc_OWN;
1554+
1555+ /* Set Buffer1 size and Second Address Chained bit */
1556+ DMARxDesc->ControlBufferSize = ETH_DMARxDesc_RCH | (uint32_t)ETH_MAX_PACKET_SIZE;
1557+ /* Set Buffer1 address pointer */
1558+ DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff[i*ETH_MAX_PACKET_SIZE]);
1559+
1560+ /* Initialize the next descriptor with the Next Desciptor Polling Enable */
1561+ if(i < (RxBuffCount-1))
1562+ {
1563+ /* Set next descriptor address register with next descriptor base address */
1564+ DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab+i+1);
1565+ }
1566+ else
1567+ {
1568+ /* For last descriptor, set next descriptor address register equal to the first descriptor base address */
1569+ DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab);
1570+ }
1571+ }
1572+
1573+ /* Set Receive Desciptor List Address Register */
1574+ ETH->DMARDLAR = (uint32_t) DMARxDescTab;
1575+}
1576+
1577+/**
1578+ * @brief Initializes the DMA Rx descriptors in ring mode.
1579+ * @param DMARxDescTab: Pointer on the first Rx desc list
1580+ * @param RxBuff1: Pointer on the first RxBuffer1 list
1581+ * @param RxBuff2: Pointer on the first RxBuffer2 list
1582+ * @param RxBuffCount: Number of the used Rx desc in the list
1583+ * Note: see decriptor skip length defined in ETH_DMA_InitStruct
1584+ * for the number of Words to skip between two unchained descriptors.
1585+ * @retval None
1586+ */
1587+void ETH_DMARxDescRingInit(ETH_DMADESCTypeDef *DMARxDescTab, uint8_t *RxBuff1, uint8_t *RxBuff2, uint32_t RxBuffCount)
1588+{
1589+ uint32_t i = 0;
1590+ ETH_DMADESCTypeDef *DMARxDesc;
1591+ /* Set the DMARxDescToGet pointer with the first one of the DMARxDescTab list */
1592+ DMARxDescToGet = DMARxDescTab;
1593+ /* Fill each DMARxDesc descriptor with the right values */
1594+ for(i=0; i < RxBuffCount; i++)
1595+ {
1596+ /* Get the pointer on the ith member of the Rx Desc list */
1597+ DMARxDesc = DMARxDescTab+i;
1598+ /* Set Own bit of the Rx descriptor Status */
1599+ DMARxDesc->Status = ETH_DMARxDesc_OWN;
1600+ /* Set Buffer1 size */
1601+ DMARxDesc->ControlBufferSize = ETH_MAX_PACKET_SIZE;
1602+ /* Set Buffer1 address pointer */
1603+ DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff1[i*ETH_MAX_PACKET_SIZE]);
1604+
1605+ /* Set Buffer2 address pointer */
1606+ DMARxDesc->Buffer2NextDescAddr = (uint32_t)(&RxBuff2[i*ETH_MAX_PACKET_SIZE]);
1607+
1608+ /* Set Receive End of Ring bit for last descriptor: The DMA returns to the base
1609+ address of the list, creating a Desciptor Ring */
1610+ if(i == (RxBuffCount-1))
1611+ {
1612+ /* Set Receive End of Ring bit */
1613+ DMARxDesc->ControlBufferSize |= ETH_DMARxDesc_RER;
1614+ }
1615+ }
1616+
1617+ /* Set Receive Desciptor List Address Register */
1618+ ETH->DMARDLAR = (uint32_t) DMARxDescTab;
1619+}
1620+
1621+/**
1622+ * @brief Checks whether the specified ETHERNET Rx Desc flag is set or not.
1623+ * @param DMARxDesc: pointer on a DMA Rx descriptor
1624+ * @param ETH_DMARxDescFlag: specifies the flag to check.
1625+ * This parameter can be one of the following values:
1626+ * @arg ETH_DMARxDesc_OWN: OWN bit: descriptor is owned by DMA engine
1627+ * @arg ETH_DMARxDesc_AFM: DA Filter Fail for the rx frame
1628+ * @arg ETH_DMARxDesc_ES: Error summary
1629+ * @arg ETH_DMARxDesc_DE: Desciptor error: no more descriptors for receive frame
1630+ * @arg ETH_DMARxDesc_SAF: SA Filter Fail for the received frame
1631+ * @arg ETH_DMARxDesc_LE: Frame size not matching with length field
1632+ * @arg ETH_DMARxDesc_OE: Overflow Error: Frame was damaged due to buffer overflow
1633+ * @arg ETH_DMARxDesc_VLAN: VLAN Tag: received frame is a VLAN frame
1634+ * @arg ETH_DMARxDesc_FS: First descriptor of the frame
1635+ * @arg ETH_DMARxDesc_LS: Last descriptor of the frame
1636+ * @arg ETH_DMARxDesc_IPV4HCE: IPC Checksum Error/Giant Frame: Rx Ipv4 header checksum error
1637+ * @arg ETH_DMARxDesc_LC: Late collision occurred during reception
1638+ * @arg ETH_DMARxDesc_FT: Frame type - Ethernet, otherwise 802.3
1639+ * @arg ETH_DMARxDesc_RWT: Receive Watchdog Timeout: watchdog timer expired during reception
1640+ * @arg ETH_DMARxDesc_RE: Receive error: error reported by MII interface
1641+ * @arg ETH_DMARxDesc_DE: Dribble bit error: frame contains non int multiple of 8 bits
1642+ * @arg ETH_DMARxDesc_CE: CRC error
1643+ * @arg ETH_DMARxDesc_MAMPCE: Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error
1644+ * @retval The new state of ETH_DMARxDescFlag (SET or RESET).
1645+ */
1646+FlagStatus ETH_GetDMARxDescFlagStatus(ETH_DMADESCTypeDef *DMARxDesc, uint32_t ETH_DMARxDescFlag)
1647+{
1648+ FlagStatus bitstatus = RESET;
1649+ /* Check the parameters */
1650+ assert_param(IS_ETH_DMARxDESC_GET_FLAG(ETH_DMARxDescFlag));
1651+ if ((DMARxDesc->Status & ETH_DMARxDescFlag) != (uint32_t)RESET)
1652+ {
1653+ bitstatus = SET;
1654+ }
1655+ else
1656+ {
1657+ bitstatus = RESET;
1658+ }
1659+ return bitstatus;
1660+}
1661+
1662+/**
1663+ * @brief Set the specified DMA Rx Desc Own bit.
1664+ * @param DMARxDesc: Pointer on a Rx desc
1665+ * @retval None
1666+ */
1667+void ETH_SetDMARxDescOwnBit(ETH_DMADESCTypeDef *DMARxDesc)
1668+{
1669+ /* Set the DMA Rx Desc Own bit */
1670+ DMARxDesc->Status |= ETH_DMARxDesc_OWN;
1671+}
1672+
1673+/**
1674+ * @brief Returns the specified DMA Rx Desc frame length.
1675+ * @param DMARxDesc: pointer on a DMA Rx descriptor
1676+ * @retval The Rx descriptor received frame length.
1677+ */
1678+uint32_t ETH_GetDMARxDescFrameLength(ETH_DMADESCTypeDef *DMARxDesc)
1679+{
1680+ /* Return the Receive descriptor frame length */
1681+ return ((DMARxDesc->Status & ETH_DMARxDesc_FL) >> ETH_DMARXDESC_FRAME_LENGTHSHIFT);
1682+}
1683+
1684+/**
1685+ * @brief Enables or disables the specified DMA Rx Desc receive interrupt.
1686+ * @param DMARxDesc: Pointer on a Rx desc
1687+ * @param NewState: new state of the specified DMA Rx Desc interrupt.
1688+ * This parameter can be: ENABLE or DISABLE.
1689+ * @retval None
1690+ */
1691+void ETH_DMARxDescReceiveITConfig(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState)
1692+{
1693+ /* Check the parameters */
1694+ assert_param(IS_FUNCTIONAL_STATE(NewState));
1695+
1696+ if (NewState != DISABLE)
1697+ {
1698+ /* Enable the DMA Rx Desc receive interrupt */
1699+ DMARxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARxDesc_DIC);
1700+ }
1701+ else
1702+ {
1703+ /* Disable the DMA Rx Desc receive interrupt */
1704+ DMARxDesc->ControlBufferSize |= ETH_DMARxDesc_DIC;
1705+ }
1706+}
1707+
1708+/**
1709+ * @brief Enables or disables the DMA Rx Desc end of ring.
1710+ * @param DMARxDesc: pointer on a DMA Rx descriptor
1711+ * @param NewState: new state of the specified DMA Rx Desc end of ring.
1712+ * This parameter can be: ENABLE or DISABLE.
1713+ * @retval None
1714+ */
1715+void ETH_DMARxDescEndOfRingCmd(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState)
1716+{
1717+ /* Check the parameters */
1718+ assert_param(IS_FUNCTIONAL_STATE(NewState));
1719+
1720+ if (NewState != DISABLE)
1721+ {
1722+ /* Enable the selected DMA Rx Desc end of ring */
1723+ DMARxDesc->ControlBufferSize |= ETH_DMARxDesc_RER;
1724+ }
1725+ else
1726+ {
1727+ /* Disable the selected DMA Rx Desc end of ring */
1728+ DMARxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARxDesc_RER);
1729+ }
1730+}
1731+
1732+/**
1733+ * @brief Enables or disables the DMA Rx Desc second address chained.
1734+ * @param DMARxDesc: pointer on a DMA Rx descriptor
1735+ * @param NewState: new state of the specified DMA Rx Desc second address chained.
1736+ * This parameter can be: ENABLE or DISABLE.
1737+ * @retval None
1738+ */
1739+void ETH_DMARxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState)
1740+{
1741+ /* Check the parameters */
1742+ assert_param(IS_FUNCTIONAL_STATE(NewState));
1743+
1744+ if (NewState != DISABLE)
1745+ {
1746+ /* Enable the selected DMA Rx Desc second address chained */
1747+ DMARxDesc->ControlBufferSize |= ETH_DMARxDesc_RCH;
1748+ }
1749+ else
1750+ {
1751+ /* Disable the selected DMA Rx Desc second address chained */
1752+ DMARxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARxDesc_RCH);
1753+ }
1754+}
1755+
1756+/**
1757+ * @brief Returns the specified ETHERNET DMA Rx Desc buffer size.
1758+ * @param DMARxDesc: pointer on a DMA Rx descriptor
1759+ * @param DMARxDesc_Buffer: specifies the DMA Rx Desc buffer.
1760+ * This parameter can be any one of the following values:
1761+ * @arg ETH_DMARxDesc_Buffer1 : DMA Rx Desc Buffer1
1762+ * @arg ETH_DMARxDesc_Buffer2 : DMA Rx Desc Buffer2
1763+ * @retval The Receive descriptor frame length.
1764+ */
1765+uint32_t ETH_GetDMARxDescBufferSize(ETH_DMADESCTypeDef *DMARxDesc, uint32_t DMARxDesc_Buffer)
1766+{
1767+ /* Check the parameters */
1768+ assert_param(IS_ETH_DMA_RXDESC_BUFFER(DMARxDesc_Buffer));
1769+
1770+ if(DMARxDesc_Buffer != ETH_DMARxDesc_Buffer1)
1771+ {
1772+ /* Return the DMA Rx Desc buffer2 size */
1773+ return ((DMARxDesc->ControlBufferSize & ETH_DMARxDesc_RBS2) >> ETH_DMARXDESC_BUFFER2_SIZESHIFT);
1774+ }
1775+ else
1776+ {
1777+ /* Return the DMA Rx Desc buffer1 size */
1778+ return (DMARxDesc->ControlBufferSize & ETH_DMARxDesc_RBS1);
1779+ }
1780+}
1781+
1782+/*--------------------------------- DMA ------------------------------------*/
1783+/**
1784+ * @brief Resets all MAC subsystem internal registers and logic.
1785+ * @param None
1786+ * @retval None
1787+ */
1788+void ETH_SoftwareReset(void)
1789+{
1790+ /* Set the SWR bit: resets all MAC subsystem internal registers and logic */
1791+ /* After reset all the registers holds their respective reset values */
1792+ ETH->DMABMR |= ETH_DMABMR_SR;
1793+}
1794+
1795+/**
1796+ * @brief Checks whether the ETHERNET software reset bit is set or not.
1797+ * @param None
1798+ * @retval The new state of DMA Bus Mode register SR bit (SET or RESET).
1799+ */
1800+FlagStatus ETH_GetSoftwareResetStatus(void)
1801+{
1802+ FlagStatus bitstatus = RESET;
1803+ if((ETH->DMABMR & ETH_DMABMR_SR) != (uint32_t)RESET)
1804+ {
1805+ bitstatus = SET;
1806+ }
1807+ else
1808+ {
1809+ bitstatus = RESET;
1810+ }
1811+ return bitstatus;
1812+}
1813+
1814+/**
1815+ * @brief Checks whether the specified ETHERNET DMA flag is set or not.
1816+ * @param ETH_DMA_FLAG: specifies the flag to check.
1817+ * This parameter can be one of the following values:
1818+ * @arg ETH_DMA_FLAG_TST : Time-stamp trigger flag
1819+ * @arg ETH_DMA_FLAG_PMT : PMT flag
1820+ * @arg ETH_DMA_FLAG_MMC : MMC flag
1821+ * @arg ETH_DMA_FLAG_DataTransferError : Error bits 0-data buffer, 1-desc. access
1822+ * @arg ETH_DMA_FLAG_ReadWriteError : Error bits 0-write trnsf, 1-read transfr
1823+ * @arg ETH_DMA_FLAG_AccessError : Error bits 0-Rx DMA, 1-Tx DMA
1824+ * @arg ETH_DMA_FLAG_NIS : Normal interrupt summary flag
1825+ * @arg ETH_DMA_FLAG_AIS : Abnormal interrupt summary flag
1826+ * @arg ETH_DMA_FLAG_ER : Early receive flag
1827+ * @arg ETH_DMA_FLAG_FBE : Fatal bus error flag
1828+ * @arg ETH_DMA_FLAG_ET : Early transmit flag
1829+ * @arg ETH_DMA_FLAG_RWT : Receive watchdog timeout flag
1830+ * @arg ETH_DMA_FLAG_RPS : Receive process stopped flag
1831+ * @arg ETH_DMA_FLAG_RBU : Receive buffer unavailable flag
1832+ * @arg ETH_DMA_FLAG_R : Receive flag
1833+ * @arg ETH_DMA_FLAG_TU : Underflow flag
1834+ * @arg ETH_DMA_FLAG_RO : Overflow flag
1835+ * @arg ETH_DMA_FLAG_TJT : Transmit jabber timeout flag
1836+ * @arg ETH_DMA_FLAG_TBU : Transmit buffer unavailable flag
1837+ * @arg ETH_DMA_FLAG_TPS : Transmit process stopped flag
1838+ * @arg ETH_DMA_FLAG_T : Transmit flag
1839+ * @retval The new state of ETH_DMA_FLAG (SET or RESET).
1840+ */
1841+FlagStatus ETH_GetDMAFlagStatus(uint32_t ETH_DMA_FLAG)
1842+{
1843+ FlagStatus bitstatus = RESET;
1844+ /* Check the parameters */
1845+ assert_param(IS_ETH_DMA_GET_IT(ETH_DMA_FLAG));
1846+ if ((ETH->DMASR & ETH_DMA_FLAG) != (uint32_t)RESET)
1847+ {
1848+ bitstatus = SET;
1849+ }
1850+ else
1851+ {
1852+ bitstatus = RESET;
1853+ }
1854+ return bitstatus;
1855+}
1856+
1857+/**
1858+ * @brief Clears the ETHERNET’s DMA pending flag.
1859+ * @param ETH_DMA_FLAG: specifies the flag to clear.
1860+ * This parameter can be any combination of the following values:
1861+ * @arg ETH_DMA_FLAG_NIS : Normal interrupt summary flag
1862+ * @arg ETH_DMA_FLAG_AIS : Abnormal interrupt summary flag
1863+ * @arg ETH_DMA_FLAG_ER : Early receive flag
1864+ * @arg ETH_DMA_FLAG_FBE : Fatal bus error flag
1865+ * @arg ETH_DMA_FLAG_ETI : Early transmit flag
1866+ * @arg ETH_DMA_FLAG_RWT : Receive watchdog timeout flag
1867+ * @arg ETH_DMA_FLAG_RPS : Receive process stopped flag
1868+ * @arg ETH_DMA_FLAG_RBU : Receive buffer unavailable flag
1869+ * @arg ETH_DMA_FLAG_R : Receive flag
1870+ * @arg ETH_DMA_FLAG_TU : Transmit Underflow flag
1871+ * @arg ETH_DMA_FLAG_RO : Receive Overflow flag
1872+ * @arg ETH_DMA_FLAG_TJT : Transmit jabber timeout flag
1873+ * @arg ETH_DMA_FLAG_TBU : Transmit buffer unavailable flag
1874+ * @arg ETH_DMA_FLAG_TPS : Transmit process stopped flag
1875+ * @arg ETH_DMA_FLAG_T : Transmit flag
1876+ * @retval None
1877+ */
1878+void ETH_DMAClearFlag(uint32_t ETH_DMA_FLAG)
1879+{
1880+ /* Check the parameters */
1881+ assert_param(IS_ETH_DMA_FLAG(ETH_DMA_FLAG));
1882+
1883+ /* Clear the selected ETHERNET DMA FLAG */
1884+ ETH->DMASR = (uint32_t) ETH_DMA_FLAG;
1885+}
1886+
1887+/**
1888+ * @brief Checks whether the specified ETHERNET DMA interrupt has occured or not.
1889+ * @param ETH_DMA_IT: specifies the interrupt source to check.
1890+ * This parameter can be one of the following values:
1891+ * @arg ETH_DMA_IT_TST : Time-stamp trigger interrupt
1892+ * @arg ETH_DMA_IT_PMT : PMT interrupt
1893+ * @arg ETH_DMA_IT_MMC : MMC interrupt
1894+ * @arg ETH_DMA_IT_NIS : Normal interrupt summary
1895+ * @arg ETH_DMA_IT_AIS : Abnormal interrupt summary
1896+ * @arg ETH_DMA_IT_ER : Early receive interrupt
1897+ * @arg ETH_DMA_IT_FBE : Fatal bus error interrupt
1898+ * @arg ETH_DMA_IT_ET : Early transmit interrupt
1899+ * @arg ETH_DMA_IT_RWT : Receive watchdog timeout interrupt
1900+ * @arg ETH_DMA_IT_RPS : Receive process stopped interrupt
1901+ * @arg ETH_DMA_IT_RBU : Receive buffer unavailable interrupt
1902+ * @arg ETH_DMA_IT_R : Receive interrupt
1903+ * @arg ETH_DMA_IT_TU : Underflow interrupt
1904+ * @arg ETH_DMA_IT_RO : Overflow interrupt
1905+ * @arg ETH_DMA_IT_TJT : Transmit jabber timeout interrupt
1906+ * @arg ETH_DMA_IT_TBU : Transmit buffer unavailable interrupt
1907+ * @arg ETH_DMA_IT_TPS : Transmit process stopped interrupt
1908+ * @arg ETH_DMA_IT_T : Transmit interrupt
1909+ * @retval The new state of ETH_DMA_IT (SET or RESET).
1910+ */
1911+ITStatus ETH_GetDMAITStatus(uint32_t ETH_DMA_IT)
1912+{
1913+ ITStatus bitstatus = RESET;
1914+ /* Check the parameters */
1915+ assert_param(IS_ETH_DMA_GET_IT(ETH_DMA_IT));
1916+ if ((ETH->DMASR & ETH_DMA_IT) != (uint32_t)RESET)
1917+ {
1918+ bitstatus = SET;
1919+ }
1920+ else
1921+ {
1922+ bitstatus = RESET;
1923+ }
1924+ return bitstatus;
1925+}
1926+
1927+/**
1928+ * @brief Clears the ETHERNET’s DMA IT pending bit.
1929+ * @param ETH_DMA_IT: specifies the interrupt pending bit to clear.
1930+ * This parameter can be any combination of the following values:
1931+ * @arg ETH_DMA_IT_NIS : Normal interrupt summary
1932+ * @arg ETH_DMA_IT_AIS : Abnormal interrupt summary
1933+ * @arg ETH_DMA_IT_ER : Early receive interrupt
1934+ * @arg ETH_DMA_IT_FBE : Fatal bus error interrupt
1935+ * @arg ETH_DMA_IT_ETI : Early transmit interrupt
1936+ * @arg ETH_DMA_IT_RWT : Receive watchdog timeout interrupt
1937+ * @arg ETH_DMA_IT_RPS : Receive process stopped interrupt
1938+ * @arg ETH_DMA_IT_RBU : Receive buffer unavailable interrupt
1939+ * @arg ETH_DMA_IT_R : Receive interrupt
1940+ * @arg ETH_DMA_IT_TU : Transmit Underflow interrupt
1941+ * @arg ETH_DMA_IT_RO : Receive Overflow interrupt
1942+ * @arg ETH_DMA_IT_TJT : Transmit jabber timeout interrupt
1943+ * @arg ETH_DMA_IT_TBU : Transmit buffer unavailable interrupt
1944+ * @arg ETH_DMA_IT_TPS : Transmit process stopped interrupt
1945+ * @arg ETH_DMA_IT_T : Transmit interrupt
1946+ * @retval None
1947+ */
1948+void ETH_DMAClearITPendingBit(uint32_t ETH_DMA_IT)
1949+{
1950+ /* Check the parameters */
1951+ assert_param(IS_ETH_DMA_IT(ETH_DMA_IT));
1952+
1953+ /* Clear the selected ETHERNET DMA IT */
1954+ ETH->DMASR = (uint32_t) ETH_DMA_IT;
1955+}
1956+
1957+/**
1958+ * @brief Returns the ETHERNET DMA Transmit Process State.
1959+ * @param None
1960+ * @retval The new ETHERNET DMA Transmit Process State:
1961+ * This can be one of the following values:
1962+ * - ETH_DMA_TransmitProcess_Stopped : Stopped - Reset or Stop Tx Command issued
1963+ * - ETH_DMA_TransmitProcess_Fetching : Running - fetching the Tx descriptor
1964+ * - ETH_DMA_TransmitProcess_Waiting : Running - waiting for status
1965+ * - ETH_DMA_TransmitProcess_Reading : unning - reading the data from host memory
1966+ * - ETH_DMA_TransmitProcess_Suspended : Suspended - Tx Desciptor unavailabe
1967+ * - ETH_DMA_TransmitProcess_Closing : Running - closing Rx descriptor
1968+ */
1969+uint32_t ETH_GetTransmitProcessState(void)
1970+{
1971+ return ((uint32_t)(ETH->DMASR & ETH_DMASR_TS));
1972+}
1973+
1974+/**
1975+ * @brief Returns the ETHERNET DMA Receive Process State.
1976+ * @param None
1977+ * @retval The new ETHERNET DMA Receive Process State:
1978+ * This can be one of the following values:
1979+ * - ETH_DMA_ReceiveProcess_Stopped : Stopped - Reset or Stop Rx Command issued
1980+ * - ETH_DMA_ReceiveProcess_Fetching : Running - fetching the Rx descriptor
1981+ * - ETH_DMA_ReceiveProcess_Waiting : Running - waiting for packet
1982+ * - ETH_DMA_ReceiveProcess_Suspended : Suspended - Rx Desciptor unavailable
1983+ * - ETH_DMA_ReceiveProcess_Closing : Running - closing descriptor
1984+ * - ETH_DMA_ReceiveProcess_Queuing : Running - queuing the recieve frame into host memory
1985+ */
1986+uint32_t ETH_GetReceiveProcessState(void)
1987+{
1988+ return ((uint32_t)(ETH->DMASR & ETH_DMASR_RS));
1989+}
1990+
1991+/**
1992+ * @brief Clears the ETHERNET transmit FIFO.
1993+ * @param None
1994+ * @retval None
1995+ */
1996+void ETH_FlushTransmitFIFO(void)
1997+{
1998+ /* Set the Flush Transmit FIFO bit */
1999+ ETH->DMAOMR |= ETH_DMAOMR_FTF;
2000+}
2001+
2002+/**
2003+ * @brief Checks whether the ETHERNET transmit FIFO bit is cleared or not.
2004+ * @param None
2005+ * @retval The new state of ETHERNET flush transmit FIFO bit (SET or RESET).
2006+ */
2007+FlagStatus ETH_GetFlushTransmitFIFOStatus(void)
2008+{
2009+ FlagStatus bitstatus = RESET;
2010+ if ((ETH->DMAOMR & ETH_DMAOMR_FTF) != (uint32_t)RESET)
2011+ {
2012+ bitstatus = SET;
2013+ }
2014+ else
2015+ {
2016+ bitstatus = RESET;
2017+ }
2018+ return bitstatus;
2019+}
2020+
2021+/**
2022+ * @brief Enables or disables the DMA transmission.
2023+ * @param NewState: new state of the DMA transmission.
2024+ * This parameter can be: ENABLE or DISABLE.
2025+ * @retval None
2026+ */
2027+void ETH_DMATransmissionCmd(FunctionalState NewState)
2028+{
2029+ /* Check the parameters */
2030+ assert_param(IS_FUNCTIONAL_STATE(NewState));
2031+
2032+ if (NewState != DISABLE)
2033+ {
2034+ /* Enable the DMA transmission */
2035+ ETH->DMAOMR |= ETH_DMAOMR_ST;
2036+ }
2037+ else
2038+ {
2039+ /* Disable the DMA transmission */
2040+ ETH->DMAOMR &= ~ETH_DMAOMR_ST;
2041+ }
2042+}
2043+
2044+/**
2045+ * @brief Enables or disables the DMA reception.
2046+ * @param NewState: new state of the DMA reception.
2047+ * This parameter can be: ENABLE or DISABLE.
2048+ * @retval None
2049+ */
2050+void ETH_DMAReceptionCmd(FunctionalState NewState)
2051+{
2052+ /* Check the parameters */
2053+ assert_param(IS_FUNCTIONAL_STATE(NewState));
2054+
2055+ if (NewState != DISABLE)
2056+ {
2057+ /* Enable the DMA reception */
2058+ ETH->DMAOMR |= ETH_DMAOMR_SR;
2059+ }
2060+ else
2061+ {
2062+ /* Disable the DMA reception */
2063+ ETH->DMAOMR &= ~ETH_DMAOMR_SR;
2064+ }
2065+}
2066+
2067+/**
2068+ * @brief Enables or disables the specified ETHERNET DMA interrupts.
2069+ * @param ETH_DMA_IT: specifies the ETHERNET DMA interrupt sources to be
2070+ * enabled or disabled.
2071+ * This parameter can be any combination of the following values:
2072+ * @arg ETH_DMA_IT_NIS : Normal interrupt summary
2073+ * @arg ETH_DMA_IT_AIS : Abnormal interrupt summary
2074+ * @arg ETH_DMA_IT_ER : Early receive interrupt
2075+ * @arg ETH_DMA_IT_FBE : Fatal bus error interrupt
2076+ * @arg ETH_DMA_IT_ET : Early transmit interrupt
2077+ * @arg ETH_DMA_IT_RWT : Receive watchdog timeout interrupt
2078+ * @arg ETH_DMA_IT_RPS : Receive process stopped interrupt
2079+ * @arg ETH_DMA_IT_RBU : Receive buffer unavailable interrupt
2080+ * @arg ETH_DMA_IT_R : Receive interrupt
2081+ * @arg ETH_DMA_IT_TU : Underflow interrupt
2082+ * @arg ETH_DMA_IT_RO : Overflow interrupt
2083+ * @arg ETH_DMA_IT_TJT : Transmit jabber timeout interrupt
2084+ * @arg ETH_DMA_IT_TBU : Transmit buffer unavailable interrupt
2085+ * @arg ETH_DMA_IT_TPS : Transmit process stopped interrupt
2086+ * @arg ETH_DMA_IT_T : Transmit interrupt
2087+ * @param NewState: new state of the specified ETHERNET DMA interrupts.
2088+ * This parameter can be: ENABLE or DISABLE.
2089+ * @retval None
2090+ */
2091+void ETH_DMAITConfig(uint32_t ETH_DMA_IT, FunctionalState NewState)
2092+{
2093+ /* Check the parameters */
2094+ assert_param(IS_ETH_DMA_IT(ETH_DMA_IT));
2095+ assert_param(IS_FUNCTIONAL_STATE(NewState));
2096+
2097+ if (NewState != DISABLE)
2098+ {
2099+ /* Enable the selected ETHERNET DMA interrupts */
2100+ ETH->DMAIER |= ETH_DMA_IT;
2101+ }
2102+ else
2103+ {
2104+ /* Disable the selected ETHERNET DMA interrupts */
2105+ ETH->DMAIER &=(~(uint32_t)ETH_DMA_IT);
2106+ }
2107+}
2108+
2109+/**
2110+ * @brief Checks whether the specified ETHERNET DMA overflow flag is set or not.
2111+ * @param ETH_DMA_Overflow: specifies the DMA overflow flag to check.
2112+ * This parameter can be one of the following values:
2113+ * @arg ETH_DMA_Overflow_RxFIFOCounter : Overflow for FIFO Overflow Counter
2114+ * @arg ETH_DMA_Overflow_MissedFrameCounter : Overflow for Missed Frame Counter
2115+ * @retval The new state of ETHERNET DMA overflow Flag (SET or RESET).
2116+ */
2117+FlagStatus ETH_GetDMAOverflowStatus(uint32_t ETH_DMA_Overflow)
2118+{
2119+ FlagStatus bitstatus = RESET;
2120+ /* Check the parameters */
2121+ assert_param(IS_ETH_DMA_GET_OVERFLOW(ETH_DMA_Overflow));
2122+
2123+ if ((ETH->DMAMFBOCR & ETH_DMA_Overflow) != (uint32_t)RESET)
2124+ {
2125+ bitstatus = SET;
2126+ }
2127+ else
2128+ {
2129+ bitstatus = RESET;
2130+ }
2131+ return bitstatus;
2132+}
2133+
2134+/**
2135+ * @brief Get the ETHERNET DMA Rx Overflow Missed Frame Counter value.
2136+ * @param None
2137+ * @retval The value of Rx overflow Missed Frame Counter.
2138+ */
2139+uint32_t ETH_GetRxOverflowMissedFrameCounter(void)
2140+{
2141+ return ((uint32_t)((ETH->DMAMFBOCR & ETH_DMAMFBOCR_MFA)>>ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT));
2142+}
2143+
2144+/**
2145+ * @brief Get the ETHERNET DMA Buffer Unavailable Missed Frame Counter value.
2146+ * @param None
2147+ * @retval The value of Buffer unavailable Missed Frame Counter.
2148+ */
2149+uint32_t ETH_GetBufferUnavailableMissedFrameCounter(void)
2150+{
2151+ return ((uint32_t)(ETH->DMAMFBOCR) & ETH_DMAMFBOCR_MFC);
2152+}
2153+
2154+/**
2155+ * @brief Get the ETHERNET DMA DMACHTDR register value.
2156+ * @param None
2157+ * @retval The value of the current Tx desc start address.
2158+ */
2159+uint32_t ETH_GetCurrentTxDescStartAddress(void)
2160+{
2161+ return ((uint32_t)(ETH->DMACHTDR));
2162+}
2163+
2164+/**
2165+ * @brief Get the ETHERNET DMA DMACHRDR register value.
2166+ * @param None
2167+ * @retval The value of the current Rx desc start address.
2168+ */
2169+uint32_t ETH_GetCurrentRxDescStartAddress(void)
2170+{
2171+ return ((uint32_t)(ETH->DMACHRDR));
2172+}
2173+
2174+/**
2175+ * @brief Get the ETHERNET DMA DMACHTBAR register value.
2176+ * @param None
2177+ * @retval The value of the current Tx buffer address.
2178+ */
2179+uint32_t ETH_GetCurrentTxBufferAddress(void)
2180+{
2181+ return ((uint32_t)(ETH->DMACHTBAR));
2182+}
2183+
2184+/**
2185+ * @brief Get the ETHERNET DMA DMACHRBAR register value.
2186+ * @param None
2187+ * @retval The value of the current Rx buffer address.
2188+ */
2189+uint32_t ETH_GetCurrentRxBufferAddress(void)
2190+{
2191+ return ((uint32_t)(ETH->DMACHRBAR));
2192+}
2193+
2194+/**
2195+ * @brief Resumes the DMA Transmission by writing to the DmaTxPollDemand register
2196+ * (the data written could be anything). This forces the DMA to resume transmission.
2197+ * @param None
2198+ * @retval None.
2199+ */
2200+void ETH_ResumeDMATransmission(void)
2201+{
2202+ ETH->DMATPDR = 0;
2203+}
2204+
2205+/**
2206+ * @brief Resumes the DMA Transmission by writing to the DmaRxPollDemand register
2207+ * (the data written could be anything). This forces the DMA to resume reception.
2208+ * @param None
2209+ * @retval None.
2210+ */
2211+void ETH_ResumeDMAReception(void)
2212+{
2213+ ETH->DMARPDR = 0;
2214+}
2215+
2216+/*--------------------------------- PMT ------------------------------------*/
2217+/**
2218+ * @brief Reset Wakeup frame filter register pointer.
2219+ * @param None
2220+ * @retval None
2221+ */
2222+void ETH_ResetWakeUpFrameFilterRegisterPointer(void)
2223+{
2224+ /* Resets the Remote Wake-up Frame Filter register pointer to 0x0000 */
2225+ ETH->MACPMTCSR |= ETH_MACPMTCSR_WFFRPR;
2226+}
2227+
2228+/**
2229+ * @brief Populates the remote wakeup frame registers.
2230+ * @param Buffer: Pointer on remote WakeUp Frame Filter Register buffer data (8 words).
2231+ * @retval None
2232+ */
2233+void ETH_SetWakeUpFrameFilterRegister(uint32_t *Buffer)
2234+{
2235+ uint32_t i = 0;
2236+
2237+ /* Fill Remote Wake-up Frame Filter register with Buffer data */
2238+ for(i =0; i<ETH_WAKEUP_REGISTER_LENGTH; i++)
2239+ {
2240+ /* Write each time to the same register */
2241+ ETH->MACRWUFFR = Buffer[i];
2242+ }
2243+}
2244+
2245+/**
2246+ * @brief Enables or disables any unicast packet filtered by the MAC address
2247+ * recognition to be a wake-up frame.
2248+ * @param NewState: new state of the MAC Global Unicast Wake-Up.
2249+ * This parameter can be: ENABLE or DISABLE.
2250+ * @retval None
2251+ */
2252+void ETH_GlobalUnicastWakeUpCmd(FunctionalState NewState)
2253+{
2254+ /* Check the parameters */
2255+ assert_param(IS_FUNCTIONAL_STATE(NewState));
2256+
2257+ if (NewState != DISABLE)
2258+ {
2259+ /* Enable the MAC Global Unicast Wake-Up */
2260+ ETH->MACPMTCSR |= ETH_MACPMTCSR_GU;
2261+ }
2262+ else
2263+ {
2264+ /* Disable the MAC Global Unicast Wake-Up */
2265+ ETH->MACPMTCSR &= ~ETH_MACPMTCSR_GU;
2266+ }
2267+}
2268+
2269+/**
2270+ * @brief Checks whether the specified ETHERNET PMT flag is set or not.
2271+ * @param ETH_PMT_FLAG: specifies the flag to check.
2272+ * This parameter can be one of the following values:
2273+ * @arg ETH_PMT_FLAG_WUFFRPR : Wake-Up Frame Filter Register Poniter Reset
2274+ * @arg ETH_PMT_FLAG_WUFR : Wake-Up Frame Received
2275+ * @arg ETH_PMT_FLAG_MPR : Magic Packet Received
2276+ * @retval The new state of ETHERNET PMT Flag (SET or RESET).
2277+ */
2278+FlagStatus ETH_GetPMTFlagStatus(uint32_t ETH_PMT_FLAG)
2279+{
2280+ FlagStatus bitstatus = RESET;
2281+ /* Check the parameters */
2282+ assert_param(IS_ETH_PMT_GET_FLAG(ETH_PMT_FLAG));
2283+
2284+ if ((ETH->MACPMTCSR & ETH_PMT_FLAG) != (uint32_t)RESET)
2285+ {
2286+ bitstatus = SET;
2287+ }
2288+ else
2289+ {
2290+ bitstatus = RESET;
2291+ }
2292+ return bitstatus;
2293+}
2294+
2295+/**
2296+ * @brief Enables or disables the MAC Wake-Up Frame Detection.
2297+ * @param NewState: new state of the MAC Wake-Up Frame Detection.
2298+ * This parameter can be: ENABLE or DISABLE.
2299+ * @retval None
2300+ */
2301+void ETH_WakeUpFrameDetectionCmd(FunctionalState NewState)
2302+{
2303+ /* Check the parameters */
2304+ assert_param(IS_FUNCTIONAL_STATE(NewState));
2305+
2306+ if (NewState != DISABLE)
2307+ {
2308+ /* Enable the MAC Wake-Up Frame Detection */
2309+ ETH->MACPMTCSR |= ETH_MACPMTCSR_WFE;
2310+ }
2311+ else
2312+ {
2313+ /* Disable the MAC Wake-Up Frame Detection */
2314+ ETH->MACPMTCSR &= ~ETH_MACPMTCSR_WFE;
2315+ }
2316+}
2317+
2318+/**
2319+ * @brief Enables or disables the MAC Magic Packet Detection.
2320+ * @param NewState: new state of the MAC Magic Packet Detection.
2321+ * This parameter can be: ENABLE or DISABLE.
2322+ * @retval None
2323+ */
2324+void ETH_MagicPacketDetectionCmd(FunctionalState NewState)
2325+{
2326+ /* Check the parameters */
2327+ assert_param(IS_FUNCTIONAL_STATE(NewState));
2328+
2329+ if (NewState != DISABLE)
2330+ {
2331+ /* Enable the MAC Magic Packet Detection */
2332+ ETH->MACPMTCSR |= ETH_MACPMTCSR_MPE;
2333+ }
2334+ else
2335+ {
2336+ /* Disable the MAC Magic Packet Detection */
2337+ ETH->MACPMTCSR &= ~ETH_MACPMTCSR_MPE;
2338+ }
2339+}
2340+
2341+/**
2342+ * @brief Enables or disables the MAC Power Down.
2343+ * @param NewState: new state of the MAC Power Down.
2344+ * This parameter can be: ENABLE or DISABLE.
2345+ * @retval None
2346+ */
2347+void ETH_PowerDownCmd(FunctionalState NewState)
2348+{
2349+ /* Check the parameters */
2350+ assert_param(IS_FUNCTIONAL_STATE(NewState));
2351+
2352+ if (NewState != DISABLE)
2353+ {
2354+ /* Enable the MAC Power Down */
2355+ /* This puts the MAC in power down mode */
2356+ ETH->MACPMTCSR |= ETH_MACPMTCSR_PD;
2357+ }
2358+ else
2359+ {
2360+ /* Disable the MAC Power Down */
2361+ ETH->MACPMTCSR &= ~ETH_MACPMTCSR_PD;
2362+ }
2363+}
2364+
2365+/*--------------------------------- MMC ------------------------------------*/
2366+/**
2367+ * @brief Enables or disables the MMC Counter Freeze.
2368+ * @param NewState: new state of the MMC Counter Freeze.
2369+ * This parameter can be: ENABLE or DISABLE.
2370+ * @retval None
2371+ */
2372+void ETH_MMCCounterFreezeCmd(FunctionalState NewState)
2373+{
2374+ /* Check the parameters */
2375+ assert_param(IS_FUNCTIONAL_STATE(NewState));
2376+
2377+ if (NewState != DISABLE)
2378+ {
2379+ /* Enable the MMC Counter Freeze */
2380+ ETH->MMCCR |= ETH_MMCCR_MCF;
2381+ }
2382+ else
2383+ {
2384+ /* Disable the MMC Counter Freeze */
2385+ ETH->MMCCR &= ~ETH_MMCCR_MCF;
2386+ }
2387+}
2388+
2389+/**
2390+ * @brief Enables or disables the MMC Reset On Read.
2391+ * @param NewState: new state of the MMC Reset On Read.
2392+ * This parameter can be: ENABLE or DISABLE.
2393+ * @retval None
2394+ */
2395+void ETH_MMCResetOnReadCmd(FunctionalState NewState)
2396+{
2397+ /* Check the parameters */
2398+ assert_param(IS_FUNCTIONAL_STATE(NewState));
2399+
2400+ if (NewState != DISABLE)
2401+ {
2402+ /* Enable the MMC Counter reset on read */
2403+ ETH->MMCCR |= ETH_MMCCR_ROR;
2404+ }
2405+ else
2406+ {
2407+ /* Disable the MMC Counter reset on read */
2408+ ETH->MMCCR &= ~ETH_MMCCR_ROR;
2409+ }
2410+}
2411+
2412+/**
2413+ * @brief Enables or disables the MMC Counter Stop Rollover.
2414+ * @param NewState: new state of the MMC Counter Stop Rollover.
2415+ * This parameter can be: ENABLE or DISABLE.
2416+ * @retval None
2417+ */
2418+void ETH_MMCCounterRolloverCmd(FunctionalState NewState)
2419+{
2420+ /* Check the parameters */
2421+ assert_param(IS_FUNCTIONAL_STATE(NewState));
2422+
2423+ if (NewState != DISABLE)
2424+ {
2425+ /* Disable the MMC Counter Stop Rollover */
2426+ ETH->MMCCR &= ~ETH_MMCCR_CSR;
2427+ }
2428+ else
2429+ {
2430+ /* Enable the MMC Counter Stop Rollover */
2431+ ETH->MMCCR |= ETH_MMCCR_CSR;
2432+ }
2433+}
2434+
2435+/**
2436+ * @brief Resets the MMC Counters.
2437+ * @param None
2438+ * @retval None
2439+ */
2440+void ETH_MMCCountersReset(void)
2441+{
2442+ /* Resets the MMC Counters */
2443+ ETH->MMCCR |= ETH_MMCCR_CR;
2444+}
2445+
2446+/**
2447+ * @brief Enables or disables the specified ETHERNET MMC interrupts.
2448+ * @param ETH_MMC_IT: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
2449+ * This parameter can be any combination of Tx interrupt or
2450+ * any combination of Rx interrupt (but not both)of the following values:
2451+ * @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value
2452+ * @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value
2453+ * @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value
2454+ * @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value
2455+ * @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value
2456+ * @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value
2457+ * @param NewState: new state of the specified ETHERNET MMC interrupts.
2458+ * This parameter can be: ENABLE or DISABLE.
2459+ * @retval None
2460+ */
2461+void ETH_MMCITConfig(uint32_t ETH_MMC_IT, FunctionalState NewState)
2462+{
2463+ /* Check the parameters */
2464+ assert_param(IS_ETH_MMC_IT(ETH_MMC_IT));
2465+ assert_param(IS_FUNCTIONAL_STATE(NewState));
2466+
2467+ if ((ETH_MMC_IT & (uint32_t)0x10000000) != (uint32_t)RESET)
2468+ {
2469+ /* Remove egister mak from IT */
2470+ ETH_MMC_IT &= 0xEFFFFFFF;
2471+
2472+ /* ETHERNET MMC Rx interrupts selected */
2473+ if (NewState != DISABLE)
2474+ {
2475+ /* Enable the selected ETHERNET MMC interrupts */
2476+ ETH->MMCRIMR &=(~(uint32_t)ETH_MMC_IT);
2477+ }
2478+ else
2479+ {
2480+ /* Disable the selected ETHERNET MMC interrupts */
2481+ ETH->MMCRIMR |= ETH_MMC_IT;
2482+ }
2483+ }
2484+ else
2485+ {
2486+ /* ETHERNET MMC Tx interrupts selected */
2487+ if (NewState != DISABLE)
2488+ {
2489+ /* Enable the selected ETHERNET MMC interrupts */
2490+ ETH->MMCTIMR &=(~(uint32_t)ETH_MMC_IT);
2491+ }
2492+ else
2493+ {
2494+ /* Disable the selected ETHERNET MMC interrupts */
2495+ ETH->MMCTIMR |= ETH_MMC_IT;
2496+ }
2497+ }
2498+}
2499+
2500+/**
2501+ * @brief Checks whether the specified ETHERNET MMC IT is set or not.
2502+ * @param ETH_MMC_IT: specifies the ETHERNET MMC interrupt.
2503+ * This parameter can be one of the following values:
2504+ * @arg ETH_MMC_IT_TxFCGC: When Tx good frame counter reaches half the maximum value
2505+ * @arg ETH_MMC_IT_TxMCGC: When Tx good multi col counter reaches half the maximum value
2506+ * @arg ETH_MMC_IT_TxSCGC: When Tx good single col counter reaches half the maximum value
2507+ * @arg ETH_MMC_IT_RxUGFC: When Rx good unicast frames counter reaches half the maximum value
2508+ * @arg ETH_MMC_IT_RxAEC : When Rx alignment error counter reaches half the maximum value
2509+ * @arg ETH_MMC_IT_RxCEC : When Rx crc error counter reaches half the maximum value
2510+ * @retval The value of ETHERNET MMC IT (SET or RESET).
2511+ */
2512+ITStatus ETH_GetMMCITStatus(uint32_t ETH_MMC_IT)
2513+{
2514+ ITStatus bitstatus = RESET;
2515+ /* Check the parameters */
2516+ assert_param(IS_ETH_MMC_GET_IT(ETH_MMC_IT));
2517+
2518+ if ((ETH_MMC_IT & (uint32_t)0x10000000) != (uint32_t)RESET)
2519+ {
2520+ /* ETHERNET MMC Rx interrupts selected */
2521+ /* Check if the ETHERNET MMC Rx selected interrupt is enabled and occured */
2522+ if ((((ETH->MMCRIR & ETH_MMC_IT) != (uint32_t)RESET)) && ((ETH->MMCRIMR & ETH_MMC_IT) != (uint32_t)RESET))
2523+ {
2524+ bitstatus = SET;
2525+ }
2526+ else
2527+ {
2528+ bitstatus = RESET;
2529+ }
2530+ }
2531+ else
2532+ {
2533+ /* ETHERNET MMC Tx interrupts selected */
2534+ /* Check if the ETHERNET MMC Tx selected interrupt is enabled and occured */
2535+ if ((((ETH->MMCTIR & ETH_MMC_IT) != (uint32_t)RESET)) && ((ETH->MMCRIMR & ETH_MMC_IT) != (uint32_t)RESET))
2536+ {
2537+ bitstatus = SET;
2538+ }
2539+ else
2540+ {
2541+ bitstatus = RESET;
2542+ }
2543+ }
2544+
2545+ return bitstatus;
2546+}
2547+
2548+/**
2549+ * @brief Get the specified ETHERNET MMC register value.
2550+ * @param ETH_MMCReg: specifies the ETHERNET MMC register.
2551+ * This parameter can be one of the following values:
2552+ * @arg ETH_MMCCR : MMC CR register
2553+ * @arg ETH_MMCRIR : MMC RIR register
2554+ * @arg ETH_MMCTIR : MMC TIR register
2555+ * @arg ETH_MMCRIMR : MMC RIMR register
2556+ * @arg ETH_MMCTIMR : MMC TIMR register
2557+ * @arg ETH_MMCTGFSCCR : MMC TGFSCCR register
2558+ * @arg ETH_MMCTGFMSCCR: MMC TGFMSCCR register
2559+ * @arg ETH_MMCTGFCR : MMC TGFCR register
2560+ * @arg ETH_MMCRFCECR : MMC RFCECR register
2561+ * @arg ETH_MMCRFAECR : MMC RFAECR register
2562+ * @arg ETH_MMCRGUFCR : MMC RGUFCRregister
2563+ * @retval The value of ETHERNET MMC Register value.
2564+ */
2565+uint32_t ETH_GetMMCRegister(uint32_t ETH_MMCReg)
2566+{
2567+ /* Check the parameters */
2568+ assert_param(IS_ETH_MMC_REGISTER(ETH_MMCReg));
2569+
2570+ /* Return the selected register value */
2571+ return (*(__IO uint32_t *)(ETH_MAC_BASE + ETH_MMCReg));
2572+}
2573+/*--------------------------------- PTP ------------------------------------*/
2574+
2575+/**
2576+ * @brief Updated the PTP block for fine correction with the Time Stamp Addend register value.
2577+ * @param None
2578+ * @retval None
2579+ */
2580+void ETH_EnablePTPTimeStampAddend(void)
2581+{
2582+ /* Enable the PTP block update with the Time Stamp Addend register value */
2583+ ETH->PTPTSCR |= ETH_PTPTSCR_TSARU;
2584+}
2585+
2586+/**
2587+ * @brief Enable the PTP Time Stamp interrupt trigger
2588+ * @param None
2589+ * @retval None
2590+ */
2591+void ETH_EnablePTPTimeStampInterruptTrigger(void)
2592+{
2593+ /* Enable the PTP target time interrupt */
2594+ ETH->PTPTSCR |= ETH_PTPTSCR_TSITE;
2595+}
2596+
2597+/**
2598+ * @brief Updated the PTP system time with the Time Stamp Update register value.
2599+ * @param None
2600+ * @retval None
2601+ */
2602+void ETH_EnablePTPTimeStampUpdate(void)
2603+{
2604+ /* Enable the PTP system time update with the Time Stamp Update register value */
2605+ ETH->PTPTSCR |= ETH_PTPTSCR_TSSTU;
2606+}
2607+
2608+/**
2609+ * @brief Initialize the PTP Time Stamp
2610+ * @param None
2611+ * @retval None
2612+ */
2613+void ETH_InitializePTPTimeStamp(void)
2614+{
2615+ /* Initialize the PTP Time Stamp */
2616+ ETH->PTPTSCR |= ETH_PTPTSCR_TSSTI;
2617+}
2618+
2619+/**
2620+ * @brief Selects the PTP Update method
2621+ * @param UpdateMethod: the PTP Update method
2622+ * This parameter can be one of the following values:
2623+ * @arg ETH_PTP_FineUpdate : Fine Update method
2624+ * @arg ETH_PTP_CoarseUpdate : Coarse Update method
2625+ * @retval None
2626+ */
2627+void ETH_PTPUpdateMethodConfig(uint32_t UpdateMethod)
2628+{
2629+ /* Check the parameters */
2630+ assert_param(IS_ETH_PTP_UPDATE(UpdateMethod));
2631+
2632+ if (UpdateMethod != ETH_PTP_CoarseUpdate)
2633+ {
2634+ /* Enable the PTP Fine Update method */
2635+ ETH->PTPTSCR |= ETH_PTPTSCR_TSFCU;
2636+ }
2637+ else
2638+ {
2639+ /* Disable the PTP Coarse Update method */
2640+ ETH->PTPTSCR &= (~(uint32_t)ETH_PTPTSCR_TSFCU);
2641+ }
2642+}
2643+
2644+/**
2645+ * @brief Enables or disables the PTP time stamp for transmit and receive frames.
2646+ * @param NewState: new state of the PTP time stamp for transmit and receive frames
2647+ * This parameter can be: ENABLE or DISABLE.
2648+ * @retval None
2649+ */
2650+void ETH_PTPTimeStampCmd(FunctionalState NewState)
2651+{
2652+ /* Check the parameters */
2653+ assert_param(IS_FUNCTIONAL_STATE(NewState));
2654+
2655+ if (NewState != DISABLE)
2656+ {
2657+ /* Enable the PTP time stamp for transmit and receive frames */
2658+ ETH->PTPTSCR |= ETH_PTPTSCR_TSE;
2659+ }
2660+ else
2661+ {
2662+ /* Disable the PTP time stamp for transmit and receive frames */
2663+ ETH->PTPTSCR &= (~(uint32_t)ETH_PTPTSCR_TSE);
2664+ }
2665+}
2666+
2667+/**
2668+ * @brief Checks whether the specified ETHERNET PTP flag is set or not.
2669+ * @param ETH_PTP_FLAG: specifies the flag to check.
2670+ * This parameter can be one of the following values:
2671+ * @arg ETH_PTP_FLAG_TSARU : Addend Register Update
2672+ * @arg ETH_PTP_FLAG_TSITE : Time Stamp Interrupt Trigger Enable
2673+ * @arg ETH_PTP_FLAG_TSSTU : Time Stamp Update
2674+ * @arg ETH_PTP_FLAG_TSSTI : Time Stamp Initialize
2675+ * @retval The new state of ETHERNET PTP Flag (SET or RESET).
2676+ */
2677+FlagStatus ETH_GetPTPFlagStatus(uint32_t ETH_PTP_FLAG)
2678+{
2679+ FlagStatus bitstatus = RESET;
2680+ /* Check the parameters */
2681+ assert_param(IS_ETH_PTP_GET_FLAG(ETH_PTP_FLAG));
2682+
2683+ if ((ETH->PTPTSCR & ETH_PTP_FLAG) != (uint32_t)RESET)
2684+ {
2685+ bitstatus = SET;
2686+ }
2687+ else
2688+ {
2689+ bitstatus = RESET;
2690+ }
2691+ return bitstatus;
2692+}
2693+
2694+/**
2695+ * @brief Sets the system time Sub-Second Increment value.
2696+ * @param SubSecondValue: specifies the PTP Sub-Second Increment Register value.
2697+ * @retval None
2698+ */
2699+void ETH_SetPTPSubSecondIncrement(uint32_t SubSecondValue)
2700+{
2701+ /* Check the parameters */
2702+ assert_param(IS_ETH_PTP_SUBSECOND_INCREMENT(SubSecondValue));
2703+ /* Set the PTP Sub-Second Increment Register */
2704+ ETH->PTPSSIR = SubSecondValue;
2705+}
2706+
2707+/**
2708+ * @brief Sets the Time Stamp update sign and values.
2709+ * @param Sign: specifies the PTP Time update value sign.
2710+ * This parameter can be one of the following values:
2711+ * @arg ETH_PTP_PositiveTime : positive time value.
2712+ * @arg ETH_PTP_NegativeTime : negative time value.
2713+ * @param SecondValue: specifies the PTP Time update second value.
2714+ * @param SubSecondValue: specifies the PTP Time update sub-second value.
2715+ * This parameter is a 31 bit value, bit32 correspond to the sign.
2716+ * @retval None
2717+ */
2718+void ETH_SetPTPTimeStampUpdate(uint32_t Sign, uint32_t SecondValue, uint32_t SubSecondValue)
2719+{
2720+ /* Check the parameters */
2721+ assert_param(IS_ETH_PTP_TIME_SIGN(Sign));
2722+ assert_param(IS_ETH_PTP_TIME_STAMP_UPDATE_SUBSECOND(SubSecondValue));
2723+ /* Set the PTP Time Update High Register */
2724+ ETH->PTPTSHUR = SecondValue;
2725+
2726+ /* Set the PTP Time Update Low Register with sign */
2727+ ETH->PTPTSLUR = Sign | SubSecondValue;
2728+}
2729+
2730+/**
2731+ * @brief Sets the Time Stamp Addend value.
2732+ * @param Value: specifies the PTP Time Stamp Addend Register value.
2733+ * @retval None
2734+ */
2735+void ETH_SetPTPTimeStampAddend(uint32_t Value)
2736+{
2737+ /* Set the PTP Time Stamp Addend Register */
2738+ ETH->PTPTSAR = Value;
2739+}
2740+
2741+/**
2742+ * @brief Sets the Target Time registers values.
2743+ * @param HighValue: specifies the PTP Target Time High Register value.
2744+ * @param LowValue: specifies the PTP Target Time Low Register value.
2745+ * @retval None
2746+ */
2747+void ETH_SetPTPTargetTime(uint32_t HighValue, uint32_t LowValue)
2748+{
2749+ /* Set the PTP Target Time High Register */
2750+ ETH->PTPTTHR = HighValue;
2751+ /* Set the PTP Target Time Low Register */
2752+ ETH->PTPTTLR = LowValue;
2753+}
2754+
2755+/**
2756+ * @brief Get the specified ETHERNET PTP register value.
2757+ * @param ETH_PTPReg: specifies the ETHERNET PTP register.
2758+ * This parameter can be one of the following values:
2759+ * @arg ETH_PTPTSCR : Sub-Second Increment Register
2760+ * @arg ETH_PTPSSIR : Sub-Second Increment Register
2761+ * @arg ETH_PTPTSHR : Time Stamp High Register
2762+ * @arg ETH_PTPTSLR : Time Stamp Low Register
2763+ * @arg ETH_PTPTSHUR : Time Stamp High Update Register
2764+ * @arg ETH_PTPTSLUR : Time Stamp Low Update Register
2765+ * @arg ETH_PTPTSAR : Time Stamp Addend Register
2766+ * @arg ETH_PTPTTHR : Target Time High Register
2767+ * @arg ETH_PTPTTLR : Target Time Low Register
2768+ * @retval The value of ETHERNET PTP Register value.
2769+ */
2770+uint32_t ETH_GetPTPRegister(uint32_t ETH_PTPReg)
2771+{
2772+ /* Check the parameters */
2773+ assert_param(IS_ETH_PTP_REGISTER(ETH_PTPReg));
2774+
2775+ /* Return the selected register value */
2776+ return (*(__IO uint32_t *)(ETH_MAC_BASE + ETH_PTPReg));
2777+}
2778+
2779+/**
2780+ * @brief Initializes the DMA Tx descriptors in chain mode with PTP.
2781+ * @param DMATxDescTab: Pointer on the first Tx desc list
2782+ * @param DMAPTPTxDescTab: Pointer on the first PTP Tx desc list
2783+ * @param TxBuff: Pointer on the first TxBuffer list
2784+ * @param TxBuffCount: Number of the used Tx desc in the list
2785+ * @retval None
2786+ */
2787+void ETH_DMAPTPTxDescChainInit(ETH_DMADESCTypeDef *DMATxDescTab, ETH_DMADESCTypeDef *DMAPTPTxDescTab,
2788+ uint8_t* TxBuff, uint32_t TxBuffCount)
2789+{
2790+ uint32_t i = 0;
2791+ ETH_DMADESCTypeDef *DMATxDesc;
2792+
2793+ /* Set the DMATxDescToSet pointer with the first one of the DMATxDescTab list */
2794+ DMATxDescToSet = DMATxDescTab;
2795+ DMAPTPTxDescToSet = DMAPTPTxDescTab;
2796+ /* Fill each DMATxDesc descriptor with the right values */
2797+ for(i=0; i < TxBuffCount; i++)
2798+ {
2799+ /* Get the pointer on the ith member of the Tx Desc list */
2800+ DMATxDesc = DMATxDescTab+i;
2801+ /* Set Second Address Chained bit and enable PTP */
2802+ DMATxDesc->Status = ETH_DMATxDesc_TCH | ETH_DMATxDesc_TTSE;
2803+
2804+ /* Set Buffer1 address pointer */
2805+ DMATxDesc->Buffer1Addr =(uint32_t)(&TxBuff[i*ETH_MAX_PACKET_SIZE]);
2806+
2807+ /* Initialize the next descriptor with the Next Desciptor Polling Enable */
2808+ if(i < (TxBuffCount-1))
2809+ {
2810+ /* Set next descriptor address register with next descriptor base address */
2811+ DMATxDesc->Buffer2NextDescAddr = (uint32_t)(DMATxDescTab+i+1);
2812+ }
2813+ else
2814+ {
2815+ /* For last descriptor, set next descriptor address register equal to the first descriptor base address */
2816+ DMATxDesc->Buffer2NextDescAddr = (uint32_t) DMATxDescTab;
2817+ }
2818+ /* make DMAPTPTxDescTab points to the same addresses as DMATxDescTab */
2819+ (&DMAPTPTxDescTab[i])->Buffer1Addr = DMATxDesc->Buffer1Addr;
2820+ (&DMAPTPTxDescTab[i])->Buffer2NextDescAddr = DMATxDesc->Buffer2NextDescAddr;
2821+ }
2822+ /* Store on the last DMAPTPTxDescTab desc status record the first list address */
2823+ (&DMAPTPTxDescTab[i-1])->Status = (uint32_t) DMAPTPTxDescTab;
2824+
2825+ /* Set Transmit Desciptor List Address Register */
2826+ ETH->DMATDLAR = (uint32_t) DMATxDescTab;
2827+}
2828+
2829+/**
2830+ * @brief Initializes the DMA Rx descriptors in chain mode.
2831+ * @param DMARxDescTab: Pointer on the first Rx desc list
2832+ * @param DMAPTPRxDescTab: Pointer on the first PTP Rx desc list
2833+ * @param RxBuff: Pointer on the first RxBuffer list
2834+ * @param RxBuffCount: Number of the used Rx desc in the list
2835+ * @retval None
2836+ */
2837+void ETH_DMAPTPRxDescChainInit(ETH_DMADESCTypeDef *DMARxDescTab, ETH_DMADESCTypeDef *DMAPTPRxDescTab,
2838+ uint8_t *RxBuff, uint32_t RxBuffCount)
2839+{
2840+ uint32_t i = 0;
2841+ ETH_DMADESCTypeDef *DMARxDesc;
2842+
2843+ /* Set the DMARxDescToGet pointer with the first one of the DMARxDescTab list */
2844+ DMARxDescToGet = DMARxDescTab;
2845+ DMAPTPRxDescToGet = DMAPTPRxDescTab;
2846+ /* Fill each DMARxDesc descriptor with the right values */
2847+ for(i=0; i < RxBuffCount; i++)
2848+ {
2849+ /* Get the pointer on the ith member of the Rx Desc list */
2850+ DMARxDesc = DMARxDescTab+i;
2851+ /* Set Own bit of the Rx descriptor Status */
2852+ DMARxDesc->Status = ETH_DMARxDesc_OWN;
2853+
2854+ /* Set Buffer1 size and Second Address Chained bit */
2855+ DMARxDesc->ControlBufferSize = ETH_DMARxDesc_RCH | (uint32_t)ETH_MAX_PACKET_SIZE;
2856+ /* Set Buffer1 address pointer */
2857+ DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff[i*ETH_MAX_PACKET_SIZE]);
2858+
2859+ /* Initialize the next descriptor with the Next Desciptor Polling Enable */
2860+ if(i < (RxBuffCount-1))
2861+ {
2862+ /* Set next descriptor address register with next descriptor base address */
2863+ DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab+i+1);
2864+ }
2865+ else
2866+ {
2867+ /* For last descriptor, set next descriptor address register equal to the first descriptor base address */
2868+ DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab);
2869+ }
2870+ /* Make DMAPTPRxDescTab points to the same addresses as DMARxDescTab */
2871+ (&DMAPTPRxDescTab[i])->Buffer1Addr = DMARxDesc->Buffer1Addr;
2872+ (&DMAPTPRxDescTab[i])->Buffer2NextDescAddr = DMARxDesc->Buffer2NextDescAddr;
2873+ }
2874+ /* Store on the last DMAPTPRxDescTab desc status record the first list address */
2875+ (&DMAPTPRxDescTab[i-1])->Status = (uint32_t) DMAPTPRxDescTab;
2876+
2877+ /* Set Receive Desciptor List Address Register */
2878+ ETH->DMARDLAR = (uint32_t) DMARxDescTab;
2879+}
2880+
2881+/**
2882+ * @brief Transmits a packet, from application buffer, pointed by ppkt with Time Stamp values.
2883+ * @param ppkt: pointer to application packet buffer to transmit.
2884+ * @param FrameLength: Tx Packet size.
2885+ * @param PTPTxTab: Pointer on the first PTP Tx table to store Time stamp values.
2886+ * @retval ETH_ERROR: in case of Tx desc owned by DMA
2887+ * ETH_SUCCESS: for correct transmission
2888+ */
2889+uint32_t ETH_HandlePTPTxPkt(uint8_t *ppkt, uint16_t FrameLength, uint32_t *PTPTxTab)
2890+{
2891+ uint32_t offset = 0, timeout = 0;
2892+ /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */
2893+ if((DMATxDescToSet->Status & ETH_DMATxDesc_OWN) != (uint32_t)RESET)
2894+ {
2895+ /* Return ERROR: OWN bit set */
2896+ return ETH_ERROR;
2897+ }
2898+ /* Copy the frame to be sent into memory pointed by the current ETHERNET DMA Tx descriptor */
2899+ for(offset=0; offset<FrameLength; offset++)
2900+ {
2901+ (*(__IO uint8_t *)((DMAPTPTxDescToSet->Buffer1Addr) + offset)) = (*(ppkt + offset));
2902+ }
2903+ /* Setting the Frame Length: bits[12:0] */
2904+ DMATxDescToSet->ControlBufferSize = (FrameLength & (uint32_t)0x1FFF);
2905+ /* Setting the last segment and first segment bits (in this case a frame is transmitted in one descriptor) */
2906+ DMATxDescToSet->Status |= ETH_DMATxDesc_LS | ETH_DMATxDesc_FS;
2907+ /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
2908+ DMATxDescToSet->Status |= ETH_DMATxDesc_OWN;
2909+ /* When Tx Buffer unavailable flag is set: clear it and resume transmission */
2910+ if ((ETH->DMASR & ETH_DMASR_TBUS) != (uint32_t)RESET)
2911+ {
2912+ /* Clear TBUS ETHERNET DMA flag */
2913+ ETH->DMASR = ETH_DMASR_TBUS;
2914+ /* Resume DMA transmission*/
2915+ ETH->DMATPDR = 0;
2916+ }
2917+ /* Wait for ETH_DMATxDesc_TTSS flag to be set */
2918+ do
2919+ {
2920+ timeout++;
2921+ } while (!(DMATxDescToSet->Status & ETH_DMATxDesc_TTSS) && (timeout < 0xFFFF));
2922+ /* Return ERROR in case of timeout */
2923+ if(timeout == PHY_READ_TO)
2924+ {
2925+ return ETH_ERROR;
2926+ }
2927+ /* Clear the DMATxDescToSet status register TTSS flag */
2928+ DMATxDescToSet->Status &= ~ETH_DMATxDesc_TTSS;
2929+ *PTPTxTab++ = DMATxDescToSet->Buffer1Addr;
2930+ *PTPTxTab = DMATxDescToSet->Buffer2NextDescAddr;
2931+ /* Update the ENET DMA current descriptor */
2932+ /* Chained Mode */
2933+ if((DMATxDescToSet->Status & ETH_DMATxDesc_TCH) != (uint32_t)RESET)
2934+ {
2935+ /* Selects the next DMA Tx descriptor list for next buffer read */
2936+ DMATxDescToSet = (ETH_DMADESCTypeDef*) (DMAPTPTxDescToSet->Buffer2NextDescAddr);
2937+ if(DMAPTPTxDescToSet->Status != 0)
2938+ {
2939+ DMAPTPTxDescToSet = (ETH_DMADESCTypeDef*) (DMAPTPTxDescToSet->Status);
2940+ }
2941+ else
2942+ {
2943+ DMAPTPTxDescToSet++;
2944+ }
2945+ }
2946+ else /* Ring Mode */
2947+ {
2948+ if((DMATxDescToSet->Status & ETH_DMATxDesc_TER) != (uint32_t)RESET)
2949+ {
2950+ /* Selects the next DMA Tx descriptor list for next buffer read: this will
2951+ be the first Tx descriptor in this case */
2952+ DMATxDescToSet = (ETH_DMADESCTypeDef*) (ETH->DMATDLAR);
2953+ DMAPTPTxDescToSet = (ETH_DMADESCTypeDef*) (ETH->DMATDLAR);
2954+ }
2955+ else
2956+ {
2957+ /* Selects the next DMA Tx descriptor list for next buffer read */
2958+ DMATxDescToSet = (ETH_DMADESCTypeDef*) ((uint32_t)DMATxDescToSet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2));
2959+ DMAPTPTxDescToSet = (ETH_DMADESCTypeDef*) ((uint32_t)DMAPTPTxDescToSet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2));
2960+ }
2961+ }
2962+ /* Return SUCCESS */
2963+ return ETH_SUCCESS;
2964+}
2965+
2966+/**
2967+ * @brief Receives a packet and copies it to memory pointed by ppkt with Time Stamp values.
2968+ * @param ppkt: pointer to application packet receive buffer.
2969+ * @param PTPRxTab: Pointer on the first PTP Rx table to store Time stamp values.
2970+ * @retval ETH_ERROR: if there is error in reception
2971+ * framelength: received packet size if packet reception is correct
2972+ */
2973+uint32_t ETH_HandlePTPRxPkt(uint8_t *ppkt, uint32_t *PTPRxTab)
2974+{
2975+ uint32_t offset = 0, framelength = 0;
2976+ /* Check if the descriptor is owned by the ENET or CPU */
2977+ if((DMARxDescToGet->Status & ETH_DMARxDesc_OWN) != (uint32_t)RESET)
2978+ {
2979+ /* Return error: OWN bit set */
2980+ return ETH_ERROR;
2981+ }
2982+ if(((DMARxDescToGet->Status & ETH_DMARxDesc_ES) == (uint32_t)RESET) &&
2983+ ((DMARxDescToGet->Status & ETH_DMARxDesc_LS) != (uint32_t)RESET) &&
2984+ ((DMARxDescToGet->Status & ETH_DMARxDesc_FS) != (uint32_t)RESET))
2985+ {
2986+ /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */
2987+ framelength = ((DMARxDescToGet->Status & ETH_DMARxDesc_FL) >> ETH_DMARXDESC_FRAME_LENGTHSHIFT) - 4;
2988+ /* Copy the received frame into buffer from memory pointed by the current ETHERNET DMA Rx descriptor */
2989+ for(offset=0; offset<framelength; offset++)
2990+ {
2991+ (*(ppkt + offset)) = (*(__IO uint8_t *)((DMAPTPRxDescToGet->Buffer1Addr) + offset));
2992+ }
2993+ }
2994+ else
2995+ {
2996+ /* Return ERROR */
2997+ framelength = ETH_ERROR;
2998+ }
2999+ /* When Rx Buffer unavailable flag is set: clear it and resume reception */
3000+ if ((ETH->DMASR & ETH_DMASR_RBUS) != (uint32_t)RESET)
3001+ {
3002+ /* Clear RBUS ETHERNET DMA flag */
3003+ ETH->DMASR = ETH_DMASR_RBUS;
3004+ /* Resume DMA reception */
3005+ ETH->DMARPDR = 0;
3006+ }
3007+ *PTPRxTab++ = DMARxDescToGet->Buffer1Addr;
3008+ *PTPRxTab = DMARxDescToGet->Buffer2NextDescAddr;
3009+ /* Set Own bit of the Rx descriptor Status: gives the buffer back to ETHERNET DMA */
3010+ DMARxDescToGet->Status |= ETH_DMARxDesc_OWN;
3011+ /* Update the ETHERNET DMA global Rx descriptor with next Rx decriptor */
3012+ /* Chained Mode */
3013+ if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RCH) != (uint32_t)RESET)
3014+ {
3015+ /* Selects the next DMA Rx descriptor list for next buffer read */
3016+ DMARxDescToGet = (ETH_DMADESCTypeDef*) (DMAPTPRxDescToGet->Buffer2NextDescAddr);
3017+ if(DMAPTPRxDescToGet->Status != 0)
3018+ {
3019+ DMAPTPRxDescToGet = (ETH_DMADESCTypeDef*) (DMAPTPRxDescToGet->Status);
3020+ }
3021+ else
3022+ {
3023+ DMAPTPRxDescToGet++;
3024+ }
3025+ }
3026+ else /* Ring Mode */
3027+ {
3028+ if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RER) != (uint32_t)RESET)
3029+ {
3030+ /* Selects the first DMA Rx descriptor for next buffer to read: last Rx descriptor was used */
3031+ DMARxDescToGet = (ETH_DMADESCTypeDef*) (ETH->DMARDLAR);
3032+ }
3033+ else
3034+ {
3035+ /* Selects the next DMA Rx descriptor list for next buffer to read */
3036+ DMARxDescToGet = (ETH_DMADESCTypeDef*) ((uint32_t)DMARxDescToGet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2));
3037+ }
3038+ }
3039+ /* Return Frame Length/ERROR */
3040+ return (framelength);
3041+}
3042+
3043+#ifndef USE_Delay
3044+/**
3045+ * @brief Inserts a delay time.
3046+ * @param nCount: specifies the delay time length.
3047+ * @retval None
3048+ */
3049+static void ETH_Delay(__IO uint32_t nCount)
3050+{
3051+ __IO uint32_t index = 0;
3052+ for(index = nCount; index != 0; index--)
3053+ {
3054+ }
3055+}
3056+#endif /* USE_Delay*/
3057+
3058+/**
3059+ * @}
3060+ */
3061+
3062+/**
3063+ * @}
3064+ */
3065+
3066+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
--- branches/stm32_ethernet_wrapper/os/hal/platforms/STM32/stm32_eth.h (nonexistent)
+++ branches/stm32_ethernet_wrapper/os/hal/platforms/STM32/stm32_eth.h (revision 2871)
@@ -0,0 +1,1742 @@
1+/**
2+ ******************************************************************************
3+ * @file stm32_eth.h
4+ * @author MCD Application Team
5+ * @version V1.1.0
6+ * @date 11/20/2009
7+ * @brief This file contains all the functions prototypes for the Ethernet
8+ * firmware library.
9+ ******************************************************************************
10+ * @copy
11+ *
12+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
13+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
14+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
15+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
16+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
17+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
18+ *
19+ * <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2>
20+ */
21+
22+/* Define to prevent recursive inclusion -------------------------------------*/
23+#ifndef __STM32_ETH_H
24+#define __STM32_ETH_H
25+
26+#ifdef __cplusplus
27+ extern "C" {
28+#endif
29+
30+/* Includes ------------------------------------------------------------------*/
31+#include "stm32f10x.h"
32+
33+/** @addtogroup STM32_ETH_Driver
34+ * @{
35+ */
36+
37+/** @defgroup ETH_Exported_Types
38+ * @{
39+ */
40+
41+/**
42+ * @brief ETH MAC Init structure definition
43+ * @note The user should not configure all the ETH_InitTypeDef structure's fields.
44+ * By calling the ETH_StructInit function the structure’s fields are set to their default values.
45+ * Only the parameters that will be set to a non-default value should be configured.
46+ */
47+typedef struct {
48+/**
49+ * @brief / * MAC
50+ */
51+ uint32_t ETH_AutoNegotiation; /*!< Selects or not the AutoNegotiation mode for the external PHY
52+ The AutoNegotiation allows an automatic setting of the Speed (10/100Mbps)
53+ and the mode (half/full-duplex).
54+ This parameter can be a value of @ref ETH_AutoNegotiation */
55+
56+ uint32_t ETH_Watchdog; /*!< Selects or not the Watchdog timer
57+ When enabled, the MAC allows no more then 2048 bytes to be received.
58+ When disabled, the MAC can receive up to 16384 bytes.
59+ This parameter can be a value of @ref ETH_watchdog */
60+
61+ uint32_t ETH_Jabber; /*!< Selects or not Jabber timer
62+ When enabled, the MAC allows no more then 2048 bytes to be sent.
63+ When disabled, the MAC can send up to 16384 bytes.
64+ This parameter can be a value of @ref ETH_Jabber */
65+
66+ uint32_t ETH_InterFrameGap; /*!< Selects the minimum IFG between frames during transmission
67+ This parameter can be a value of @ref ETH_Inter_Frame_Gap */
68+
69+ uint32_t ETH_CarrierSense; /*!< Selects or not the Carrier Sense
70+ This parameter can be a value of @ref ETH_Carrier_Sense */
71+
72+ uint32_t ETH_Speed; /*!< Sets the Ethernet speed: 10/100 Mbps
73+ This parameter can be a value of @ref ETH_Speed */
74+
75+ uint32_t ETH_ReceiveOwn; /*!< Selects or not the ReceiveOwn
76+ ReceiveOwn allows the reception of frames when the TX_EN signal is asserted
77+ in Half-Duplex mode
78+ This parameter can be a value of @ref ETH_Receive_Own */
79+
80+ uint32_t ETH_LoopbackMode; /*!< Selects or not the internal MAC MII Loopback mode
81+ This parameter can be a value of @ref ETH_Loop_Back_Mode */
82+
83+ uint32_t ETH_Mode; /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode
84+ This parameter can be a value of @ref ETH_Duplex_Mode */
85+
86+ uint32_t ETH_ChecksumOffload; /*!< Selects or not the IPv4 checksum checking for received frame payloads' TCP/UDP/ICMP headers.
87+ This parameter can be a value of @ref ETH_Checksum_Offload */
88+
89+ uint32_t ETH_RetryTransmission; /*!< Selects or not the MAC attempt retries transmission, based on the settings of BL,
90+ when a colision occurs (Half-Duplex mode)
91+ This parameter can be a value of @ref ETH_Retry_Transmission */
92+
93+ uint32_t ETH_AutomaticPadCRCStrip; /*!< Selects or not the Automatic MAC Pad/CRC Stripping
94+ This parameter can be a value of @ref ETH_Automatic_Pad_CRC_Strip */
95+
96+ uint32_t ETH_BackOffLimit; /*!< Selects the BackOff limit value
97+ This parameter can be a value of @ref ETH_Back_Off_Limit */
98+
99+ uint32_t ETH_DeferralCheck; /*!< Selects or not the deferral check function (Half-Duplex mode)
100+ This parameter can be a value of @ref ETH_Deferral_Check */
101+
102+ uint32_t ETH_ReceiveAll; /*!< Selects or not all frames reception by the MAC (No fitering)
103+ This parameter can be a value of @ref ETH_Receive_All */
104+
105+ uint32_t ETH_SourceAddrFilter; /*!< Selects the Source Address Filter mode
106+ This parameter can be a value of @ref ETH_Source_Addr_Filter */
107+
108+ uint32_t ETH_PassControlFrames; /*!< Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames)
109+ This parameter can be a value of @ref ETH_Pass_Control_Frames */
110+
111+ uint32_t ETH_BroadcastFramesReception; /*!< Selects or not the reception of Broadcast Frames
112+ This parameter can be a value of @ref ETH_Broadcast_Frames_Reception */
113+
114+ uint32_t ETH_DestinationAddrFilter; /*!< Sets the destination filter mode for both unicast and multicast frames
115+ This parameter can be a value of @ref ETH_Destination_Addr_Filter */
116+
117+ uint32_t ETH_PromiscuousMode; /*!< Selects or not the Promiscuous Mode
118+ This parameter can be a value of @ref ETH_Promiscuous_Mode */
119+
120+ uint32_t ETH_MulticastFramesFilter; /*!< Selects the Multicast Frames filter mode: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter
121+ This parameter can be a value of @ref ETH_Multicast_Frames_Filter */
122+
123+ uint32_t ETH_UnicastFramesFilter; /*!< Selects the Unicast Frames filter mode: HashTableFilter/PerfectFilter/PerfectHashTableFilter
124+ This parameter can be a value of @ref ETH_Unicast_Frames_Filter */
125+
126+ uint32_t ETH_HashTableHigh; /*!< This field holds the higher 32 bits of Hash table. */
127+
128+ uint32_t ETH_HashTableLow; /*!< This field holds the lower 32 bits of Hash table. */
129+
130+ uint32_t ETH_PauseTime; /*!< This field holds the value to be used in the Pause Time field in the
131+ transmit control frame */
132+
133+ uint32_t ETH_ZeroQuantaPause; /*!< Selects or not the automatic generation of Zero-Quanta Pause Control frames
134+ This parameter can be a value of @ref ETH_Zero_Quanta_Pause */
135+
136+ uint32_t ETH_PauseLowThreshold; /*!< This field configures the threshold of the PAUSE to be checked for
137+ automatic retransmission of PAUSE Frame
138+ This parameter can be a value of @ref ETH_Pause_Low_Threshold */
139+
140+ uint32_t ETH_UnicastPauseFrameDetect; /*!< Selects or not the MAC detection of the Pause frames (with MAC Address0
141+ unicast address and unique multicast address)
142+ This parameter can be a value of @ref ETH_Unicast_Pause_Frame_Detect */
143+
144+ uint32_t ETH_ReceiveFlowControl; /*!< Enables or disables the MAC to decode the received Pause frame and
145+ disable its transmitter for a specified time (Pause Time)
146+ This parameter can be a value of @ref ETH_Receive_Flow_Control */
147+
148+ uint32_t ETH_TransmitFlowControl; /*!< Enables or disables the MAC to transmit Pause frames (Full-Duplex mode)
149+ or the MAC back-pressure operation (Half-Duplex mode)
150+ This parameter can be a value of @ref ETH_Transmit_Flow_Control */
151+
152+ uint32_t ETH_VLANTagComparison; /*!< Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for
153+ comparison and filtering
154+ This parameter can be a value of @ref ETH_VLAN_Tag_Comparison */
155+
156+ uint32_t ETH_VLANTagIdentifier; /*!< Holds the VLAN tag identifier for receive frames */
157+
158+/**
159+ * @brief / * DMA
160+ */
161+
162+ uint32_t ETH_DropTCPIPChecksumErrorFrame; /*!< Selects or not the Dropping of TCP/IP Checksum Error Frames
163+ This parameter can be a value of @ref ETH_Drop_TCP_IP_Checksum_Error_Frame */
164+
165+ uint32_t ETH_ReceiveStoreForward; /*!< Enables or disables the Receive store and forward mode
166+ This parameter can be a value of @ref ETH_Receive_Store_Forward */
167+
168+ uint32_t ETH_FlushReceivedFrame; /*!< Enables or disables the flushing of received frames
169+ This parameter can be a value of @ref ETH_Flush_Received_Frame */
170+
171+ uint32_t ETH_TransmitStoreForward; /*!< Enables or disables Transmit store and forward mode
172+ This parameter can be a value of @ref ETH_Transmit_Store_Forward */
173+
174+ uint32_t ETH_TransmitThresholdControl; /*!< Selects or not the Transmit Threshold Control
175+ This parameter can be a value of @ref ETH_Transmit_Threshold_Control */
176+
177+ uint32_t ETH_ForwardErrorFrames; /*!< Selects or not the forward to the DMA of erroneous frames
178+ This parameter can be a value of @ref ETH_Forward_Error_Frames */
179+
180+ uint32_t ETH_ForwardUndersizedGoodFrames; /*!< Enables or disables the Rx FIFO to forward Undersized frames (frames with no Error
181+ and length less than 64 bytes) including pad-bytes and CRC)
182+ This parameter can be a value of @ref ETH_Forward_Undersized_Good_Frames */
183+
184+ uint32_t ETH_ReceiveThresholdControl; /*!< Selects the threshold level of the Receive FIFO
185+ This parameter can be a value of @ref ETH_Receive_Threshold_Control */
186+
187+ uint32_t ETH_SecondFrameOperate; /*!< Selects or not the Operate on second frame mode, which allows the DMA to process a second
188+ frame of Transmit data even before obtaining the status for the first frame.
189+ This parameter can be a value of @ref ETH_Second_Frame_Operate */
190+
191+ uint32_t ETH_AddressAlignedBeats; /*!< Enables or disables the Address Aligned Beats
192+ This parameter can be a value of @ref ETH_Address_Aligned_Beats */
193+
194+ uint32_t ETH_FixedBurst; /*!< Enables or disables the AHB Master interface fixed burst transfers
195+ This parameter can be a value of @ref ETH_Fixed_Burst */
196+
197+ uint32_t ETH_RxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction
198+ This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */
199+
200+ uint32_t ETH_TxDMABurstLength; /*!< Indicates sthe maximum number of beats to be transferred in one Tx DMA transaction
201+ This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */
202+
203+ uint32_t ETH_DescriptorSkipLength; /*!< Specifies the number of word to skip between two unchained descriptors (Ring mode) */
204+
205+ uint32_t ETH_DMAArbitration; /*!< Selects the DMA Tx/Rx arbitration
206+ This parameter can be a value of @ref ETH_DMA_Arbitration */
207+}ETH_InitTypeDef;
208+
209+/**--------------------------------------------------------------------------**/
210+/**
211+ * @brief DMA descriptors types
212+ */
213+/**--------------------------------------------------------------------------**/
214+
215+/**
216+ * @brief ETH DMA Desciptors data structure definition
217+ */
218+typedef struct {
219+ uint32_t Status; /*!< Status */
220+ uint32_t ControlBufferSize; /*!< Control and Buffer1, Buffer2 lengths */
221+ uint32_t Buffer1Addr; /*!< Buffer1 address pointer */
222+ uint32_t Buffer2NextDescAddr; /*!< Buffer2 or next descriptor address pointer */
223+} ETH_DMADESCTypeDef;
224+
225+/**
226+ * @}
227+ */
228+
229+/** @defgroup ETH_Exported_Constants
230+ * @{
231+ */
232+
233+/**
234+ * @brief Uncomment the line below if you want to use user defined Delay function
235+ * (for precise timing), otherwise default _eth_delay_ function defined within
236+ * this driver is used (less precise timing).
237+ */
238+/* #define USE_Delay */
239+
240+#ifdef USE_Delay
241+#include "main.h"
242+ #define _eth_delay_ Delay /*!< User can provide more timing precise _eth_delay_ function */
243+#else
244+ #define _eth_delay_ ETH_Delay /*!< Default _eth_delay_ function with less precise timing */
245+#endif
246+
247+/**--------------------------------------------------------------------------**/
248+/**
249+ * @brief ETH Frames defines
250+ */
251+/**--------------------------------------------------------------------------**/
252+
253+/** @defgroup ENET_Buffers_setting
254+ * @{
255+ */
256+#define ETH_MAX_PACKET_SIZE 1520 /*!< ETH_HEADER + ETH_EXTRA + MAX_ETH_PAYLOAD + ETH_CRC */
257+#define ETH_HEADER 14 /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */
258+#define ETH_CRC 4 /*!< Ethernet CRC */
259+#define ETH_EXTRA 2 /*!< Extra bytes in some cases */
260+#define VLAN_TAG 4 /*!< optional 802.1q VLAN Tag */
261+#define MIN_ETH_PAYLOAD 46 /*!< Minimum Ethernet payload size */
262+#define MAX_ETH_PAYLOAD 1500 /*!< Maximum Ethernet payload size */
263+#define JUMBO_FRAME_PAYLOAD 9000 /*!< Jumbo frame payload size */
264+
265+/**--------------------------------------------------------------------------**/
266+/**
267+ * @brief Ethernet DMA descriptors registers bits definition
268+ */
269+/**--------------------------------------------------------------------------**/
270+
271+/**
272+@code
273+ DMA Tx Desciptor
274+ -----------------------------------------------------------------------------------------------
275+ TDES0 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] |
276+ -----------------------------------------------------------------------------------------------
277+ TDES1 | Reserved[31:29] | Buffer2 ByteCount[28:16] | Reserved[15:13] | Buffer1 ByteCount[12:0] |
278+ -----------------------------------------------------------------------------------------------
279+ TDES2 | Buffer1 Address [31:0] |
280+ -----------------------------------------------------------------------------------------------
281+ TDES3 | Buffer2 Address [31:0] / Next Desciptor Address [31:0] |
282+ -----------------------------------------------------------------------------------------------
283+@endcode
284+*/
285+
286+/**
287+ * @brief Bit definition of TDES0 register: DMA Tx descriptor status register
288+ */
289+#define ETH_DMATxDesc_OWN ((uint32_t)0x80000000) /*!< OWN bit: descriptor is owned by DMA engine */
290+#define ETH_DMATxDesc_IC ((uint32_t)0x40000000) /*!< Interrupt on Completion */
291+#define ETH_DMATxDesc_LS ((uint32_t)0x20000000) /*!< Last Segment */
292+#define ETH_DMATxDesc_FS ((uint32_t)0x10000000) /*!< First Segment */
293+#define ETH_DMATxDesc_DC ((uint32_t)0x08000000) /*!< Disable CRC */
294+#define ETH_DMATxDesc_DP ((uint32_t)0x04000000) /*!< Disable Padding */
295+#define ETH_DMATxDesc_TTSE ((uint32_t)0x02000000) /*!< Transmit Time Stamp Enable */
296+#define ETH_DMATxDesc_CIC ((uint32_t)0x00C00000) /*!< Checksum Insertion Control: 4 cases */
297+#define ETH_DMATxDesc_CIC_ByPass ((uint32_t)0x00000000) /*!< Do Nothing: Checksum Engine is bypassed */
298+#define ETH_DMATxDesc_CIC_IPV4Header ((uint32_t)0x00400000) /*!< IPV4 header Checksum Insertion */
299+#define ETH_DMATxDesc_CIC_TCPUDPICMP_Segment ((uint32_t)0x00800000) /*!< TCP/UDP/ICMP Checksum Insertion calculated over segment only */
300+#define ETH_DMATxDesc_CIC_TCPUDPICMP_Full ((uint32_t)0x00C00000) /*!< TCP/UDP/ICMP Checksum Insertion fully calculated */
301+#define ETH_DMATxDesc_TER ((uint32_t)0x00200000) /*!< Transmit End of Ring */
302+#define ETH_DMATxDesc_TCH ((uint32_t)0x00100000) /*!< Second Address Chained */
303+#define ETH_DMATxDesc_TTSS ((uint32_t)0x00020000) /*!< Tx Time Stamp Status */
304+#define ETH_DMATxDesc_IHE ((uint32_t)0x00010000) /*!< IP Header Error */
305+#define ETH_DMATxDesc_ES ((uint32_t)0x00008000) /*!< Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT */
306+#define ETH_DMATxDesc_JT ((uint32_t)0x00004000) /*!< Jabber Timeout */
307+#define ETH_DMATxDesc_FF ((uint32_t)0x00002000) /*!< Frame Flushed: DMA/MTL flushed the frame due to SW flush */
308+#define ETH_DMATxDesc_PCE ((uint32_t)0x00001000) /*!< Payload Checksum Error */
309+#define ETH_DMATxDesc_LCA ((uint32_t)0x00000800) /*!< Loss of Carrier: carrier lost during tramsmission */
310+#define ETH_DMATxDesc_NC ((uint32_t)0x00000400) /*!< No Carrier: no carrier signal from the tranceiver */
311+#define ETH_DMATxDesc_LCO ((uint32_t)0x00000200) /*!< Late Collision: transmission aborted due to collision */
312+#define ETH_DMATxDesc_EC ((uint32_t)0x00000100) /*!< Excessive Collision: transmission aborted after 16 collisions */
313+#define ETH_DMATxDesc_VF ((uint32_t)0x00000080) /*!< VLAN Frame */
314+#define ETH_DMATxDesc_CC ((uint32_t)0x00000078) /*!< Collision Count */
315+#define ETH_DMATxDesc_ED ((uint32_t)0x00000004) /*!< Excessive Deferral */
316+#define ETH_DMATxDesc_UF ((uint32_t)0x00000002) /*!< Underflow Error: late data arrival from the memory */
317+#define ETH_DMATxDesc_DB ((uint32_t)0x00000001) /*!< Deferred Bit */
318+
319+/**
320+ * @brief Bit definition of TDES1 register
321+ */
322+#define ETH_DMATxDesc_TBS2 ((uint32_t)0x1FFF0000) /*!< Transmit Buffer2 Size */
323+#define ETH_DMATxDesc_TBS1 ((uint32_t)0x00001FFF) /*!< Transmit Buffer1 Size */
324+
325+/**
326+ * @brief Bit definition of TDES2 register
327+ */
328+#define ETH_DMATxDesc_B1AP ((uint32_t)0xFFFFFFFF) /*!< Buffer1 Address Pointer */
329+
330+/**
331+ * @brief Bit definition of TDES3 register
332+ */
333+#define ETH_DMATxDesc_B2AP ((uint32_t)0xFFFFFFFF) /*!< Buffer2 Address Pointer */
334+
335+/**
336+ * @}
337+ */
338+
339+
340+/** @defgroup DMA_Rx_descriptor
341+ * @{
342+ */
343+
344+/**
345+@code
346+ DMA Rx Desciptor
347+ --------------------------------------------------------------------------------------------------------------------
348+ RDES0 | OWN(31) | Status [30:0] |
349+ ---------------------------------------------------------------------------------------------------------------------
350+ RDES1 | CTRL(31) | Reserved[30:29] | Buffer2 ByteCount[28:16] | CTRL[15:14] | Reserved(13) | Buffer1 ByteCount[12:0] |
351+ ---------------------------------------------------------------------------------------------------------------------
352+ RDES2 | Buffer1 Address [31:0] |
353+ ---------------------------------------------------------------------------------------------------------------------
354+ RDES3 | Buffer2 Address [31:0] / Next Desciptor Address [31:0] |
355+ ---------------------------------------------------------------------------------------------------------------------
356+@endcode
357+*/
358+
359+/**
360+ * @brief Bit definition of RDES0 register: DMA Rx descriptor status register
361+ */
362+#define ETH_DMARxDesc_OWN ((uint32_t)0x80000000) /*!< OWN bit: descriptor is owned by DMA engine */
363+#define ETH_DMARxDesc_AFM ((uint32_t)0x40000000) /*!< DA Filter Fail for the rx frame */
364+#define ETH_DMARxDesc_FL ((uint32_t)0x3FFF0000) /*!< Receive descriptor frame length */
365+#define ETH_DMARxDesc_ES ((uint32_t)0x00008000) /*!< Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE */
366+#define ETH_DMARxDesc_DE ((uint32_t)0x00004000) /*!< Desciptor error: no more descriptors for receive frame */
367+#define ETH_DMARxDesc_SAF ((uint32_t)0x00002000) /*!< SA Filter Fail for the received frame */
368+#define ETH_DMARxDesc_LE ((uint32_t)0x00001000) /*!< Frame size not matching with length field */
369+#define ETH_DMARxDesc_OE ((uint32_t)0x00000800) /*!< Overflow Error: Frame was damaged due to buffer overflow */
370+#define ETH_DMARxDesc_VLAN ((uint32_t)0x00000400) /*!< VLAN Tag: received frame is a VLAN frame */
371+#define ETH_DMARxDesc_FS ((uint32_t)0x00000200) /*!< First descriptor of the frame */
372+#define ETH_DMARxDesc_LS ((uint32_t)0x00000100) /*!< Last descriptor of the frame */
373+#define ETH_DMARxDesc_IPV4HCE ((uint32_t)0x00000080) /*!< IPC Checksum Error: Rx Ipv4 header checksum error */
374+#define ETH_DMARxDesc_LC ((uint32_t)0x00000040) /*!< Late collision occurred during reception */
375+#define ETH_DMARxDesc_FT ((uint32_t)0x00000020) /*!< Frame type - Ethernet, otherwise 802.3 */
376+#define ETH_DMARxDesc_RWT ((uint32_t)0x00000010) /*!< Receive Watchdog Timeout: watchdog timer expired during reception */
377+#define ETH_DMARxDesc_RE ((uint32_t)0x00000008) /*!< Receive error: error reported by MII interface */
378+#define ETH_DMARxDesc_DBE ((uint32_t)0x00000004) /*!< Dribble bit error: frame contains non int multiple of 8 bits */
379+#define ETH_DMARxDesc_CE ((uint32_t)0x00000002) /*!< CRC error */
380+#define ETH_DMARxDesc_MAMPCE ((uint32_t)0x00000001) /*!< Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error */
381+
382+/**
383+ * @brief Bit definition of RDES1 register
384+ */
385+#define ETH_DMARxDesc_DIC ((uint32_t)0x80000000) /*!< Disable Interrupt on Completion */
386+#define ETH_DMARxDesc_RBS2 ((uint32_t)0x1FFF0000) /*!< Receive Buffer2 Size */
387+#define ETH_DMARxDesc_RER ((uint32_t)0x00008000) /*!< Receive End of Ring */
388+#define ETH_DMARxDesc_RCH ((uint32_t)0x00004000) /*!< Second Address Chained */
389+#define ETH_DMARxDesc_RBS1 ((uint32_t)0x00001FFF) /*!< Receive Buffer1 Size */
390+
391+/**
392+ * @brief Bit definition of RDES2 register
393+ */
394+#define ETH_DMARxDesc_B1AP ((uint32_t)0xFFFFFFFF) /*!< Buffer1 Address Pointer */
395+
396+/**
397+ * @brief Bit definition of RDES3 register
398+ */
399+#define ETH_DMARxDesc_B2AP ((uint32_t)0xFFFFFFFF) /*!< Buffer2 Address Pointer */
400+
401+/**--------------------------------------------------------------------------**/
402+/**
403+ * @brief Desciption of common PHY registers
404+ */
405+/**--------------------------------------------------------------------------**/
406+
407+/**
408+ * @}
409+ */
410+
411+/** @defgroup PHY_Read_write_Timeouts
412+ * @{
413+ */
414+#define PHY_READ_TO ((uint32_t)0x0004FFFF)
415+#define PHY_WRITE_TO ((uint32_t)0x0004FFFF)
416+
417+/**
418+ * @}
419+ */
420+
421+/** @defgroup PHY_Reset_Delay
422+ * @{
423+ */
424+#define PHY_ResetDelay ((uint32_t)0x000FFFFF)
425+
426+/**
427+ * @}
428+ */
429+
430+/** @defgroup PHY_Config_Delay
431+ * @{
432+ */
433+#define PHY_ConfigDelay ((uint32_t)0x00FFFFFF)
434+
435+/**
436+ * @}
437+ */
438+
439+/** @defgroup PHY_Register_address
440+ * @{
441+ */
442+#define PHY_BCR 0 /*!< Tranceiver Basic Control Register */
443+#define PHY_BSR 1 /*!< Tranceiver Basic Status Register */
444+
445+/**
446+ * @}
447+ */
448+
449+/** @defgroup PHY_basic_Control_register
450+ * @{
451+ */
452+#define PHY_Reset ((u16)0x8000) /*!< PHY Reset */
453+#define PHY_Loopback ((u16)0x4000) /*!< Select loop-back mode */
454+#define PHY_FULLDUPLEX_100M ((u16)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */
455+#define PHY_HALFDUPLEX_100M ((u16)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */
456+#define PHY_FULLDUPLEX_10M ((u16)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */
457+#define PHY_HALFDUPLEX_10M ((u16)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */
458+#define PHY_AutoNegotiation ((u16)0x1000) /*!< Enable auto-negotiation function */
459+#define PHY_Restart_AutoNegotiation ((u16)0x0200) /*!< Restart auto-negotiation function */
460+#define PHY_Powerdown ((u16)0x0800) /*!< Select the power down mode */
461+#define PHY_Isolate ((u16)0x0400) /*!< Isolate PHY from MII */
462+
463+/**
464+ * @}
465+ */
466+
467+/** @defgroup PHY_basic_status_register
468+ * @{
469+ */
470+#define PHY_AutoNego_Complete ((u16)0x0020) /*!< Auto-Negotioation process completed */
471+#define PHY_Linked_Status ((u16)0x0004) /*!< Valid link established */
472+#define PHY_Jabber_detection ((u16)0x0002) /*!< Jabber condition detected */
473+
474+/**
475+ * @}
476+ */
477+
478+/** @defgroup PHY_status_register
479+ * @{
480+ */
481+/* The PHY status register value change from a PHY to another so the user have
482+ to update this value depending on the used external PHY */
483+/**
484+ * @brief For LAN8700
485+ */
486+//#define PHY_SR 31 /*!< Tranceiver Status Register */
487+/**
488+ * @brief For DP83848
489+ */
490+#define PHY_SR 16 /*!< Tranceiver Status Register */
491+
492+/* The Speed and Duplex mask values change from a PHY to another so the user have to update
493+ this value depending on the used external PHY */
494+/**
495+ * @brief For LAN8700
496+ */
497+//#define PHY_Speed_Status ((u16)0x0004) /*!< Configured information of Speed: 10Mbps */
498+//#define PHY_Duplex_Status ((u16)0x0010) /*!< Configured information of Duplex: Full-duplex */
499+
500+/**
501+ * @brief For DP83848
502+ */
503+#define PHY_Speed_Status ((u16)0x0002) /*!< Configured information of Speed: 10Mbps */
504+#define PHY_Duplex_Status ((u16)0x0004) /*!< Configured information of Duplex: Full-duplex */
505+#define IS_ETH_PHY_ADDRESS(ADDRESS) ((ADDRESS) <= 0x20)
506+#define IS_ETH_PHY_REG(REG) (((REG) == PHY_BCR) || \
507+ ((REG) == PHY_BSR) || \
508+ ((REG) == PHY_SR))
509+
510+/**--------------------------------------------------------------------------**/
511+/**
512+ * @brief MAC defines
513+ */
514+/**--------------------------------------------------------------------------**/
515+
516+/**
517+ * @}
518+ */
519+
520+/** @defgroup ETH_AutoNegotiation
521+ * @{
522+ */
523+#define ETH_AutoNegotiation_Enable ((uint32_t)0x00000001)
524+#define ETH_AutoNegotiation_Disable ((uint32_t)0x00000000)
525+#define IS_ETH_AUTONEGOTIATION(CMD) (((CMD) == ETH_AutoNegotiation_Enable) || \
526+ ((CMD) == ETH_AutoNegotiation_Disable))
527+
528+/**
529+ * @}
530+ */
531+
532+/** @defgroup ETH_watchdog
533+ * @{
534+ */
535+#define ETH_Watchdog_Enable ((uint32_t)0x00000000)
536+#define ETH_Watchdog_Disable ((uint32_t)0x00800000)
537+#define IS_ETH_WATCHDOG(CMD) (((CMD) == ETH_Watchdog_Enable) || \
538+ ((CMD) == ETH_Watchdog_Disable))
539+
540+/**
541+ * @}
542+ */
543+
544+/** @defgroup ETH_Jabber
545+ * @{
546+ */
547+#define ETH_Jabber_Enable ((uint32_t)0x00000000)
548+#define ETH_Jabber_Disable ((uint32_t)0x00400000)
549+#define IS_ETH_JABBER(CMD) (((CMD) == ETH_Jabber_Enable) || \
550+ ((CMD) == ETH_Jabber_Disable))
551+
552+/**
553+ * @}
554+ */
555+
556+/** @defgroup ETH_Inter_Frame_Gap
557+ * @{
558+ */
559+#define ETH_InterFrameGap_96Bit ((uint32_t)0x00000000) /*!< minimum IFG between frames during transmission is 96Bit */
560+#define ETH_InterFrameGap_88Bit ((uint32_t)0x00020000) /*!< minimum IFG between frames during transmission is 88Bit */
561+#define ETH_InterFrameGap_80Bit ((uint32_t)0x00040000) /*!< minimum IFG between frames during transmission is 80Bit */
562+#define ETH_InterFrameGap_72Bit ((uint32_t)0x00060000) /*!< minimum IFG between frames during transmission is 72Bit */
563+#define ETH_InterFrameGap_64Bit ((uint32_t)0x00080000) /*!< minimum IFG between frames during transmission is 64Bit */
564+#define ETH_InterFrameGap_56Bit ((uint32_t)0x000A0000) /*!< minimum IFG between frames during transmission is 56Bit */
565+#define ETH_InterFrameGap_48Bit ((uint32_t)0x000C0000) /*!< minimum IFG between frames during transmission is 48Bit */
566+#define ETH_InterFrameGap_40Bit ((uint32_t)0x000E0000) /*!< minimum IFG between frames during transmission is 40Bit */
567+#define IS_ETH_INTER_FRAME_GAP(GAP) (((GAP) == ETH_InterFrameGap_96Bit) || \
568+ ((GAP) == ETH_InterFrameGap_88Bit) || \
569+ ((GAP) == ETH_InterFrameGap_80Bit) || \
570+ ((GAP) == ETH_InterFrameGap_72Bit) || \
571+ ((GAP) == ETH_InterFrameGap_64Bit) || \
572+ ((GAP) == ETH_InterFrameGap_56Bit) || \
573+ ((GAP) == ETH_InterFrameGap_48Bit) || \
574+ ((GAP) == ETH_InterFrameGap_40Bit))
575+
576+/**
577+ * @}
578+ */
579+
580+/** @defgroup ETH_Carrier_Sense
581+ * @{
582+ */
583+#define ETH_CarrierSense_Enable ((uint32_t)0x00000000)
584+#define ETH_CarrierSense_Disable ((uint32_t)0x00010000)
585+#define IS_ETH_CARRIER_SENSE(CMD) (((CMD) == ETH_CarrierSense_Enable) || \
586+ ((CMD) == ETH_CarrierSense_Disable))
587+
588+/**
589+ * @}
590+ */
591+
592+/** @defgroup ETH_Speed
593+ * @{
594+ */
595+#define ETH_Speed_10M ((uint32_t)0x00000000)
596+#define ETH_Speed_100M ((uint32_t)0x00004000)
597+#define IS_ETH_SPEED(SPEED) (((SPEED) == ETH_Speed_10M) || \
598+ ((SPEED) == ETH_Speed_100M))
599+
600+/**
601+ * @}
602+ */
603+
604+/** @defgroup ETH_Receive_Own
605+ * @{
606+ */
607+#define ETH_ReceiveOwn_Enable ((uint32_t)0x00000000)
608+#define ETH_ReceiveOwn_Disable ((uint32_t)0x00002000)
609+#define IS_ETH_RECEIVE_OWN(CMD) (((CMD) == ETH_ReceiveOwn_Enable) || \
610+ ((CMD) == ETH_ReceiveOwn_Disable))
611+
612+/**
613+ * @}
614+ */
615+
616+/** @defgroup ETH_Loop_Back_Mode
617+ * @{
618+ */
619+#define ETH_LoopbackMode_Enable ((uint32_t)0x00001000)
620+#define ETH_LoopbackMode_Disable ((uint32_t)0x00000000)
621+#define IS_ETH_LOOPBACK_MODE(CMD) (((CMD) == ETH_LoopbackMode_Enable) || \
622+ ((CMD) == ETH_LoopbackMode_Disable))
623+
624+/**
625+ * @}
626+ */
627+
628+/** @defgroup ETH_Duplex_Mode
629+ * @{
630+ */
631+#define ETH_Mode_FullDuplex ((uint32_t)0x00000800)
632+#define ETH_Mode_HalfDuplex ((uint32_t)0x00000000)
633+#define IS_ETH_DUPLEX_MODE(MODE) (((MODE) == ETH_Mode_FullDuplex) || \
634+ ((MODE) == ETH_Mode_HalfDuplex))
635+
636+/**
637+ * @}
638+ */
639+
640+/** @defgroup ETH_Checksum_Offload
641+ * @{
642+ */
643+#define ETH_ChecksumOffload_Enable ((uint32_t)0x00000400)
644+#define ETH_ChecksumOffload_Disable ((uint32_t)0x00000000)
645+#define IS_ETH_CHECKSUM_OFFLOAD(CMD) (((CMD) == ETH_ChecksumOffload_Enable) || \
646+ ((CMD) == ETH_ChecksumOffload_Disable))
647+
648+/**
649+ * @}
650+ */
651+
652+/** @defgroup ETH_Retry_Transmission
653+ * @{
654+ */
655+#define ETH_RetryTransmission_Enable ((uint32_t)0x00000000)
656+#define ETH_RetryTransmission_Disable ((uint32_t)0x00000200)
657+#define IS_ETH_RETRY_TRANSMISSION(CMD) (((CMD) == ETH_RetryTransmission_Enable) || \
658+ ((CMD) == ETH_RetryTransmission_Disable))
659+
660+/**
661+ * @}
662+ */
663+
664+/** @defgroup ETH_Automatic_Pad_CRC_Strip
665+ * @{
666+ */
667+#define ETH_AutomaticPadCRCStrip_Enable ((uint32_t)0x00000080)
668+#define ETH_AutomaticPadCRCStrip_Disable ((uint32_t)0x00000000)
669+#define IS_ETH_AUTOMATIC_PADCRC_STRIP(CMD) (((CMD) == ETH_AutomaticPadCRCStrip_Enable) || \
670+ ((CMD) == ETH_AutomaticPadCRCStrip_Disable))
671+
672+/**
673+ * @}
674+ */
675+
676+/** @defgroup ETH_Back_Off_Limit
677+ * @{
678+ */
679+#define ETH_BackOffLimit_10 ((uint32_t)0x00000000)
680+#define ETH_BackOffLimit_8 ((uint32_t)0x00000020)
681+#define ETH_BackOffLimit_4 ((uint32_t)0x00000040)
682+#define ETH_BackOffLimit_1 ((uint32_t)0x00000060)
683+#define IS_ETH_BACKOFF_LIMIT(LIMIT) (((LIMIT) == ETH_BackOffLimit_10) || \
684+ ((LIMIT) == ETH_BackOffLimit_8) || \
685+ ((LIMIT) == ETH_BackOffLimit_4) || \
686+ ((LIMIT) == ETH_BackOffLimit_1))
687+
688+/**
689+ * @}
690+ */
691+
692+/** @defgroup ETH_Deferral_Check
693+ * @{
694+ */
695+#define ETH_DeferralCheck_Enable ((uint32_t)0x00000010)
696+#define ETH_DeferralCheck_Disable ((uint32_t)0x00000000)
697+#define IS_ETH_DEFERRAL_CHECK(CMD) (((CMD) == ETH_DeferralCheck_Enable) || \
698+ ((CMD) == ETH_DeferralCheck_Disable))
699+
700+/**
701+ * @}
702+ */
703+
704+/** @defgroup ETH_Receive_All
705+ * @{
706+ */
707+#define ETH_ReceiveAll_Enable ((uint32_t)0x80000000)
708+#define ETH_ReceiveAll_Disable ((uint32_t)0x00000000)
709+#define IS_ETH_RECEIVE_ALL(CMD) (((CMD) == ETH_ReceiveAll_Enable) || \
710+ ((CMD) == ETH_ReceiveAll_Disable))
711+
712+/**
713+ * @}
714+ */
715+
716+/** @defgroup ETH_Source_Addr_Filter
717+ * @{
718+ */
719+#define ETH_SourceAddrFilter_Normal_Enable ((uint32_t)0x00000200)
720+#define ETH_SourceAddrFilter_Inverse_Enable ((uint32_t)0x00000300)
721+#define ETH_SourceAddrFilter_Disable ((uint32_t)0x00000000)
722+#define IS_ETH_SOURCE_ADDR_FILTER(CMD) (((CMD) == ETH_SourceAddrFilter_Normal_Enable) || \
723+ ((CMD) == ETH_SourceAddrFilter_Inverse_Enable) || \
724+ ((CMD) == ETH_SourceAddrFilter_Disable))
725+
726+/**
727+ * @}
728+ */
729+
730+/** @defgroup ETH_Pass_Control_Frames
731+ * @{
732+ */
733+#define ETH_PassControlFrames_BlockAll ((uint32_t)0x00000040) /*!< MAC filters all control frames from reaching the application */
734+#define ETH_PassControlFrames_ForwardAll ((uint32_t)0x00000080) /*!< MAC forwards all control frames to application even if they fail the Address Filter */
735+#define ETH_PassControlFrames_ForwardPassedAddrFilter ((uint32_t)0x000000C0) /*!< MAC forwards control frames that pass the Address Filter. */
736+#define IS_ETH_CONTROL_FRAMES(PASS) (((PASS) == ETH_PassControlFrames_BlockAll) || \
737+ ((PASS) == ETH_PassControlFrames_ForwardAll) || \
738+ ((PASS) == ETH_PassControlFrames_ForwardPassedAddrFilter))
739+
740+/**
741+ * @}
742+ */
743+
744+/** @defgroup ETH_Broadcast_Frames_Reception
745+ * @{
746+ */
747+#define ETH_BroadcastFramesReception_Enable ((uint32_t)0x00000000)
748+#define ETH_BroadcastFramesReception_Disable ((uint32_t)0x00000020)
749+#define IS_ETH_BROADCAST_FRAMES_RECEPTION(CMD) (((CMD) == ETH_BroadcastFramesReception_Enable) || \
750+ ((CMD) == ETH_BroadcastFramesReception_Disable))
751+
752+/**
753+ * @}
754+ */
755+
756+/** @defgroup ETH_Destination_Addr_Filter
757+ * @{
758+ */
759+#define ETH_DestinationAddrFilter_Normal ((uint32_t)0x00000000)
760+#define ETH_DestinationAddrFilter_Inverse ((uint32_t)0x00000008)
761+#define IS_ETH_DESTINATION_ADDR_FILTER(FILTER) (((FILTER) == ETH_DestinationAddrFilter_Normal) || \
762+ ((FILTER) == ETH_DestinationAddrFilter_Inverse))
763+
764+/**
765+ * @}
766+ */
767+
768+/** @defgroup ETH_Promiscuous_Mode
769+ * @{
770+ */
771+#define ETH_PromiscuousMode_Enable ((uint32_t)0x00000001)
772+#define ETH_PromiscuousMode_Disable ((uint32_t)0x00000000)
773+#define IS_ETH_PROMISCUOUS_MODE(CMD) (((CMD) == ETH_PromiscuousMode_Enable) || \
774+ ((CMD) == ETH_PromiscuousMode_Disable))
775+
776+/**
777+ * @}
778+ */
779+
780+/** @defgroup ETH_Multicast_Frames_Filter
781+ * @{
782+ */
783+#define ETH_MulticastFramesFilter_PerfectHashTable ((uint32_t)0x00000404)
784+#define ETH_MulticastFramesFilter_HashTable ((uint32_t)0x00000004)
785+#define ETH_MulticastFramesFilter_Perfect ((uint32_t)0x00000000)
786+#define ETH_MulticastFramesFilter_None ((uint32_t)0x00000010)
787+#define IS_ETH_MULTICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_MulticastFramesFilter_PerfectHashTable) || \
788+ ((FILTER) == ETH_MulticastFramesFilter_HashTable) || \
789+ ((FILTER) == ETH_MulticastFramesFilter_Perfect) || \
790+ ((FILTER) == ETH_MulticastFramesFilter_None))
791+
792+
793+/**
794+ * @}
795+ */
796+
797+/** @defgroup ETH_Unicast_Frames_Filter
798+ * @{
799+ */
800+#define ETH_UnicastFramesFilter_PerfectHashTable ((uint32_t)0x00000402)
801+#define ETH_UnicastFramesFilter_HashTable ((uint32_t)0x00000002)
802+#define ETH_UnicastFramesFilter_Perfect ((uint32_t)0x00000000)
803+#define IS_ETH_UNICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_UnicastFramesFilter_PerfectHashTable) || \
804+ ((FILTER) == ETH_UnicastFramesFilter_HashTable) || \
805+ ((FILTER) == ETH_UnicastFramesFilter_Perfect))
806+
807+/**
808+ * @}
809+ */
810+
811+/** @defgroup ETH_Pause_Time
812+ * @{
813+ */
814+#define IS_ETH_PAUSE_TIME(TIME) ((TIME) <= 0xFFFF)
815+
816+/**
817+ * @}
818+ */
819+
820+/** @defgroup ETH_Zero_Quanta_Pause
821+ * @{
822+ */
823+#define ETH_ZeroQuantaPause_Enable ((uint32_t)0x00000000)
824+#define ETH_ZeroQuantaPause_Disable ((uint32_t)0x00000080)
825+#define IS_ETH_ZEROQUANTA_PAUSE(CMD) (((CMD) == ETH_ZeroQuantaPause_Enable) || \
826+ ((CMD) == ETH_ZeroQuantaPause_Disable))
827+/**
828+ * @}
829+ */
830+
831+/** @defgroup ETH_Pause_Low_Threshold
832+ * @{
833+ */
834+#define ETH_PauseLowThreshold_Minus4 ((uint32_t)0x00000000) /*!< Pause time minus 4 slot times */
835+#define ETH_PauseLowThreshold_Minus28 ((uint32_t)0x00000010) /*!< Pause time minus 28 slot times */
836+#define ETH_PauseLowThreshold_Minus144 ((uint32_t)0x00000020) /*!< Pause time minus 144 slot times */
837+#define ETH_PauseLowThreshold_Minus256 ((uint32_t)0x00000030) /*!< Pause time minus 256 slot times */
838+#define IS_ETH_PAUSE_LOW_THRESHOLD(THRESHOLD) (((THRESHOLD) == ETH_PauseLowThreshold_Minus4) || \
839+ ((THRESHOLD) == ETH_PauseLowThreshold_Minus28) || \
840+ ((THRESHOLD) == ETH_PauseLowThreshold_Minus144) || \
841+ ((THRESHOLD) == ETH_PauseLowThreshold_Minus256))
842+
843+/**
844+ * @}
845+ */
846+
847+/** @defgroup ETH_Unicast_Pause_Frame_Detect
848+ * @{
849+ */
850+#define ETH_UnicastPauseFrameDetect_Enable ((uint32_t)0x00000008)
851+#define ETH_UnicastPauseFrameDetect_Disable ((uint32_t)0x00000000)
852+#define IS_ETH_UNICAST_PAUSE_FRAME_DETECT(CMD) (((CMD) == ETH_UnicastPauseFrameDetect_Enable) || \
853+ ((CMD) == ETH_UnicastPauseFrameDetect_Disable))
854+
855+/**
856+ * @}
857+ */
858+
859+/** @defgroup ETH_Receive_Flow_Control
860+ * @{
861+ */
862+#define ETH_ReceiveFlowControl_Enable ((uint32_t)0x00000004)
863+#define ETH_ReceiveFlowControl_Disable ((uint32_t)0x00000000)
864+#define IS_ETH_RECEIVE_FLOWCONTROL(CMD) (((CMD) == ETH_ReceiveFlowControl_Enable) || \
865+ ((CMD) == ETH_ReceiveFlowControl_Disable))
866+
867+/**
868+ * @}
869+ */
870+
871+/** @defgroup ETH_Transmit_Flow_Control
872+ * @{
873+ */
874+#define ETH_TransmitFlowControl_Enable ((uint32_t)0x00000002)
875+#define ETH_TransmitFlowControl_Disable ((uint32_t)0x00000000)
876+#define IS_ETH_TRANSMIT_FLOWCONTROL(CMD) (((CMD) == ETH_TransmitFlowControl_Enable) || \
877+ ((CMD) == ETH_TransmitFlowControl_Disable))
878+
879+/**
880+ * @}
881+ */
882+
883+/** @defgroup ETH_VLAN_Tag_Comparison
884+ * @{
885+ */
886+#define ETH_VLANTagComparison_12Bit ((uint32_t)0x00010000)
887+#define ETH_VLANTagComparison_16Bit ((uint32_t)0x00000000)
888+#define IS_ETH_VLAN_TAG_COMPARISON(COMPARISON) (((COMPARISON) == ETH_VLANTagComparison_12Bit) || \
889+ ((COMPARISON) == ETH_VLANTagComparison_16Bit))
890+#define IS_ETH_VLAN_TAG_IDENTIFIER(IDENTIFIER) ((IDENTIFIER) <= 0xFFFF)
891+
892+/**
893+ * @}
894+ */
895+
896+/** @defgroup ETH_MAC_Flags
897+ * @{
898+ */
899+#define ETH_MAC_FLAG_TST ((uint32_t)0x00000200) /*!< Time stamp trigger flag (on MAC) */
900+#define ETH_MAC_FLAG_MMCT ((uint32_t)0x00000040) /*!< MMC transmit flag */
901+#define ETH_MAC_FLAG_MMCR ((uint32_t)0x00000020) /*!< MMC receive flag */
902+#define ETH_MAC_FLAG_MMC ((uint32_t)0x00000010) /*!< MMC flag (on MAC) */
903+#define ETH_MAC_FLAG_PMT ((uint32_t)0x00000008) /*!< PMT flag (on MAC) */
904+#define IS_ETH_MAC_GET_FLAG(FLAG) (((FLAG) == ETH_MAC_FLAG_TST) || ((FLAG) == ETH_MAC_FLAG_MMCT) || \
905+ ((FLAG) == ETH_MAC_FLAG_MMCR) || ((FLAG) == ETH_MAC_FLAG_MMC) || \
906+ ((FLAG) == ETH_MAC_FLAG_PMT))
907+/**
908+ * @}
909+ */
910+
911+/** @defgroup ETH_MAC_Interrupts
912+ * @{
913+ */
914+#define ETH_MAC_IT_TST ((uint32_t)0x00000200) /*!< Time stamp trigger interrupt (on MAC) */
915+#define ETH_MAC_IT_MMCT ((uint32_t)0x00000040) /*!< MMC transmit interrupt */
916+#define ETH_MAC_IT_MMCR ((uint32_t)0x00000020) /*!< MMC receive interrupt */
917+#define ETH_MAC_IT_MMC ((uint32_t)0x00000010) /*!< MMC interrupt (on MAC) */
918+#define ETH_MAC_IT_PMT ((uint32_t)0x00000008) /*!< PMT interrupt (on MAC) */
919+#define IS_ETH_MAC_IT(IT) ((((IT) & (uint32_t)0xFFFFFDF7) == 0x00) && ((IT) != 0x00))
920+#define IS_ETH_MAC_GET_IT(IT) (((IT) == ETH_MAC_IT_TST) || ((IT) == ETH_MAC_IT_MMCT) || \
921+ ((IT) == ETH_MAC_IT_MMCR) || ((IT) == ETH_MAC_IT_MMC) || \
922+ ((IT) == ETH_MAC_IT_PMT))
923+/**
924+ * @}
925+ */
926+
927+/** @defgroup ETH_MAC_addresses
928+ * @{
929+ */
930+#define ETH_MAC_Address0 ((uint32_t)0x00000000)
931+#define ETH_MAC_Address1 ((uint32_t)0x00000008)
932+#define ETH_MAC_Address2 ((uint32_t)0x00000010)
933+#define ETH_MAC_Address3 ((uint32_t)0x00000018)
934+#define IS_ETH_MAC_ADDRESS0123(ADDRESS) (((ADDRESS) == ETH_MAC_Address0) || \
935+ ((ADDRESS) == ETH_MAC_Address1) || \
936+ ((ADDRESS) == ETH_MAC_Address2) || \
937+ ((ADDRESS) == ETH_MAC_Address3))
938+#define IS_ETH_MAC_ADDRESS123(ADDRESS) (((ADDRESS) == ETH_MAC_Address1) || \
939+ ((ADDRESS) == ETH_MAC_Address2) || \
940+ ((ADDRESS) == ETH_MAC_Address3))
941+/**
942+ * @}
943+ */
944+
945+/** @defgroup ETH_MAC_addresses_filter_SA_DA_filed_of_received_frames
946+ * @{
947+ */
948+#define ETH_MAC_AddressFilter_SA ((uint32_t)0x00000000)
949+#define ETH_MAC_AddressFilter_DA ((uint32_t)0x00000008)
950+#define IS_ETH_MAC_ADDRESS_FILTER(FILTER) (((FILTER) == ETH_MAC_AddressFilter_SA) || \
951+ ((FILTER) == ETH_MAC_AddressFilter_DA))
952+/**
953+ * @}
954+ */
955+
956+/** @defgroup ETH_MAC_addresses_filter_Mask_bytes
957+ * @{
958+ */
959+#define ETH_MAC_AddressMask_Byte6 ((uint32_t)0x20000000) /*!< Mask MAC Address high reg bits [15:8] */
960+#define ETH_MAC_AddressMask_Byte5 ((uint32_t)0x10000000) /*!< Mask MAC Address high reg bits [7:0] */
961+#define ETH_MAC_AddressMask_Byte4 ((uint32_t)0x08000000) /*!< Mask MAC Address low reg bits [31:24] */
962+#define ETH_MAC_AddressMask_Byte3 ((uint32_t)0x04000000) /*!< Mask MAC Address low reg bits [23:16] */
963+#define ETH_MAC_AddressMask_Byte2 ((uint32_t)0x02000000) /*!< Mask MAC Address low reg bits [15:8] */
964+#define ETH_MAC_AddressMask_Byte1 ((uint32_t)0x01000000) /*!< Mask MAC Address low reg bits [70] */
965+#define IS_ETH_MAC_ADDRESS_MASK(MASK) (((MASK) == ETH_MAC_AddressMask_Byte6) || \
966+ ((MASK) == ETH_MAC_AddressMask_Byte5) || \
967+ ((MASK) == ETH_MAC_AddressMask_Byte4) || \
968+ ((MASK) == ETH_MAC_AddressMask_Byte3) || \
969+ ((MASK) == ETH_MAC_AddressMask_Byte2) || \
970+ ((MASK) == ETH_MAC_AddressMask_Byte1))
971+
972+/**--------------------------------------------------------------------------**/
973+/**
974+ * @brief Ethernet DMA Desciptors defines
975+ */
976+/**--------------------------------------------------------------------------**/
977+/**
978+ * @}
979+ */
980+
981+/** @defgroup ETH_DMA_Tx_descriptor_flags
982+ * @{
983+ */
984+#define IS_ETH_DMATxDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMATxDesc_OWN) || \
985+ ((FLAG) == ETH_DMATxDesc_IC) || \
986+ ((FLAG) == ETH_DMATxDesc_LS) || \
987+ ((FLAG) == ETH_DMATxDesc_FS) || \
988+ ((FLAG) == ETH_DMATxDesc_DC) || \
989+ ((FLAG) == ETH_DMATxDesc_DP) || \
990+ ((FLAG) == ETH_DMATxDesc_TTSE) || \
991+ ((FLAG) == ETH_DMATxDesc_TER) || \
992+ ((FLAG) == ETH_DMATxDesc_TCH) || \
993+ ((FLAG) == ETH_DMATxDesc_TTSS) || \
994+ ((FLAG) == ETH_DMATxDesc_IHE) || \
995+ ((FLAG) == ETH_DMATxDesc_ES) || \
996+ ((FLAG) == ETH_DMATxDesc_JT) || \
997+ ((FLAG) == ETH_DMATxDesc_FF) || \
998+ ((FLAG) == ETH_DMATxDesc_PCE) || \
999+ ((FLAG) == ETH_DMATxDesc_LCA) || \
1000+ ((FLAG) == ETH_DMATxDesc_NC) || \
1001+ ((FLAG) == ETH_DMATxDesc_LCO) || \
1002+ ((FLAG) == ETH_DMATxDesc_EC) || \
1003+ ((FLAG) == ETH_DMATxDesc_VF) || \
1004+ ((FLAG) == ETH_DMATxDesc_CC) || \
1005+ ((FLAG) == ETH_DMATxDesc_ED) || \
1006+ ((FLAG) == ETH_DMATxDesc_UF) || \
1007+ ((FLAG) == ETH_DMATxDesc_DB))
1008+
1009+/**
1010+ * @}
1011+ */
1012+
1013+/** @defgroup ETH_DMA_Tx_descriptor_segment
1014+ * @{
1015+ */
1016+#define ETH_DMATxDesc_LastSegment ((uint32_t)0x40000000) /*!< Last Segment */
1017+#define ETH_DMATxDesc_FirstSegment ((uint32_t)0x20000000) /*!< First Segment */
1018+#define IS_ETH_DMA_TXDESC_SEGMENT(SEGMENT) (((SEGMENT) == ETH_DMATxDesc_LastSegment) || \
1019+ ((SEGMENT) == ETH_DMATxDesc_FirstSegment))
1020+
1021+/**
1022+ * @}
1023+ */
1024+
1025+/** @defgroup ETH_DMA_Tx_descriptor_Checksum_Insertion_Control
1026+ * @{
1027+ */
1028+#define ETH_DMATxDesc_ChecksumByPass ((uint32_t)0x00000000) /*!< Checksum engine bypass */
1029+#define ETH_DMATxDesc_ChecksumIPV4Header ((uint32_t)0x00400000) /*!< IPv4 header checksum insertion */
1030+#define ETH_DMATxDesc_ChecksumTCPUDPICMPSegment ((uint32_t)0x00800000) /*!< TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present */
1031+#define ETH_DMATxDesc_ChecksumTCPUDPICMPFull ((uint32_t)0x00C00000) /*!< TCP/UDP/ICMP checksum fully in hardware including pseudo header */
1032+#define IS_ETH_DMA_TXDESC_CHECKSUM(CHECKSUM) (((CHECKSUM) == ETH_DMATxDesc_ChecksumByPass) || \
1033+ ((CHECKSUM) == ETH_DMATxDesc_ChecksumIPV4Header) || \
1034+ ((CHECKSUM) == ETH_DMATxDesc_ChecksumTCPUDPICMPSegment) || \
1035+ ((CHECKSUM) == ETH_DMATxDesc_ChecksumTCPUDPICMPFull))
1036+/**
1037+ * @brief ETH DMA Tx Desciptor buffer size
1038+ */
1039+#define IS_ETH_DMATxDESC_BUFFER_SIZE(SIZE) ((SIZE) <= 0x1FFF)
1040+
1041+/**
1042+ * @}
1043+ */
1044+
1045+/** @defgroup ETH_DMA_Rx_descriptor_flags
1046+ * @{
1047+ */
1048+#define IS_ETH_DMARxDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMARxDesc_OWN) || \
1049+ ((FLAG) == ETH_DMARxDesc_AFM) || \
1050+ ((FLAG) == ETH_DMARxDesc_ES) || \
1051+ ((FLAG) == ETH_DMARxDesc_DE) || \
1052+ ((FLAG) == ETH_DMARxDesc_SAF) || \
1053+ ((FLAG) == ETH_DMARxDesc_LE) || \
1054+ ((FLAG) == ETH_DMARxDesc_OE) || \
1055+ ((FLAG) == ETH_DMARxDesc_VLAN) || \
1056+ ((FLAG) == ETH_DMARxDesc_FS) || \
1057+ ((FLAG) == ETH_DMARxDesc_LS) || \
1058+ ((FLAG) == ETH_DMARxDesc_IPV4HCE) || \
1059+ ((FLAG) == ETH_DMARxDesc_LC) || \
1060+ ((FLAG) == ETH_DMARxDesc_FT) || \
1061+ ((FLAG) == ETH_DMARxDesc_RWT) || \
1062+ ((FLAG) == ETH_DMARxDesc_RE) || \
1063+ ((FLAG) == ETH_DMARxDesc_DBE) || \
1064+ ((FLAG) == ETH_DMARxDesc_CE) || \
1065+ ((FLAG) == ETH_DMARxDesc_MAMPCE))
1066+
1067+/**
1068+ * @}
1069+ */
1070+
1071+/** @defgroup ETH_DMA_Rx_descriptor_buffers_
1072+ * @{
1073+ */
1074+#define ETH_DMARxDesc_Buffer1 ((uint32_t)0x00000000) /*!< DMA Rx Desc Buffer1 */
1075+#define ETH_DMARxDesc_Buffer2 ((uint32_t)0x00000001) /*!< DMA Rx Desc Buffer2 */
1076+#define IS_ETH_DMA_RXDESC_BUFFER(BUFFER) (((BUFFER) == ETH_DMARxDesc_Buffer1) || \
1077+ ((BUFFER) == ETH_DMARxDesc_Buffer2))
1078+
1079+/**--------------------------------------------------------------------------**/
1080+/**
1081+ * @brief Ethernet DMA defines
1082+ */
1083+/**--------------------------------------------------------------------------**/
1084+/**
1085+ * @}
1086+ */
1087+
1088+/** @defgroup ETH_Drop_TCP_IP_Checksum_Error_Frame
1089+ * @{
1090+ */
1091+#define ETH_DropTCPIPChecksumErrorFrame_Enable ((uint32_t)0x00000000)
1092+#define ETH_DropTCPIPChecksumErrorFrame_Disable ((uint32_t)0x04000000)
1093+#define IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(CMD) (((CMD) == ETH_DropTCPIPChecksumErrorFrame_Enable) || \
1094+ ((CMD) == ETH_DropTCPIPChecksumErrorFrame_Disable))
1095+/**
1096+ * @}
1097+ */
1098+
1099+/** @defgroup ETH_Receive_Store_Forward
1100+ * @{
1101+ */
1102+#define ETH_ReceiveStoreForward_Enable ((uint32_t)0x02000000)
1103+#define ETH_ReceiveStoreForward_Disable ((uint32_t)0x00000000)
1104+#define IS_ETH_RECEIVE_STORE_FORWARD(CMD) (((CMD) == ETH_ReceiveStoreForward_Enable) || \
1105+ ((CMD) == ETH_ReceiveStoreForward_Disable))
1106+/**
1107+ * @}
1108+ */
1109+
1110+/** @defgroup ETH_Flush_Received_Frame
1111+ * @{
1112+ */
1113+#define ETH_FlushReceivedFrame_Enable ((uint32_t)0x00000000)
1114+#define ETH_FlushReceivedFrame_Disable ((uint32_t)0x01000000)
1115+#define IS_ETH_FLUSH_RECEIVE_FRAME(CMD) (((CMD) == ETH_FlushReceivedFrame_Enable) || \
1116+ ((CMD) == ETH_FlushReceivedFrame_Disable))
1117+/**
1118+ * @}
1119+ */
1120+
1121+/** @defgroup ETH_Transmit_Store_Forward
1122+ * @{
1123+ */
1124+#define ETH_TransmitStoreForward_Enable ((uint32_t)0x00200000)
1125+#define ETH_TransmitStoreForward_Disable ((uint32_t)0x00000000)
1126+#define IS_ETH_TRANSMIT_STORE_FORWARD(CMD) (((CMD) == ETH_TransmitStoreForward_Enable) || \
1127+ ((CMD) == ETH_TransmitStoreForward_Disable))
1128+/**
1129+ * @}
1130+ */
1131+
1132+/** @defgroup ETH_Transmit_Threshold_Control
1133+ * @{
1134+ */
1135+#define ETH_TransmitThresholdControl_64Bytes ((uint32_t)0x00000000) /*!< threshold level of the MTL Transmit FIFO is 64 Bytes */
1136+#define ETH_TransmitThresholdControl_128Bytes ((uint32_t)0x00004000) /*!< threshold level of the MTL Transmit FIFO is 128 Bytes */
1137+#define ETH_TransmitThresholdControl_192Bytes ((uint32_t)0x00008000) /*!< threshold level of the MTL Transmit FIFO is 192 Bytes */
1138+#define ETH_TransmitThresholdControl_256Bytes ((uint32_t)0x0000C000) /*!< threshold level of the MTL Transmit FIFO is 256 Bytes */
1139+#define ETH_TransmitThresholdControl_40Bytes ((uint32_t)0x00010000) /*!< threshold level of the MTL Transmit FIFO is 40 Bytes */
1140+#define ETH_TransmitThresholdControl_32Bytes ((uint32_t)0x00014000) /*!< threshold level of the MTL Transmit FIFO is 32 Bytes */
1141+#define ETH_TransmitThresholdControl_24Bytes ((uint32_t)0x00018000) /*!< threshold level of the MTL Transmit FIFO is 24 Bytes */
1142+#define ETH_TransmitThresholdControl_16Bytes ((uint32_t)0x0001C000) /*!< threshold level of the MTL Transmit FIFO is 16 Bytes */
1143+#define IS_ETH_TRANSMIT_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_TransmitThresholdControl_64Bytes) || \
1144+ ((THRESHOLD) == ETH_TransmitThresholdControl_128Bytes) || \
1145+ ((THRESHOLD) == ETH_TransmitThresholdControl_192Bytes) || \
1146+ ((THRESHOLD) == ETH_TransmitThresholdControl_256Bytes) || \
1147+ ((THRESHOLD) == ETH_TransmitThresholdControl_40Bytes) || \
1148+ ((THRESHOLD) == ETH_TransmitThresholdControl_32Bytes) || \
1149+ ((THRESHOLD) == ETH_TransmitThresholdControl_24Bytes) || \
1150+ ((THRESHOLD) == ETH_TransmitThresholdControl_16Bytes))
1151+/**
1152+ * @}
1153+ */
1154+
1155+/** @defgroup ETH_Forward_Error_Frames
1156+ * @{
1157+ */
1158+#define ETH_ForwardErrorFrames_Enable ((uint32_t)0x00000080)
1159+#define ETH_ForwardErrorFrames_Disable ((uint32_t)0x00000000)
1160+#define IS_ETH_FORWARD_ERROR_FRAMES(CMD) (((CMD) == ETH_ForwardErrorFrames_Enable) || \
1161+ ((CMD) == ETH_ForwardErrorFrames_Disable))
1162+/**
1163+ * @}
1164+ */
1165+
1166+/** @defgroup ETH_Forward_Undersized_Good_Frames
1167+ * @{
1168+ */
1169+#define ETH_ForwardUndersizedGoodFrames_Enable ((uint32_t)0x00000040)
1170+#define ETH_ForwardUndersizedGoodFrames_Disable ((uint32_t)0x00000000)
1171+#define IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(CMD) (((CMD) == ETH_ForwardUndersizedGoodFrames_Enable) || \
1172+ ((CMD) == ETH_ForwardUndersizedGoodFrames_Disable))
1173+
1174+/**
1175+ * @}
1176+ */
1177+
1178+/** @defgroup ETH_Receive_Threshold_Control
1179+ * @{
1180+ */
1181+#define ETH_ReceiveThresholdControl_64Bytes ((uint32_t)0x00000000) /*!< threshold level of the MTL Receive FIFO is 64 Bytes */
1182+#define ETH_ReceiveThresholdControl_32Bytes ((uint32_t)0x00000008) /*!< threshold level of the MTL Receive FIFO is 32 Bytes */
1183+#define ETH_ReceiveThresholdControl_96Bytes ((uint32_t)0x00000010) /*!< threshold level of the MTL Receive FIFO is 96 Bytes */
1184+#define ETH_ReceiveThresholdControl_128Bytes ((uint32_t)0x00000018) /*!< threshold level of the MTL Receive FIFO is 128 Bytes */
1185+#define IS_ETH_RECEIVE_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_ReceiveThresholdControl_64Bytes) || \
1186+ ((THRESHOLD) == ETH_ReceiveThresholdControl_32Bytes) || \
1187+ ((THRESHOLD) == ETH_ReceiveThresholdControl_96Bytes) || \
1188+ ((THRESHOLD) == ETH_ReceiveThresholdControl_128Bytes))
1189+/**
1190+ * @}
1191+ */
1192+
1193+/** @defgroup ETH_Second_Frame_Operate
1194+ * @{
1195+ */
1196+#define ETH_SecondFrameOperate_Enable ((uint32_t)0x00000004)
1197+#define ETH_SecondFrameOperate_Disable ((uint32_t)0x00000000)
1198+#define IS_ETH_SECOND_FRAME_OPERATE(CMD) (((CMD) == ETH_SecondFrameOperate_Enable) || \
1199+ ((CMD) == ETH_SecondFrameOperate_Disable))
1200+
1201+/**
1202+ * @}
1203+ */
1204+
1205+/** @defgroup ETH_Address_Aligned_Beats
1206+ * @{
1207+ */
1208+#define ETH_AddressAlignedBeats_Enable ((uint32_t)0x02000000)
1209+#define ETH_AddressAlignedBeats_Disable ((uint32_t)0x00000000)
1210+#define IS_ETH_ADDRESS_ALIGNED_BEATS(CMD) (((CMD) == ETH_AddressAlignedBeats_Enable) || \
1211+ ((CMD) == ETH_AddressAlignedBeats_Disable))
1212+
1213+/**
1214+ * @}
1215+ */
1216+
1217+/** @defgroup ETH_Fixed_Burst
1218+ * @{
1219+ */
1220+#define ETH_FixedBurst_Enable ((uint32_t)0x00010000)
1221+#define ETH_FixedBurst_Disable ((uint32_t)0x00000000)
1222+#define IS_ETH_FIXED_BURST(CMD) (((CMD) == ETH_FixedBurst_Enable) || \
1223+ ((CMD) == ETH_FixedBurst_Disable))
1224+
1225+/**
1226+ * @}
1227+ */
1228+
1229+/** @defgroup ETH_Rx_DMA_Burst_Length
1230+ * @{
1231+ */
1232+#define ETH_RxDMABurstLength_1Beat ((uint32_t)0x00020000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 1 */
1233+#define ETH_RxDMABurstLength_2Beat ((uint32_t)0x00040000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 2 */
1234+#define ETH_RxDMABurstLength_4Beat ((uint32_t)0x00080000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */
1235+#define ETH_RxDMABurstLength_8Beat ((uint32_t)0x00100000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */
1236+#define ETH_RxDMABurstLength_16Beat ((uint32_t)0x00200000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */
1237+#define ETH_RxDMABurstLength_32Beat ((uint32_t)0x00400000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */
1238+#define ETH_RxDMABurstLength_4xPBL_4Beat ((uint32_t)0x01020000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */
1239+#define ETH_RxDMABurstLength_4xPBL_8Beat ((uint32_t)0x01040000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */
1240+#define ETH_RxDMABurstLength_4xPBL_16Beat ((uint32_t)0x01080000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */
1241+#define ETH_RxDMABurstLength_4xPBL_32Beat ((uint32_t)0x01100000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */
1242+#define ETH_RxDMABurstLength_4xPBL_64Beat ((uint32_t)0x01200000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 64 */
1243+#define ETH_RxDMABurstLength_4xPBL_128Beat ((uint32_t)0x01400000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 128 */
1244+#define IS_ETH_RXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_RxDMABurstLength_1Beat) || \
1245+ ((LENGTH) == ETH_RxDMABurstLength_2Beat) || \
1246+ ((LENGTH) == ETH_RxDMABurstLength_4Beat) || \
1247+ ((LENGTH) == ETH_RxDMABurstLength_8Beat) || \
1248+ ((LENGTH) == ETH_RxDMABurstLength_16Beat) || \
1249+ ((LENGTH) == ETH_RxDMABurstLength_32Beat) || \
1250+ ((LENGTH) == ETH_RxDMABurstLength_4xPBL_4Beat) || \
1251+ ((LENGTH) == ETH_RxDMABurstLength_4xPBL_8Beat) || \
1252+ ((LENGTH) == ETH_RxDMABurstLength_4xPBL_16Beat) || \
1253+ ((LENGTH) == ETH_RxDMABurstLength_4xPBL_32Beat) || \
1254+ ((LENGTH) == ETH_RxDMABurstLength_4xPBL_64Beat) || \
1255+ ((LENGTH) == ETH_RxDMABurstLength_4xPBL_128Beat))
1256+
1257+/**
1258+ * @}
1259+ */
1260+
1261+/** @defgroup ETH_Tx_DMA_Burst_Length
1262+ * @{
1263+ */
1264+#define ETH_TxDMABurstLength_1Beat ((uint32_t)0x00000100) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
1265+#define ETH_TxDMABurstLength_2Beat ((uint32_t)0x00000200) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
1266+#define ETH_TxDMABurstLength_4Beat ((uint32_t)0x00000400) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
1267+#define ETH_TxDMABurstLength_8Beat ((uint32_t)0x00000800) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
1268+#define ETH_TxDMABurstLength_16Beat ((uint32_t)0x00001000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
1269+#define ETH_TxDMABurstLength_32Beat ((uint32_t)0x00002000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
1270+#define ETH_TxDMABurstLength_4xPBL_4Beat ((uint32_t)0x01000100) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
1271+#define ETH_TxDMABurstLength_4xPBL_8Beat ((uint32_t)0x01000200) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
1272+#define ETH_TxDMABurstLength_4xPBL_16Beat ((uint32_t)0x01000400) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
1273+#define ETH_TxDMABurstLength_4xPBL_32Beat ((uint32_t)0x01000800) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
1274+#define ETH_TxDMABurstLength_4xPBL_64Beat ((uint32_t)0x01001000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
1275+#define ETH_TxDMABurstLength_4xPBL_128Beat ((uint32_t)0x01002000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
1276+#define IS_ETH_TXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_TxDMABurstLength_1Beat) || \
1277+ ((LENGTH) == ETH_TxDMABurstLength_2Beat) || \
1278+ ((LENGTH) == ETH_TxDMABurstLength_4Beat) || \
1279+ ((LENGTH) == ETH_TxDMABurstLength_8Beat) || \
1280+ ((LENGTH) == ETH_TxDMABurstLength_16Beat) || \
1281+ ((LENGTH) == ETH_TxDMABurstLength_32Beat) || \
1282+ ((LENGTH) == ETH_TxDMABurstLength_4xPBL_4Beat) || \
1283+ ((LENGTH) == ETH_TxDMABurstLength_4xPBL_8Beat) || \
1284+ ((LENGTH) == ETH_TxDMABurstLength_4xPBL_16Beat) || \
1285+ ((LENGTH) == ETH_TxDMABurstLength_4xPBL_32Beat) || \
1286+ ((LENGTH) == ETH_TxDMABurstLength_4xPBL_64Beat) || \
1287+ ((LENGTH) == ETH_TxDMABurstLength_4xPBL_128Beat))
1288+/**
1289+ * @brief ETH DMA Desciptor SkipLength
1290+ */
1291+#define IS_ETH_DMA_DESC_SKIP_LENGTH(LENGTH) ((LENGTH) <= 0x1F)
1292+
1293+/**
1294+ * @}
1295+ */
1296+
1297+/** @defgroup ETH_DMA_Arbitration
1298+ * @{
1299+ */
1300+#define ETH_DMAArbitration_RoundRobin_RxTx_1_1 ((uint32_t)0x00000000)
1301+#define ETH_DMAArbitration_RoundRobin_RxTx_2_1 ((uint32_t)0x00004000)
1302+#define ETH_DMAArbitration_RoundRobin_RxTx_3_1 ((uint32_t)0x00008000)
1303+#define ETH_DMAArbitration_RoundRobin_RxTx_4_1 ((uint32_t)0x0000C000)
1304+#define ETH_DMAArbitration_RxPriorTx ((uint32_t)0x00000002)
1305+#define IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(RATIO) (((RATIO) == ETH_DMAArbitration_RoundRobin_RxTx_1_1) || \
1306+ ((RATIO) == ETH_DMAArbitration_RoundRobin_RxTx_2_1) || \
1307+ ((RATIO) == ETH_DMAArbitration_RoundRobin_RxTx_3_1) || \
1308+ ((RATIO) == ETH_DMAArbitration_RoundRobin_RxTx_4_1) || \
1309+ ((RATIO) == ETH_DMAArbitration_RxPriorTx))
1310+/**
1311+ * @}
1312+ */
1313+
1314+/** @defgroup ETH_DMA_Flags
1315+ * @{
1316+ */
1317+#define ETH_DMA_FLAG_TST ((uint32_t)0x20000000) /*!< Time-stamp trigger interrupt (on DMA) */
1318+#define ETH_DMA_FLAG_PMT ((uint32_t)0x10000000) /*!< PMT interrupt (on DMA) */
1319+#define ETH_DMA_FLAG_MMC ((uint32_t)0x08000000) /*!< MMC interrupt (on DMA) */
1320+#define ETH_DMA_FLAG_DataTransferError ((uint32_t)0x00800000) /*!< Error bits 0-Rx DMA, 1-Tx DMA */
1321+#define ETH_DMA_FLAG_ReadWriteError ((uint32_t)0x01000000) /*!< Error bits 0-write trnsf, 1-read transfr */
1322+#define ETH_DMA_FLAG_AccessError ((uint32_t)0x02000000) /*!< Error bits 0-data buffer, 1-desc. access */
1323+#define ETH_DMA_FLAG_NIS ((uint32_t)0x00010000) /*!< Normal interrupt summary flag */
1324+#define ETH_DMA_FLAG_AIS ((uint32_t)0x00008000) /*!< Abnormal interrupt summary flag */
1325+#define ETH_DMA_FLAG_ER ((uint32_t)0x00004000) /*!< Early receive flag */
1326+#define ETH_DMA_FLAG_FBE ((uint32_t)0x00002000) /*!< Fatal bus error flag */
1327+#define ETH_DMA_FLAG_ET ((uint32_t)0x00000400) /*!< Early transmit flag */
1328+#define ETH_DMA_FLAG_RWT ((uint32_t)0x00000200) /*!< Receive watchdog timeout flag */
1329+#define ETH_DMA_FLAG_RPS ((uint32_t)0x00000100) /*!< Receive process stopped flag */
1330+#define ETH_DMA_FLAG_RBU ((uint32_t)0x00000080) /*!< Receive buffer unavailable flag */
1331+#define ETH_DMA_FLAG_R ((uint32_t)0x00000040) /*!< Receive flag */
1332+#define ETH_DMA_FLAG_TU ((uint32_t)0x00000020) /*!< Underflow flag */
1333+#define ETH_DMA_FLAG_RO ((uint32_t)0x00000010) /*!< Overflow flag */
1334+#define ETH_DMA_FLAG_TJT ((uint32_t)0x00000008) /*!< Transmit jabber timeout flag */
1335+#define ETH_DMA_FLAG_TBU ((uint32_t)0x00000004) /*!< Transmit buffer unavailable flag */
1336+#define ETH_DMA_FLAG_TPS ((uint32_t)0x00000002) /*!< Transmit process stopped flag */
1337+#define ETH_DMA_FLAG_T ((uint32_t)0x00000001) /*!< Transmit flag */
1338+
1339+#define IS_ETH_DMA_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFE1800) == 0x00) && ((FLAG) != 0x00))
1340+#define IS_ETH_DMA_GET_FLAG(FLAG) (((FLAG) == ETH_DMA_FLAG_TST) || ((FLAG) == ETH_DMA_FLAG_PMT) || \
1341+ ((FLAG) == ETH_DMA_FLAG_MMC) || ((FLAG) == ETH_DMA_FLAG_DataTransferError) || \
1342+ ((FLAG) == ETH_DMA_FLAG_ReadWriteError) || ((FLAG) == ETH_DMA_FLAG_AccessError) || \
1343+ ((FLAG) == ETH_DMA_FLAG_NIS) || ((FLAG) == ETH_DMA_FLAG_AIS) || \
1344+ ((FLAG) == ETH_DMA_FLAG_ER) || ((FLAG) == ETH_DMA_FLAG_FBE) || \
1345+ ((FLAG) == ETH_DMA_FLAG_ET) || ((FLAG) == ETH_DMA_FLAG_RWT) || \
1346+ ((FLAG) == ETH_DMA_FLAG_RPS) || ((FLAG) == ETH_DMA_FLAG_RBU) || \
1347+ ((FLAG) == ETH_DMA_FLAG_R) || ((FLAG) == ETH_DMA_FLAG_TU) || \
1348+ ((FLAG) == ETH_DMA_FLAG_RO) || ((FLAG) == ETH_DMA_FLAG_TJT) || \
1349+ ((FLAG) == ETH_DMA_FLAG_TBU) || ((FLAG) == ETH_DMA_FLAG_TPS) || \
1350+ ((FLAG) == ETH_DMA_FLAG_T))
1351+/**
1352+ * @}
1353+ */
1354+
1355+/** @defgroup ETH_DMA_Interrupts
1356+ * @{
1357+ */
1358+#define ETH_DMA_IT_TST ((uint32_t)0x20000000) /*!< Time-stamp trigger interrupt (on DMA) */
1359+#define ETH_DMA_IT_PMT ((uint32_t)0x10000000) /*!< PMT interrupt (on DMA) */
1360+#define ETH_DMA_IT_MMC ((uint32_t)0x08000000) /*!< MMC interrupt (on DMA) */
1361+#define ETH_DMA_IT_NIS ((uint32_t)0x00010000) /*!< Normal interrupt summary */
1362+#define ETH_DMA_IT_AIS ((uint32_t)0x00008000) /*!< Abnormal interrupt summary */
1363+#define ETH_DMA_IT_ER ((uint32_t)0x00004000) /*!< Early receive interrupt */
1364+#define ETH_DMA_IT_FBE ((uint32_t)0x00002000) /*!< Fatal bus error interrupt */
1365+#define ETH_DMA_IT_ET ((uint32_t)0x00000400) /*!< Early transmit interrupt */
1366+#define ETH_DMA_IT_RWT ((uint32_t)0x00000200) /*!< Receive watchdog timeout interrupt */
1367+#define ETH_DMA_IT_RPS ((uint32_t)0x00000100) /*!< Receive process stopped interrupt */
1368+#define ETH_DMA_IT_RBU ((uint32_t)0x00000080) /*!< Receive buffer unavailable interrupt */
1369+#define ETH_DMA_IT_R ((uint32_t)0x00000040) /*!< Receive interrupt */
1370+#define ETH_DMA_IT_TU ((uint32_t)0x00000020) /*!< Underflow interrupt */
1371+#define ETH_DMA_IT_RO ((uint32_t)0x00000010) /*!< Overflow interrupt */
1372+#define ETH_DMA_IT_TJT ((uint32_t)0x00000008) /*!< Transmit jabber timeout interrupt */
1373+#define ETH_DMA_IT_TBU ((uint32_t)0x00000004) /*!< Transmit buffer unavailable interrupt */
1374+#define ETH_DMA_IT_TPS ((uint32_t)0x00000002) /*!< Transmit process stopped interrupt */
1375+#define ETH_DMA_IT_T ((uint32_t)0x00000001) /*!< Transmit interrupt */
1376+
1377+#define IS_ETH_DMA_IT(IT) ((((IT) & (uint32_t)0xFFFE1800) == 0x00) && ((IT) != 0x00))
1378+#define IS_ETH_DMA_GET_IT(IT) (((IT) == ETH_DMA_IT_TST) || ((IT) == ETH_DMA_IT_PMT) || \
1379+ ((IT) == ETH_DMA_IT_MMC) || ((IT) == ETH_DMA_IT_NIS) || \
1380+ ((IT) == ETH_DMA_IT_AIS) || ((IT) == ETH_DMA_IT_ER) || \
1381+ ((IT) == ETH_DMA_IT_FBE) || ((IT) == ETH_DMA_IT_ET) || \
1382+ ((IT) == ETH_DMA_IT_RWT) || ((IT) == ETH_DMA_IT_RPS) || \
1383+ ((IT) == ETH_DMA_IT_RBU) || ((IT) == ETH_DMA_IT_R) || \
1384+ ((IT) == ETH_DMA_IT_TU) || ((IT) == ETH_DMA_IT_RO) || \
1385+ ((IT) == ETH_DMA_IT_TJT) || ((IT) == ETH_DMA_IT_TBU) || \
1386+ ((IT) == ETH_DMA_IT_TPS) || ((IT) == ETH_DMA_IT_T))
1387+
1388+/**
1389+ * @}
1390+ */
1391+
1392+/** @defgroup ETH_DMA_transmit_process_state_
1393+ * @{
1394+ */
1395+#define ETH_DMA_TransmitProcess_Stopped ((uint32_t)0x00000000) /*!< Stopped - Reset or Stop Tx Command issued */
1396+#define ETH_DMA_TransmitProcess_Fetching ((uint32_t)0x00100000) /*!< Running - fetching the Tx descriptor */
1397+#define ETH_DMA_TransmitProcess_Waiting ((uint32_t)0x00200000) /*!< Running - waiting for status */
1398+#define ETH_DMA_TransmitProcess_Reading ((uint32_t)0x00300000) /*!< Running - reading the data from host memory */
1399+#define ETH_DMA_TransmitProcess_Suspended ((uint32_t)0x00600000) /*!< Suspended - Tx Desciptor unavailabe */
1400+#define ETH_DMA_TransmitProcess_Closing ((uint32_t)0x00700000) /*!< Running - closing Rx descriptor */
1401+
1402+/**
1403+ * @}
1404+ */
1405+
1406+
1407+/** @defgroup ETH_DMA_receive_process_state_
1408+ * @{
1409+ */
1410+#define ETH_DMA_ReceiveProcess_Stopped ((uint32_t)0x00000000) /*!< Stopped - Reset or Stop Rx Command issued */
1411+#define ETH_DMA_ReceiveProcess_Fetching ((uint32_t)0x00020000) /*!< Running - fetching the Rx descriptor */
1412+#define ETH_DMA_ReceiveProcess_Waiting ((uint32_t)0x00060000) /*!< Running - waiting for packet */
1413+#define ETH_DMA_ReceiveProcess_Suspended ((uint32_t)0x00080000) /*!< Suspended - Rx Desciptor unavailable */
1414+#define ETH_DMA_ReceiveProcess_Closing ((uint32_t)0x000A0000) /*!< Running - closing descriptor */
1415+#define ETH_DMA_ReceiveProcess_Queuing ((uint32_t)0x000E0000) /*!< Running - queuing the recieve frame into host memory */
1416+
1417+/**
1418+ * @}
1419+ */
1420+
1421+/** @defgroup ETH_DMA_overflow_
1422+ * @{
1423+ */
1424+#define ETH_DMA_Overflow_RxFIFOCounter ((uint32_t)0x10000000) /*!< Overflow bit for FIFO overflow counter */
1425+#define ETH_DMA_Overflow_MissedFrameCounter ((uint32_t)0x00010000) /*!< Overflow bit for missed frame counter */
1426+#define IS_ETH_DMA_GET_OVERFLOW(OVERFLOW) (((OVERFLOW) == ETH_DMA_Overflow_RxFIFOCounter) || \
1427+ ((OVERFLOW) == ETH_DMA_Overflow_MissedFrameCounter))
1428+
1429+/**--------------------------------------------------------------------------**/
1430+/**
1431+ * @brief Ethernet PMT defines
1432+ */
1433+/**--------------------------------------------------------------------------**/
1434+/**
1435+ * @}
1436+ */
1437+
1438+/** @defgroup ETH_PMT_Flags
1439+ * @{
1440+ */
1441+#define ETH_PMT_FLAG_WUFFRPR ((uint32_t)0x80000000) /*!< Wake-Up Frame Filter Register Poniter Reset */
1442+#define ETH_PMT_FLAG_WUFR ((uint32_t)0x00000040) /*!< Wake-Up Frame Received */
1443+#define ETH_PMT_FLAG_MPR ((uint32_t)0x00000020) /*!< Magic Packet Received */
1444+#define IS_ETH_PMT_GET_FLAG(FLAG) (((FLAG) == ETH_PMT_FLAG_WUFR) || \
1445+ ((FLAG) == ETH_PMT_FLAG_MPR))
1446+
1447+/**--------------------------------------------------------------------------**/
1448+/**
1449+ * @brief Ethernet MMC defines
1450+ */
1451+/**--------------------------------------------------------------------------**/
1452+/**
1453+ * @}
1454+ */
1455+
1456+/** @defgroup ETH_MMC_Tx_Interrupts
1457+ * @{
1458+ */
1459+#define ETH_MMC_IT_TGF ((uint32_t)0x00200000) /*!< When Tx good frame counter reaches half the maximum value */
1460+#define ETH_MMC_IT_TGFMSC ((uint32_t)0x00008000) /*!< When Tx good multi col counter reaches half the maximum value */
1461+#define ETH_MMC_IT_TGFSC ((uint32_t)0x00004000) /*!< When Tx good single col counter reaches half the maximum value */
1462+
1463+/**
1464+ * @}
1465+ */
1466+
1467+/** @defgroup ETH_MMC_Rx_Interrupts
1468+ * @{
1469+ */
1470+#define ETH_MMC_IT_RGUF ((uint32_t)0x10020000) /*!< When Rx good unicast frames counter reaches half the maximum value */
1471+#define ETH_MMC_IT_RFAE ((uint32_t)0x10000040) /*!< When Rx alignment error counter reaches half the maximum value */
1472+#define ETH_MMC_IT_RFCE ((uint32_t)0x10000020) /*!< When Rx crc error counter reaches half the maximum value */
1473+#define IS_ETH_MMC_IT(IT) (((((IT) & (uint32_t)0xFFDF3FFF) == 0x00) || (((IT) & (uint32_t)0xEFFDFF9F) == 0x00)) && \
1474+ ((IT) != 0x00))
1475+#define IS_ETH_MMC_GET_IT(IT) (((IT) == ETH_MMC_IT_TGF) || ((IT) == ETH_MMC_IT_TGFMSC) || \
1476+ ((IT) == ETH_MMC_IT_TGFSC) || ((IT) == ETH_MMC_IT_RGUF) || \
1477+ ((IT) == ETH_MMC_IT_RFAE) || ((IT) == ETH_MMC_IT_RFCE))
1478+/**
1479+ * @}
1480+ */
1481+
1482+/** @defgroup ETH_MMC_Registers
1483+ * @{
1484+ */
1485+#define ETH_MMCCR ((uint32_t)0x00000100) /*!< MMC CR register */
1486+#define ETH_MMCRIR ((uint32_t)0x00000104) /*!< MMC RIR register */
1487+#define ETH_MMCTIR ((uint32_t)0x00000108) /*!< MMC TIR register */
1488+#define ETH_MMCRIMR ((uint32_t)0x0000010C) /*!< MMC RIMR register */
1489+#define ETH_MMCTIMR ((uint32_t)0x00000110) /*!< MMC TIMR register */
1490+#define ETH_MMCTGFSCCR ((uint32_t)0x0000014C) /*!< MMC TGFSCCR register */
1491+#define ETH_MMCTGFMSCCR ((uint32_t)0x00000150) /*!< MMC TGFMSCCR register */
1492+#define ETH_MMCTGFCR ((uint32_t)0x00000168) /*!< MMC TGFCR register */
1493+#define ETH_MMCRFCECR ((uint32_t)0x00000194) /*!< MMC RFCECR register */
1494+#define ETH_MMCRFAECR ((uint32_t)0x00000198) /*!< MMC RFAECR register */
1495+#define ETH_MMCRGUFCR ((uint32_t)0x000001C4) /*!< MMC RGUFCR register */
1496+
1497+/**
1498+ * @brief ETH MMC registers
1499+ */
1500+#define IS_ETH_MMC_REGISTER(REG) (((REG) == ETH_MMCCR) || ((REG) == ETH_MMCRIR) || \
1501+ ((REG) == ETH_MMCTIR) || ((REG) == ETH_MMCRIMR) || \
1502+ ((REG) == ETH_MMCTIMR) || ((REG) == ETH_MMCTGFSCCR) || \
1503+ ((REG) == ETH_MMCTGFMSCCR) || ((REG) == ETH_MMCTGFCR) || \
1504+ ((REG) == ETH_MMCRFCECR) || ((REG) == ETH_MMCRFAECR) || \
1505+ ((REG) == ETH_MMCRGUFCR))
1506+
1507+/**--------------------------------------------------------------------------**/
1508+/**
1509+ * @brief Ethernet PTP defines
1510+ */
1511+/**--------------------------------------------------------------------------**/
1512+/**
1513+ * @}
1514+ */
1515+
1516+/** @defgroup ETH_PTP_time_update_method
1517+ * @{
1518+ */
1519+#define ETH_PTP_FineUpdate ((uint32_t)0x00000001) /*!< Fine Update method */
1520+#define ETH_PTP_CoarseUpdate ((uint32_t)0x00000000) /*!< Coarse Update method */
1521+#define IS_ETH_PTP_UPDATE(UPDATE) (((UPDATE) == ETH_PTP_FineUpdate) || \
1522+ ((UPDATE) == ETH_PTP_CoarseUpdate))
1523+
1524+/**
1525+ * @}
1526+ */
1527+
1528+
1529+/** @defgroup ETH_PTP_Flags
1530+ * @{
1531+ */
1532+#define ETH_PTP_FLAG_TSARU ((uint32_t)0x00000020) /*!< Addend Register Update */
1533+#define ETH_PTP_FLAG_TSITE ((uint32_t)0x00000010) /*!< Time Stamp Interrupt Trigger */
1534+#define ETH_PTP_FLAG_TSSTU ((uint32_t)0x00000008) /*!< Time Stamp Update */
1535+#define ETH_PTP_FLAG_TSSTI ((uint32_t)0x00000004) /*!< Time Stamp Initialize */
1536+#define IS_ETH_PTP_GET_FLAG(FLAG) (((FLAG) == ETH_PTP_FLAG_TSARU) || \
1537+ ((FLAG) == ETH_PTP_FLAG_TSITE) || \
1538+ ((FLAG) == ETH_PTP_FLAG_TSSTU) || \
1539+ ((FLAG) == ETH_PTP_FLAG_TSSTI))
1540+/**
1541+ * @brief ETH PTP subsecond increment
1542+ */
1543+#define IS_ETH_PTP_SUBSECOND_INCREMENT(SUBSECOND) ((SUBSECOND) <= 0xFF)
1544+
1545+/**
1546+ * @}
1547+ */
1548+
1549+
1550+/** @defgroup ETH_PTP_time_sign
1551+ * @{
1552+ */
1553+#define ETH_PTP_PositiveTime ((uint32_t)0x00000000) /*!< Positive time value */
1554+#define ETH_PTP_NegativeTime ((uint32_t)0x80000000) /*!< Negative time value */
1555+#define IS_ETH_PTP_TIME_SIGN(SIGN) (((SIGN) == ETH_PTP_PositiveTime) || \
1556+ ((SIGN) == ETH_PTP_NegativeTime))
1557+
1558+/**
1559+ * @brief ETH PTP time stamp low update
1560+ */
1561+#define IS_ETH_PTP_TIME_STAMP_UPDATE_SUBSECOND(SUBSECOND) ((SUBSECOND) <= 0x7FFFFFFF)
1562+
1563+/**
1564+ * @brief ETH PTP registers
1565+ */
1566+#define ETH_PTPTSCR ((uint32_t)0x00000700) /*!< PTP TSCR register */
1567+#define ETH_PTPSSIR ((uint32_t)0x00000704) /*!< PTP SSIR register */
1568+#define ETH_PTPTSHR ((uint32_t)0x00000708) /*!< PTP TSHR register */
1569+#define ETH_PTPTSLR ((uint32_t)0x0000070C) /*!< PTP TSLR register */
1570+#define ETH_PTPTSHUR ((uint32_t)0x00000710) /*!< PTP TSHUR register */
1571+#define ETH_PTPTSLUR ((uint32_t)0x00000714) /*!< PTP TSLUR register */
1572+#define ETH_PTPTSAR ((uint32_t)0x00000718) /*!< PTP TSAR register */
1573+#define ETH_PTPTTHR ((uint32_t)0x0000071C) /*!< PTP TTHR register */
1574+#define ETH_PTPTTLR ((uint32_t)0x00000720) /* PTP TTLR register */
1575+#define IS_ETH_PTP_REGISTER(REG) (((REG) == ETH_PTPTSCR) || ((REG) == ETH_PTPSSIR) || \
1576+ ((REG) == ETH_PTPTSHR) || ((REG) == ETH_PTPTSLR) || \
1577+ ((REG) == ETH_PTPTSHUR) || ((REG) == ETH_PTPTSLUR) || \
1578+ ((REG) == ETH_PTPTSAR) || ((REG) == ETH_PTPTTHR) || \
1579+ ((REG) == ETH_PTPTTLR))
1580+
1581+/**
1582+ * @}
1583+ */
1584+
1585+
1586+/**
1587+ * @}
1588+ */
1589+
1590+/** @defgroup ETH_Exported_Macros
1591+ * @{
1592+ */
1593+/**
1594+ * @}
1595+ */
1596+
1597+/** @defgroup ETH_Exported_Functions
1598+ * @{
1599+ */
1600+void ETH_DeInit(void);
1601+uint32_t ETH_Init(ETH_InitTypeDef* ETH_InitStruct, u16 PHYAddress);
1602+void ETH_StructInit(ETH_InitTypeDef* ETH_InitStruct);
1603+void ETH_SoftwareReset(void);
1604+FlagStatus ETH_GetSoftwareResetStatus(void);
1605+void ETH_Start(void);
1606+uint32_t ETH_HandleTxPkt(u8 *ppkt, u16 FrameLength);
1607+uint32_t ETH_HandleRxPkt(u8 *ppkt);
1608+uint32_t ETH_GetRxPktSize(void);
1609+void ETH_DropRxPkt(void);
1610+
1611+/**
1612+ * @brief PHY
1613+ */
1614+u16 ETH_ReadPHYRegister(u16 PHYAddress, u16 PHYReg);
1615+uint32_t ETH_WritePHYRegister(u16 PHYAddress, u16 PHYReg, u16 PHYValue);
1616+uint32_t ETH_PHYLoopBackCmd(u16 PHYAddress, FunctionalState NewState);
1617+
1618+/**
1619+ * @brief MAC
1620+ */
1621+void ETH_MACTransmissionCmd(FunctionalState NewState);
1622+void ETH_MACReceptionCmd(FunctionalState NewState);
1623+FlagStatus ETH_GetFlowControlBusyStatus(void);
1624+void ETH_InitiatePauseControlFrame(void);
1625+void ETH_BackPressureActivationCmd(FunctionalState NewState);
1626+FlagStatus ETH_GetMACFlagStatus(uint32_t ETH_MAC_FLAG);
1627+ITStatus ETH_GetMACITStatus(uint32_t ETH_MAC_IT);
1628+void ETH_MACITConfig(uint32_t ETH_MAC_IT, FunctionalState NewState);
1629+void ETH_MACAddressConfig(uint32_t MacAddr, u8 *Addr);
1630+void ETH_GetMACAddress(uint32_t MacAddr, u8 *Addr);
1631+void ETH_MACAddressPerfectFilterCmd(uint32_t MacAddr, FunctionalState NewState);
1632+void ETH_MACAddressFilterConfig(uint32_t MacAddr, uint32_t Filter);
1633+void ETH_MACAddressMaskBytesFilterConfig(uint32_t MacAddr, uint32_t MaskByte);
1634+
1635+/**
1636+ * @brief DMA Tx/Rx descriptors
1637+ */
1638+void ETH_DMATxDescChainInit(ETH_DMADESCTypeDef *DMATxDescTab, u8 *TxBuff, uint32_t TxBuffCount);
1639+void ETH_DMATxDescRingInit(ETH_DMADESCTypeDef *DMATxDescTab, u8 *TxBuff1, u8 *TxBuff2, uint32_t TxBuffCount);
1640+FlagStatus ETH_GetDMATxDescFlagStatus(ETH_DMADESCTypeDef *DMATxDesc, uint32_t ETH_DMATxDescFlag);
1641+uint32_t ETH_GetDMATxDescCollisionCount(ETH_DMADESCTypeDef *DMATxDesc);
1642+void ETH_SetDMATxDescOwnBit(ETH_DMADESCTypeDef *DMATxDesc);
1643+void ETH_DMATxDescTransmitITConfig(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState);
1644+void ETH_DMATxDescFrameSegmentConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t DMATxDesc_FrameSegment);
1645+void ETH_DMATxDescChecksumInsertionConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t DMATxDesc_Checksum);
1646+void ETH_DMATxDescCRCCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState);
1647+void ETH_DMATxDescEndOfRingCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState);
1648+void ETH_DMATxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState);
1649+void ETH_DMATxDescShortFramePaddingCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState);
1650+void ETH_DMATxDescTimeStampCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState);
1651+void ETH_DMATxDescBufferSizeConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t BufferSize1, uint32_t BufferSize2);
1652+void ETH_DMARxDescChainInit(ETH_DMADESCTypeDef *DMARxDescTab, u8 *RxBuff, uint32_t RxBuffCount);
1653+void ETH_DMARxDescRingInit(ETH_DMADESCTypeDef *DMARxDescTab, u8 *RxBuff1, u8 *RxBuff2, uint32_t RxBuffCount);
1654+FlagStatus ETH_GetDMARxDescFlagStatus(ETH_DMADESCTypeDef *DMARxDesc, uint32_t ETH_DMARxDescFlag);
1655+void ETH_SetDMARxDescOwnBit(ETH_DMADESCTypeDef *DMARxDesc);
1656+uint32_t ETH_GetDMARxDescFrameLength(ETH_DMADESCTypeDef *DMARxDesc);
1657+void ETH_DMARxDescReceiveITConfig(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState);
1658+void ETH_DMARxDescEndOfRingCmd(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState);
1659+void ETH_DMARxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState);
1660+uint32_t ETH_GetDMARxDescBufferSize(ETH_DMADESCTypeDef *DMARxDesc, uint32_t DMARxDesc_Buffer);
1661+
1662+/**
1663+ * @brief DMA
1664+ */
1665+FlagStatus ETH_GetDMAFlagStatus(uint32_t ETH_DMA_FLAG);
1666+void ETH_DMAClearFlag(uint32_t ETH_DMA_FLAG);
1667+ITStatus ETH_GetDMAITStatus(uint32_t ETH_DMA_IT);
1668+void ETH_DMAClearITPendingBit(uint32_t ETH_DMA_IT);
1669+uint32_t ETH_GetTransmitProcessState(void);
1670+uint32_t ETH_GetReceiveProcessState(void);
1671+void ETH_FlushTransmitFIFO(void);
1672+FlagStatus ETH_GetFlushTransmitFIFOStatus(void);
1673+void ETH_DMATransmissionCmd(FunctionalState NewState);
1674+void ETH_DMAReceptionCmd(FunctionalState NewState);
1675+void ETH_DMAITConfig(uint32_t ETH_DMA_IT, FunctionalState NewState);
1676+FlagStatus ETH_GetDMAOverflowStatus(uint32_t ETH_DMA_Overflow);
1677+uint32_t ETH_GetRxOverflowMissedFrameCounter(void);
1678+uint32_t ETH_GetBufferUnavailableMissedFrameCounter(void);
1679+uint32_t ETH_GetCurrentTxDescStartAddress(void);
1680+uint32_t ETH_GetCurrentRxDescStartAddress(void);
1681+uint32_t ETH_GetCurrentTxBufferAddress(void);
1682+uint32_t ETH_GetCurrentRxBufferAddress(void);
1683+void ETH_ResumeDMATransmission(void);
1684+void ETH_ResumeDMAReception(void);
1685+
1686+/**
1687+ * @brief PMT
1688+ */
1689+void ETH_ResetWakeUpFrameFilterRegisterPointer(void);
1690+void ETH_SetWakeUpFrameFilterRegister(uint32_t *Buffer);
1691+void ETH_GlobalUnicastWakeUpCmd(FunctionalState NewState);
1692+FlagStatus ETH_GetPMTFlagStatus(uint32_t ETH_PMT_FLAG);
1693+void ETH_WakeUpFrameDetectionCmd(FunctionalState NewState);
1694+void ETH_MagicPacketDetectionCmd(FunctionalState NewState);
1695+void ETH_PowerDownCmd(FunctionalState NewState);
1696+
1697+/**
1698+ * @brief MMC
1699+ */
1700+void ETH_MMCCounterFreezeCmd(FunctionalState NewState);
1701+void ETH_MMCResetOnReadCmd(FunctionalState NewState);
1702+void ETH_MMCCounterRolloverCmd(FunctionalState NewState);
1703+void ETH_MMCCountersReset(void);
1704+void ETH_MMCITConfig(uint32_t ETH_MMC_IT, FunctionalState NewState);
1705+ITStatus ETH_GetMMCITStatus(uint32_t ETH_MMC_IT);
1706+uint32_t ETH_GetMMCRegister(uint32_t ETH_MMCReg);
1707+
1708+/**
1709+ * @brief PTP
1710+ */
1711+uint32_t ETH_HandlePTPTxPkt(u8 *ppkt, u16 FrameLength, uint32_t *PTPTxTab);
1712+uint32_t ETH_HandlePTPRxPkt(u8 *ppkt, uint32_t *PTPRxTab);
1713+void ETH_DMAPTPTxDescChainInit(ETH_DMADESCTypeDef *DMATxDescTab, ETH_DMADESCTypeDef *DMAPTPTxDescTab, u8* TxBuff, uint32_t TxBuffCount);
1714+void ETH_DMAPTPRxDescChainInit(ETH_DMADESCTypeDef *DMARxDescTab, ETH_DMADESCTypeDef *DMAPTPRxDescTab, u8 *RxBuff, uint32_t RxBuffCount);
1715+void ETH_EnablePTPTimeStampAddend(void);
1716+void ETH_EnablePTPTimeStampInterruptTrigger(void);
1717+void ETH_EnablePTPTimeStampUpdate(void);
1718+void ETH_InitializePTPTimeStamp(void);
1719+void ETH_PTPUpdateMethodConfig(uint32_t UpdateMethod);
1720+void ETH_PTPTimeStampCmd(FunctionalState NewState);
1721+FlagStatus ETH_GetPTPFlagStatus(uint32_t ETH_PTP_FLAG);
1722+void ETH_SetPTPSubSecondIncrement(uint32_t SubSecondValue);
1723+void ETH_SetPTPTimeStampUpdate(uint32_t Sign, uint32_t SecondValue, uint32_t SubSecondValue);
1724+void ETH_SetPTPTimeStampAddend(uint32_t Value);
1725+void ETH_SetPTPTargetTime(uint32_t HighValue, uint32_t LowValue);
1726+uint32_t ETH_GetPTPRegister(uint32_t ETH_PTPReg);
1727+
1728+#ifdef __cplusplus
1729+}
1730+#endif
1731+
1732+#endif /* __STM32_ETH_H */
1733+/**
1734+ * @}
1735+ */
1736+
1737+
1738+/**
1739+ * @}
1740+ */
1741+
1742+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
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