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hardware-intel-common-vaapi: Commit

hardware/intel/common/vaapi


Commit MetaInfo

Revisiona3b6dd4f802cd17ed54dd6c359ea115c1243a99e (tree)
Time2019-01-30 22:04:34
AuthorHaihao Xiang <haihao.xiang@inte...>
CommiterXiang, Haihao

Log Message

Revert "VPP: clear a surface using media pipeline on GEN8+"

Commit 5bdb675 causes performance drop

This reverts commit 5bdb675 and fixes compiler errors.

Change Summary

  • modified: src/gen75_picture_process.c (diff)
  • modified: src/gen8_post_processing.c (diff)
  • modified: src/gen9_post_processing.c (diff)
  • modified: src/i965_post_processing.c (diff)
  • modified: src/i965_post_processing.h (diff)
  • modified: src/intel_common_vpp_internal.c (diff)
  • modified: src/intel_common_vpp_internal.h (diff)
  • modified: src/intel_gen_vppapi.h (diff)
  • modified: src/shaders/post_processing/gen8/Makefile.am (diff)
  • delete: src/shaders/post_processing/gen8/clear_bgrx.g8b
  • delete: src/shaders/post_processing/gen8/clear_bgrx.gxa
  • delete: src/shaders/post_processing/gen8/clear_pl2_8bit.g8b
  • delete: src/shaders/post_processing/gen8/clear_pl2_8bit.gxa
  • delete: src/shaders/post_processing/gen8/clear_pl3_8bit.g8b
  • delete: src/shaders/post_processing/gen8/clear_pl3_8bit.gxa
  • delete: src/shaders/post_processing/gen8/clear_rgbx.g8b
  • delete: src/shaders/post_processing/gen8/clear_rgbx.gxa
  • delete: src/shaders/post_processing/gen8/clear_uyvy.g8b
  • delete: src/shaders/post_processing/gen8/clear_uyvy.gxa
  • delete: src/shaders/post_processing/gen8/clear_yuy2.g8b
  • delete: src/shaders/post_processing/gen8/clear_yuy2.gxa
  • modified: src/shaders/post_processing/gen9/Makefile.am (diff)
  • delete: src/shaders/post_processing/gen9/clear_bgrx.g9b
  • delete: src/shaders/post_processing/gen9/clear_bgrx.gxa
  • delete: src/shaders/post_processing/gen9/clear_pl2_8bit.g9b
  • delete: src/shaders/post_processing/gen9/clear_pl2_8bit.gxa
  • delete: src/shaders/post_processing/gen9/clear_pl3_8bit.g9b
  • delete: src/shaders/post_processing/gen9/clear_pl3_8bit.gxa
  • delete: src/shaders/post_processing/gen9/clear_rgbx.g9b
  • delete: src/shaders/post_processing/gen9/clear_rgbx.gxa
  • delete: src/shaders/post_processing/gen9/clear_uyvy.g9b
  • delete: src/shaders/post_processing/gen9/clear_uyvy.gxa
  • delete: src/shaders/post_processing/gen9/clear_yuy2.g9b
  • delete: src/shaders/post_processing/gen9/clear_yuy2.gxa

Incremental Difference

--- a/src/gen75_picture_process.c
+++ b/src/gen75_picture_process.c
@@ -113,23 +113,81 @@ gen8plus_vpp_clear_surface(VADriverContextP ctx,
113113 struct object_surface *obj_surface,
114114 unsigned int color)
115115 {
116+ struct intel_batchbuffer *batch = pp_context->batch;
117+ unsigned int blt_cmd, br13;
118+ unsigned int tiling = 0, swizzle = 0;
119+ int pitch;
116120 unsigned char y, u, v, a = 0;
121+ int region_width, region_height;
117122
118- if (!obj_surface ||
119- !obj_surface->bo ||
120- !(color & 0xFF000000))
123+ /* Currently only support NV12 surface */
124+ if (!obj_surface || obj_surface->fourcc != VA_FOURCC_NV12)
121125 return;
122126
123- if (obj_surface->fourcc == VA_FOURCC_RGBA ||
124- obj_surface->fourcc == VA_FOURCC_RGBX ||
125- obj_surface->fourcc == VA_FOURCC_BGRA ||
126- obj_surface->fourcc == VA_FOURCC_BGRX)
127- intel_common_clear_surface(ctx, pp_context, obj_surface, color);
128- else {
129- rgb_to_yuv(color, &y, &u, &v, &a);
130- intel_common_clear_surface(ctx, pp_context, obj_surface,
131- a << 24 | y << 16 | v << 8 | u);
127+ rgb_to_yuv(color, &y, &u, &v, &a);
128+
129+ if (a == 0)
130+ return;
131+
132+ dri_bo_get_tiling(obj_surface->bo, &tiling, &swizzle);
133+ blt_cmd = GEN8_XY_COLOR_BLT_CMD;
134+ pitch = obj_surface->width;
135+
136+ if (tiling != I915_TILING_NONE) {
137+ assert(tiling == I915_TILING_Y);
138+ // blt_cmd |= XY_COLOR_BLT_DST_TILED;
139+ // pitch >>= 2;
132140 }
141+
142+ br13 = 0xf0 << 16;
143+ br13 |= BR13_8;
144+ br13 |= pitch;
145+
146+ intel_batchbuffer_start_atomic_blt(batch, 56);
147+ BEGIN_BLT_BATCH(batch, 14);
148+
149+ region_width = obj_surface->width;
150+ region_height = obj_surface->height;
151+
152+ OUT_BATCH(batch, blt_cmd);
153+ OUT_BATCH(batch, br13);
154+ OUT_BATCH(batch,
155+ 0 << 16 |
156+ 0);
157+ OUT_BATCH(batch,
158+ region_height << 16 |
159+ region_width);
160+ OUT_RELOC64(batch, obj_surface->bo,
161+ I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
162+ 0);
163+ OUT_BATCH(batch, y);
164+
165+ br13 = 0xf0 << 16;
166+ br13 |= BR13_565;
167+ br13 |= pitch;
168+
169+ region_width = obj_surface->width / 2;
170+ region_height = obj_surface->height / 2;
171+
172+ if (tiling == I915_TILING_Y) {
173+ region_height = ALIGN(obj_surface->height / 2, 32);
174+ }
175+
176+ OUT_BATCH(batch, blt_cmd);
177+ OUT_BATCH(batch, br13);
178+ OUT_BATCH(batch,
179+ 0 << 16 |
180+ 0);
181+ OUT_BATCH(batch,
182+ region_height << 16 |
183+ region_width);
184+ OUT_RELOC64(batch, obj_surface->bo,
185+ I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
186+ obj_surface->width * obj_surface->y_cb_offset);
187+ OUT_BATCH(batch, v << 8 | u);
188+
189+ ADVANCE_BATCH(batch);
190+ intel_batchbuffer_end_atomic(batch);
133191 }
134192
135193 VAStatus
@@ -239,7 +297,8 @@ gen75_proc_picture(VADriverContextP ctx,
239297 assert(gpe_proc_ctx != NULL); // gpe_proc_ctx must be a non-NULL pointer
240298
241299 if ((gpe_proc_ctx->pp_context.scaling_gpe_context_initialized & VPPGPE_8BIT_8BIT) &&
242- (pipeline_param->output_background_color & 0xFF000000))
300+ (obj_dst_surf->fourcc == VA_FOURCC_NV12) &&
301+ pipeline_param->output_background_color)
243302 gen8plus_vpp_clear_surface(ctx,
244303 &gpe_proc_ctx->pp_context,
245304 obj_dst_surf,
--- a/src/gen8_post_processing.c
+++ b/src/gen8_post_processing.c
@@ -350,80 +350,6 @@ struct i965_kernel pp_common_scaling_gen8[] = {
350350 },
351351 };
352352
353-static const uint32_t pp_clear_yuy2_gen8[][4] = {
354-#include "shaders/post_processing/gen8/clear_yuy2.g8b"
355-};
356-
357-static const uint32_t pp_clear_uyvy_gen8[][4] = {
358-#include "shaders/post_processing/gen8/clear_uyvy.g8b"
359-};
360-
361-static const uint32_t pp_clear_pl2_8bit_gen8[][4] = {
362-#include "shaders/post_processing/gen8/clear_pl2_8bit.g8b"
363-};
364-
365-static const uint32_t pp_clear_pl3_8bit_gen8[][4] = {
366-#include "shaders/post_processing/gen8/clear_pl3_8bit.g8b"
367-};
368-
369-static const uint32_t pp_clear_rgbx_gen8[][4] = {
370-#include "shaders/post_processing/gen8/clear_rgbx.g8b"
371-};
372-
373-static const uint32_t pp_clear_bgrx_gen8[][4] = {
374-#include "shaders/post_processing/gen8/clear_bgrx.g8b"
375-};
376-
377-struct i965_kernel pp_clear_gen8[] = {
378- {
379- "pl2 8bit",
380- 0,
381- pp_clear_pl2_8bit_gen8,
382- sizeof(pp_clear_pl2_8bit_gen8),
383- NULL,
384- },
385-
386- {
387- "pl3 8bit",
388- 1,
389- pp_clear_pl3_8bit_gen8,
390- sizeof(pp_clear_pl3_8bit_gen8),
391- NULL,
392- },
393-
394- {
395- "yuy2",
396- 2,
397- pp_clear_yuy2_gen8,
398- sizeof(pp_clear_yuy2_gen8),
399- NULL,
400- },
401-
402- {
403- "uyvy",
404- 3,
405- pp_clear_uyvy_gen8,
406- sizeof(pp_clear_uyvy_gen8),
407- NULL,
408- },
409-
410- {
411- "rgbx",
412- 4,
413- pp_clear_rgbx_gen8,
414- sizeof(pp_clear_rgbx_gen8),
415- NULL,
416- },
417-
418- {
419- "bgrx",
420- 5,
421- pp_clear_bgrx_gen8,
422- sizeof(pp_clear_bgrx_gen8),
423- NULL,
424- },
425-};
426-
427353 static void
428354 gen8_pp_set_surface_tiling(struct gen8_surface_state *ss, unsigned int tiling)
429355 {
@@ -1621,11 +1547,6 @@ gen8_post_processing_context_finalize(VADriverContextP ctx,
16211547 pp_context->scaling_gpe_context_initialized = 0;
16221548 }
16231549
1624- if (pp_context->clear_gpe_context_initialized) {
1625- gen8_gpe_context_destroy(&pp_context->clear_gpe_context);
1626- pp_context->clear_gpe_context_initialized = 0;
1627- }
1628-
16291550 if (pp_context->vebox_proc_ctx) {
16301551 gen75_vebox_context_destroy(ctx, pp_context->vebox_proc_ctx);
16311552 pp_context->vebox_proc_ctx = NULL;
@@ -1799,36 +1720,6 @@ gen8_post_processing_context_init(VADriverContextP ctx,
17991720 gen8_gpe_context_init(ctx, gpe_context);
18001721 pp_context->scaling_gpe_context_initialized |= (VPPGPE_8BIT_8BIT | VPPGPE_8BIT_420_RGB32);
18011722
1802- gpe_context = &pp_context->clear_gpe_context;
1803- gen8_gpe_load_kernels(ctx, gpe_context, pp_clear_gen8, ARRAY_ELEMS(pp_clear_gen8));
1804- gpe_context->idrt.entry_size = ALIGN(sizeof(struct gen8_interface_descriptor_data), 64);
1805- gpe_context->idrt.max_entries = ALIGN(ARRAY_ELEMS(pp_clear_gen8), 2);
1806- gpe_context->sampler.entry_size = ALIGN(sizeof(struct gen8_sampler_state), 64);
1807- gpe_context->sampler.max_entries = 1;
1808- gpe_context->curbe.length = ALIGN(sizeof(struct clear_input_parameter), 64);
1809-
1810- gpe_context->surface_state_binding_table.max_entries = MAX_SCALING_SURFACES;
1811- gpe_context->surface_state_binding_table.binding_table_offset = 0;
1812- gpe_context->surface_state_binding_table.surface_state_offset = ALIGN(MAX_SCALING_SURFACES * 4, 64);
1813- gpe_context->surface_state_binding_table.length = ALIGN(MAX_SCALING_SURFACES * 4, 64) + ALIGN(MAX_SCALING_SURFACES * SURFACE_STATE_PADDED_SIZE_GEN9, 64);
1814-
1815- if (i965->intel.eu_total > 0) {
1816- gpe_context->vfe_state.max_num_threads = i965->intel.eu_total * 6;
1817- } else {
1818- if (i965->intel.has_bsd2)
1819- gpe_context->vfe_state.max_num_threads = 300;
1820- else
1821- gpe_context->vfe_state.max_num_threads = 60;
1822- }
1823-
1824- gpe_context->vfe_state.curbe_allocation_size = 37;
1825- gpe_context->vfe_state.urb_entry_size = 16;
1826- gpe_context->vfe_state.num_urb_entries = 127;
1827- gpe_context->vfe_state.gpgpu_mode = 0;
1828-
1829- gen8_gpe_context_init(ctx, gpe_context);
1830- pp_context->clear_gpe_context_initialized = 1;
1831-
18321723 return;
18331724 }
18341725
@@ -2485,203 +2376,3 @@ gen8_8bit_420_rgb32_scaling_post_processing(VADriverContextP ctx,
24852376
24862377 return VA_STATUS_SUCCESS;
24872378 }
2488-
2489-static void
2490-gen8_clear_surface_sample_state(VADriverContextP ctx,
2491- struct i965_gpe_context *gpe_context,
2492- const struct object_surface *obj_surface)
2493-{
2494- struct gen8_sampler_state *sampler_state;
2495-
2496- if (gpe_context == NULL)
2497- return;
2498-
2499- dri_bo_map(gpe_context->sampler.bo, 1);
2500-
2501- if (gpe_context->sampler.bo->virtual == NULL)
2502- return;
2503-
2504- sampler_state = (struct gen8_sampler_state *)(gpe_context->sampler.bo->virtual + gpe_context->sampler.offset);
2505-
2506- memset(sampler_state, 0, sizeof(*sampler_state));
2507-
2508- dri_bo_unmap(gpe_context->sampler.bo);
2509-}
2510-
2511-static void
2512-gen8_clear_surface_curbe(VADriverContextP ctx,
2513- struct i965_gpe_context *gpe_context,
2514- const struct object_surface *obj_surface,
2515- unsigned int color)
2516-{
2517- struct clear_input_parameter *clear_curbe;
2518-
2519- if (gpe_context == NULL || !obj_surface)
2520- return;
2521-
2522- clear_curbe = i965_gpe_context_map_curbe(gpe_context);
2523-
2524- if (!clear_curbe)
2525- return;
2526-
2527- memset(clear_curbe, 0, sizeof(struct clear_input_parameter));
2528- clear_curbe->color = color;
2529-
2530- i965_gpe_context_unmap_curbe(gpe_context);
2531-}
2532-
2533-static void
2534-gen8_clear_surface_state(VADriverContextP ctx,
2535- struct i965_gpe_context *gpe_context,
2536- const struct object_surface *obj_surface)
2537-{
2538- struct i965_surface src_surface;
2539- VARectangle rect;
2540- dri_bo *bo;
2541- unsigned int fourcc;
2542- int width[3], height[3], pitch[3], bo_offset[3];
2543- int bti;
2544-
2545- src_surface.base = (struct object_base *)obj_surface;
2546- src_surface.type = I965_SURFACE_TYPE_SURFACE;
2547- src_surface.flags = I965_SURFACE_FLAG_FRAME;
2548-
2549- fourcc = obj_surface->fourcc;
2550- rect.x = 0;
2551- rect.y = 0;
2552- rect.width = obj_surface->orig_width;
2553- rect.height = obj_surface->orig_height;
2554-
2555- gen8_pp_context_get_surface_conf(ctx, &src_surface,
2556- &rect,
2557- width,
2558- height,
2559- pitch,
2560- bo_offset);
2561-
2562- bti = 1;
2563- bo = obj_surface->bo;
2564-
2565- if (fourcc == VA_FOURCC_RGBA ||
2566- fourcc == VA_FOURCC_RGBX ||
2567- fourcc == VA_FOURCC_BGRA ||
2568- fourcc == VA_FOURCC_BGRX) {
2569- gen8_add_dri_buffer_2d_gpe_surface(ctx, gpe_context, bo,
2570- bo_offset[0],
2571- width[0] * 4, height[0],
2572- pitch[0], 1,
2573- I965_SURFACEFORMAT_R8_UINT,
2574- bti, 0);
2575- } else if (fourcc == VA_FOURCC_YUY2 || fourcc == VA_FOURCC_UYVY) {
2576- gen8_add_dri_buffer_2d_gpe_surface(ctx, gpe_context, bo,
2577- bo_offset[0],
2578- width[0] * 2, height[0],
2579- pitch[0], 1,
2580- I965_SURFACEFORMAT_R8_UINT,
2581- bti, 0);
2582- } else {
2583- gen8_add_dri_buffer_2d_gpe_surface(ctx, gpe_context, bo,
2584- bo_offset[0],
2585- width[0], height[0],
2586- pitch[0], 1,
2587- I965_SURFACEFORMAT_R8_UINT,
2588- bti, 0);
2589-
2590- if (fourcc == VA_FOURCC_NV12) {
2591- gen8_add_dri_buffer_2d_gpe_surface(ctx, gpe_context, bo,
2592- bo_offset[1],
2593- width[1] * 2, height[1],
2594- pitch[1], 1,
2595- I965_SURFACEFORMAT_R8_UINT,
2596- bti + 1, 0);
2597- } else {
2598- gen8_add_dri_buffer_2d_gpe_surface(ctx, gpe_context, bo,
2599- bo_offset[1],
2600- width[1], height[1],
2601- pitch[1], 1,
2602- I965_SURFACEFORMAT_R8_UINT,
2603- bti + 1, 0);
2604-
2605- gen8_add_dri_buffer_2d_gpe_surface(ctx, gpe_context, bo,
2606- bo_offset[2],
2607- width[2], height[2],
2608- pitch[2], 1,
2609- I965_SURFACEFORMAT_R8_UINT,
2610- bti + 2, 0);
2611- }
2612- }
2613-}
2614-
2615-void
2616-gen8_clear_surface(VADriverContextP ctx,
2617- struct i965_post_processing_context *pp_context,
2618- const struct object_surface *obj_surface,
2619- unsigned int color)
2620-{
2621- struct i965_gpe_context *gpe_context;
2622- struct gpe_media_object_walker_parameter media_object_walker_param;
2623- struct intel_vpp_kernel_walker_parameter kernel_walker_param;
2624- int index = 0;
2625-
2626- if (!pp_context || !obj_surface)
2627- return;
2628-
2629- if (!pp_context->clear_gpe_context_initialized)
2630- return;
2631-
2632- switch (obj_surface->fourcc) {
2633- case VA_FOURCC_NV12:
2634- index = 0;
2635- break;
2636-
2637- case VA_FOURCC_I420:
2638- case VA_FOURCC_YV12:
2639- case VA_FOURCC_IMC1:
2640- case VA_FOURCC_IMC3:
2641- index = 1;
2642- break;
2643-
2644- case VA_FOURCC_YUY2:
2645- index = 2;
2646- break;
2647-
2648- case VA_FOURCC_UYVY:
2649- index = 3;
2650- break;
2651-
2652- case VA_FOURCC_RGBA:
2653- case VA_FOURCC_RGBX:
2654- index = 4;
2655- break;
2656-
2657- case VA_FOURCC_BGRA:
2658- case VA_FOURCC_BGRX:
2659- index = 5;
2660- break;
2661-
2662- default:
2663- /* TODO: add support for other fourccs */
2664- return;
2665- }
2666-
2667- gpe_context = &pp_context->clear_gpe_context;
2668-
2669- gen8_gpe_context_init(ctx, gpe_context);
2670- gen8_clear_surface_sample_state(ctx, gpe_context, obj_surface);
2671- gen8_gpe_reset_binding_table(ctx, gpe_context);
2672- gen8_clear_surface_curbe(ctx, gpe_context, obj_surface, color);
2673- gen8_clear_surface_state(ctx, gpe_context, obj_surface);
2674- gen8_gpe_setup_interface_data(ctx, gpe_context);
2675-
2676- memset(&kernel_walker_param, 0, sizeof(kernel_walker_param));
2677- kernel_walker_param.resolution_x = ALIGN(obj_surface->orig_width, 16) >> 4;
2678- kernel_walker_param.resolution_y = ALIGN(obj_surface->orig_height, 16) >> 4;
2679- kernel_walker_param.no_dependency = 1;
2680-
2681- intel_vpp_init_media_object_walker_parameter(&kernel_walker_param, &media_object_walker_param);
2682- media_object_walker_param.interface_offset = index;
2683- gen8_run_kernel_media_object_walker(ctx,
2684- pp_context->batch,
2685- gpe_context,
2686- &media_object_walker_param);
2687-}
--- a/src/gen9_post_processing.c
+++ b/src/gen9_post_processing.c
@@ -124,30 +124,6 @@ static const uint32_t pp_8bit_420_rgb32_scaling_gen9[][4] = {
124124 #include "shaders/post_processing/gen9/conv_8bit_420_rgb32.g9b"
125125 };
126126
127-static const uint32_t pp_clear_yuy2_gen9[][4] = {
128-#include "shaders/post_processing/gen9/clear_yuy2.g9b"
129-};
130-
131-static const uint32_t pp_clear_uyvy_gen9[][4] = {
132-#include "shaders/post_processing/gen9/clear_uyvy.g9b"
133-};
134-
135-static const uint32_t pp_clear_pl2_8bit_gen9[][4] = {
136-#include "shaders/post_processing/gen9/clear_pl2_8bit.g9b"
137-};
138-
139-static const uint32_t pp_clear_pl3_8bit_gen9[][4] = {
140-#include "shaders/post_processing/gen9/clear_pl3_8bit.g9b"
141-};
142-
143-static const uint32_t pp_clear_rgbx_gen9[][4] = {
144-#include "shaders/post_processing/gen9/clear_rgbx.g9b"
145-};
146-
147-static const uint32_t pp_clear_bgrx_gen9[][4] = {
148-#include "shaders/post_processing/gen9/clear_bgrx.g9b"
149-};
150-
151127 struct i965_kernel pp_common_scaling_gen9[] = {
152128 {
153129 "10bit to 10bit",
@@ -182,56 +158,6 @@ struct i965_kernel pp_common_scaling_gen9[] = {
182158 },
183159 };
184160
185-struct i965_kernel pp_clear_gen9[] = {
186- {
187- "pl2 8bit",
188- 0,
189- pp_clear_pl2_8bit_gen9,
190- sizeof(pp_clear_pl2_8bit_gen9),
191- NULL,
192- },
193-
194- {
195- "pl3 8bit",
196- 1,
197- pp_clear_pl3_8bit_gen9,
198- sizeof(pp_clear_pl3_8bit_gen9),
199- NULL,
200- },
201-
202- {
203- "yuy2",
204- 2,
205- pp_clear_yuy2_gen9,
206- sizeof(pp_clear_yuy2_gen9),
207- NULL,
208- },
209-
210- {
211- "uyvy",
212- 3,
213- pp_clear_uyvy_gen9,
214- sizeof(pp_clear_uyvy_gen9),
215- NULL,
216- },
217-
218- {
219- "rgbx",
220- 4,
221- pp_clear_rgbx_gen9,
222- sizeof(pp_clear_rgbx_gen9),
223- NULL,
224- },
225-
226- {
227- "bgrx",
228- 5,
229- pp_clear_bgrx_gen9,
230- sizeof(pp_clear_bgrx_gen9),
231- NULL,
232- },
233-};
234-
235161 static struct pp_module pp_modules_gen9[] = {
236162 {
237163 {
@@ -649,36 +575,6 @@ gen9_post_processing_context_init(VADriverContextP ctx,
649575 gen8_gpe_context_init(ctx, gpe_context);
650576 pp_context->scaling_gpe_context_initialized |= (VPPGPE_8BIT_8BIT | VPPGPE_10BIT_10BIT | VPPGPE_10BIT_8BIT | VPPGPE_8BIT_420_RGB32);
651577
652- gpe_context = &pp_context->clear_gpe_context;
653- gen8_gpe_load_kernels(ctx, gpe_context, pp_clear_gen9, ARRAY_ELEMS(pp_clear_gen9));
654- gpe_context->idrt.entry_size = ALIGN(sizeof(struct gen8_interface_descriptor_data), 64);
655- gpe_context->idrt.max_entries = ALIGN(ARRAY_ELEMS(pp_clear_gen9), 2);
656- gpe_context->sampler.entry_size = ALIGN(sizeof(struct gen8_sampler_state), 64);
657- gpe_context->sampler.max_entries = 1;
658- gpe_context->curbe.length = ALIGN(sizeof(struct clear_input_parameter), 64);
659-
660- gpe_context->surface_state_binding_table.max_entries = MAX_SCALING_SURFACES;
661- gpe_context->surface_state_binding_table.binding_table_offset = 0;
662- gpe_context->surface_state_binding_table.surface_state_offset = ALIGN(MAX_SCALING_SURFACES * 4, 64);
663- gpe_context->surface_state_binding_table.length = ALIGN(MAX_SCALING_SURFACES * 4, 64) + ALIGN(MAX_SCALING_SURFACES * SURFACE_STATE_PADDED_SIZE_GEN9, 64);
664-
665- if (i965->intel.eu_total > 0) {
666- gpe_context->vfe_state.max_num_threads = i965->intel.eu_total * 6;
667- } else {
668- if (i965->intel.has_bsd2)
669- gpe_context->vfe_state.max_num_threads = 300;
670- else
671- gpe_context->vfe_state.max_num_threads = 60;
672- }
673-
674- gpe_context->vfe_state.curbe_allocation_size = 37;
675- gpe_context->vfe_state.urb_entry_size = 16;
676- gpe_context->vfe_state.num_urb_entries = 127;
677- gpe_context->vfe_state.gpgpu_mode = 0;
678-
679- gen8_gpe_context_init(ctx, gpe_context);
680- pp_context->clear_gpe_context_initialized = 1;
681-
682578 return;
683579 }
684580
@@ -1803,203 +1699,3 @@ gen9_8bit_420_rgb32_scaling_post_processing(VADriverContextP ctx,
18031699
18041700 return VA_STATUS_SUCCESS;
18051701 }
1806-
1807-static void
1808-gen9_clear_surface_sample_state(VADriverContextP ctx,
1809- struct i965_gpe_context *gpe_context,
1810- const struct object_surface *obj_surface)
1811-{
1812- struct gen8_sampler_state *sampler_state;
1813-
1814- if (gpe_context == NULL)
1815- return;
1816-
1817- dri_bo_map(gpe_context->sampler.bo, 1);
1818-
1819- if (gpe_context->sampler.bo->virtual == NULL)
1820- return;
1821-
1822- sampler_state = (struct gen8_sampler_state *)(gpe_context->sampler.bo->virtual + gpe_context->sampler.offset);
1823-
1824- memset(sampler_state, 0, sizeof(*sampler_state));
1825-
1826- dri_bo_unmap(gpe_context->sampler.bo);
1827-}
1828-
1829-static void
1830-gen9_clear_surface_curbe(VADriverContextP ctx,
1831- struct i965_gpe_context *gpe_context,
1832- const struct object_surface *obj_surface,
1833- unsigned int color)
1834-{
1835- struct clear_input_parameter *clear_curbe;
1836-
1837- if (gpe_context == NULL || !obj_surface)
1838- return;
1839-
1840- clear_curbe = i965_gpe_context_map_curbe(gpe_context);
1841-
1842- if (!clear_curbe)
1843- return;
1844-
1845- memset(clear_curbe, 0, sizeof(struct clear_input_parameter));
1846- clear_curbe->color = color;
1847-
1848- i965_gpe_context_unmap_curbe(gpe_context);
1849-}
1850-
1851-static void
1852-gen9_clear_surface_state(VADriverContextP ctx,
1853- struct i965_gpe_context *gpe_context,
1854- const struct object_surface *obj_surface)
1855-{
1856- struct i965_surface src_surface;
1857- VARectangle rect;
1858- dri_bo *bo;
1859- unsigned int fourcc;
1860- int width[3], height[3], pitch[3], bo_offset[3];
1861- int bti;
1862-
1863- src_surface.base = (struct object_base *)obj_surface;
1864- src_surface.type = I965_SURFACE_TYPE_SURFACE;
1865- src_surface.flags = I965_SURFACE_FLAG_FRAME;
1866-
1867- fourcc = obj_surface->fourcc;
1868- rect.x = 0;
1869- rect.y = 0;
1870- rect.width = obj_surface->orig_width;
1871- rect.height = obj_surface->orig_height;
1872-
1873- gen9_pp_context_get_surface_conf(ctx, &src_surface,
1874- &rect,
1875- width,
1876- height,
1877- pitch,
1878- bo_offset);
1879-
1880- bti = 1;
1881- bo = obj_surface->bo;
1882-
1883- if (fourcc == VA_FOURCC_RGBA ||
1884- fourcc == VA_FOURCC_RGBX ||
1885- fourcc == VA_FOURCC_BGRA ||
1886- fourcc == VA_FOURCC_BGRX) {
1887- gen9_add_dri_buffer_2d_gpe_surface(ctx, gpe_context, bo,
1888- bo_offset[0],
1889- width[0] * 4, height[0],
1890- pitch[0], 1,
1891- I965_SURFACEFORMAT_R8_UINT,
1892- bti, 0);
1893- } else if (fourcc == VA_FOURCC_YUY2 || fourcc == VA_FOURCC_UYVY) {
1894- gen9_add_dri_buffer_2d_gpe_surface(ctx, gpe_context, bo,
1895- bo_offset[0],
1896- width[0] * 2, height[0],
1897- pitch[0], 1,
1898- I965_SURFACEFORMAT_R8_UINT,
1899- bti, 0);
1900- } else {
1901- gen9_add_dri_buffer_2d_gpe_surface(ctx, gpe_context, bo,
1902- bo_offset[0],
1903- width[0], height[0],
1904- pitch[0], 1,
1905- I965_SURFACEFORMAT_R8_UINT,
1906- bti, 0);
1907-
1908- if (fourcc == VA_FOURCC_NV12) {
1909- gen9_add_dri_buffer_2d_gpe_surface(ctx, gpe_context, bo,
1910- bo_offset[1],
1911- width[1] * 2, height[1],
1912- pitch[1], 1,
1913- I965_SURFACEFORMAT_R8_UINT,
1914- bti + 1, 0);
1915- } else {
1916- gen9_add_dri_buffer_2d_gpe_surface(ctx, gpe_context, bo,
1917- bo_offset[1],
1918- width[1], height[1],
1919- pitch[1], 1,
1920- I965_SURFACEFORMAT_R8_UINT,
1921- bti + 1, 0);
1922-
1923- gen9_add_dri_buffer_2d_gpe_surface(ctx, gpe_context, bo,
1924- bo_offset[2],
1925- width[2], height[2],
1926- pitch[2], 1,
1927- I965_SURFACEFORMAT_R8_UINT,
1928- bti + 2, 0);
1929- }
1930- }
1931-}
1932-
1933-void
1934-gen9_clear_surface(VADriverContextP ctx,
1935- struct i965_post_processing_context *pp_context,
1936- const struct object_surface *obj_surface,
1937- unsigned int color)
1938-{
1939- struct i965_gpe_context *gpe_context;
1940- struct gpe_media_object_walker_parameter media_object_walker_param;
1941- struct intel_vpp_kernel_walker_parameter kernel_walker_param;
1942- int index = 0;
1943-
1944- if (!pp_context || !obj_surface)
1945- return;
1946-
1947- if (!pp_context->clear_gpe_context_initialized)
1948- return;
1949-
1950- switch (obj_surface->fourcc) {
1951- case VA_FOURCC_NV12:
1952- index = 0;
1953- break;
1954-
1955- case VA_FOURCC_I420:
1956- case VA_FOURCC_YV12:
1957- case VA_FOURCC_IMC1:
1958- case VA_FOURCC_IMC3:
1959- index = 1;
1960- break;
1961-
1962- case VA_FOURCC_YUY2:
1963- index = 2;
1964- break;
1965-
1966- case VA_FOURCC_UYVY:
1967- index = 3;
1968- break;
1969-
1970- case VA_FOURCC_RGBA:
1971- case VA_FOURCC_RGBX:
1972- index = 4;
1973- break;
1974-
1975- case VA_FOURCC_BGRA:
1976- case VA_FOURCC_BGRX:
1977- index = 5;
1978- break;
1979-
1980- default:
1981- /* TODO: add support for other fourccs */
1982- return;
1983- }
1984-
1985- gpe_context = &pp_context->clear_gpe_context;
1986-
1987- gen8_gpe_context_init(ctx, gpe_context);
1988- gen9_clear_surface_sample_state(ctx, gpe_context, obj_surface);
1989- gen9_gpe_reset_binding_table(ctx, gpe_context);
1990- gen9_clear_surface_curbe(ctx, gpe_context, obj_surface, color);
1991- gen9_clear_surface_state(ctx, gpe_context, obj_surface);
1992- gen8_gpe_setup_interface_data(ctx, gpe_context);
1993-
1994- memset(&kernel_walker_param, 0, sizeof(kernel_walker_param));
1995- kernel_walker_param.resolution_x = ALIGN(obj_surface->orig_width, 16) >> 4;
1996- kernel_walker_param.resolution_y = ALIGN(obj_surface->orig_height, 16) >> 4;
1997- kernel_walker_param.no_dependency = 1;
1998-
1999- intel_vpp_init_media_object_walker_parameter(&kernel_walker_param, &media_object_walker_param);
2000- media_object_walker_param.interface_offset = index;
2001- gen9_run_kernel_media_object_walker(ctx,
2002- pp_context->batch,
2003- gpe_context,
2004- &media_object_walker_param);
2005-}
--- a/src/i965_post_processing.c
+++ b/src/i965_post_processing.c
@@ -4791,15 +4791,6 @@ i965_vpp_clear_surface(VADriverContextP ctx,
47914791 if (a == 0)
47924792 return;
47934793
4794- if (IS_GEN8(i965->intel.device_info) ||
4795- IS_GEN9(i965->intel.device_info) ||
4796- IS_GEN10(i965->intel.device_info)) {
4797- intel_common_clear_surface(ctx, pp_context, obj_surface,
4798- a << 24 | y << 16 | u << 8 | v);
4799-
4800- return;
4801- }
4802-
48034794 dri_bo_get_tiling(obj_surface->bo, &tiling, &swizzle);
48044795 blt_cmd = XY_COLOR_BLT_CMD;
48054796 pitch = obj_surface->width;
--- a/src/i965_post_processing.h
+++ b/src/i965_post_processing.h
@@ -587,7 +587,6 @@ struct i965_post_processing_context {
587587
588588
589589 struct i965_gpe_context scaling_gpe_context;
590- struct i965_gpe_context clear_gpe_context;
591590
592591 #define VPPGPE_8BIT_8BIT (1 << 0)
593592 #define VPPGPE_8BIT_10BIT (1 << 1)
@@ -596,7 +595,6 @@ struct i965_post_processing_context {
596595 #define VPPGPE_8BIT_420_RGB32 (1 << 4)
597596
598597 unsigned int scaling_gpe_context_initialized;
599- unsigned int clear_gpe_context_initialized;
600598 };
601599
602600 struct i965_proc_context {
--- a/src/intel_common_vpp_internal.c
+++ b/src/intel_common_vpp_internal.c
@@ -277,17 +277,3 @@ intel_common_scaling_post_processing(VADriverContextP ctx,
277277
278278 return status;
279279 }
280-
281-void
282-intel_common_clear_surface(VADriverContextP ctx,
283- struct i965_post_processing_context *pp_context,
284- const struct object_surface *obj_surface,
285- unsigned int color)
286-{
287- struct i965_driver_data *i965 = i965_driver_data(ctx);
288-
289- if (IS_GEN8(i965->intel.device_info))
290- gen8_clear_surface(ctx, pp_context, obj_surface, color);
291- else
292- gen9_clear_surface(ctx, pp_context, obj_surface, color);
293-}
--- a/src/intel_common_vpp_internal.h
+++ b/src/intel_common_vpp_internal.h
@@ -29,8 +29,6 @@
2929 #ifndef _INTEL_COMMON_VPP_INTERNAL_H_
3030 #define _INTEL_COMMON_VPP_INTERNAL_H_
3131
32-struct object_surface;
33-
3432 /* the below is defined for YUV420 format scaling */
3533 #define SRC_MSB 0x0001
3634 #define DST_MSB 0x0002
@@ -106,12 +104,6 @@ struct scaling_input_parameter {
106104 unsigned int reserved[8];
107105 };
108106
109-/* 4 Registers or 32 DWs */
110-struct clear_input_parameter {
111- unsigned int color; /* ayvu */
112- unsigned int reserved[31];
113-};
114-
115107 VAStatus
116108 gen9_yuv420p8_scaling_post_processing(
117109 VADriverContextP ctx,
@@ -162,16 +154,4 @@ gen9_p010_scaling_post_processing(VADriverContextP ctx,
162154 struct i965_surface *dst_surface,
163155 VARectangle *dst_rect);
164156
165-void
166-gen8_clear_surface(VADriverContextP ctx,
167- struct i965_post_processing_context *pp_context,
168- const struct object_surface *obj_surface,
169- unsigned int color);
170-
171-void
172-gen9_clear_surface(VADriverContextP ctx,
173- struct i965_post_processing_context *pp_context,
174- const struct object_surface *obj_surface,
175- unsigned int color);
176-
177157 #endif // _INTEL_COMMON_VPP_INTERNAL_H_
--- a/src/intel_gen_vppapi.h
+++ b/src/intel_gen_vppapi.h
@@ -45,10 +45,4 @@ intel_common_scaling_post_processing(VADriverContextP ctx,
4545 struct i965_surface *dst_surface,
4646 const VARectangle *dst_rect);
4747
48-void
49-intel_common_clear_surface(VADriverContextP ctx,
50- struct i965_post_processing_context *pp_context,
51- const struct object_surface *obj_surface,
52- unsigned int color);
53-
5448 #endif // _INTE_GEN_VPPAPI_H_
--- a/src/shaders/post_processing/gen8/Makefile.am
+++ b/src/shaders/post_processing/gen8/Makefile.am
@@ -19,15 +19,6 @@ INTEL_PP_PRE_G8B = \
1919 conv_nv12.g8b \
2020 conv_8bit_420_rgb32.g8b
2121
22-INTEL_PP2_G8B = \
23- clear_bgrx.g8b \
24- clear_pl2_8bit.g8b \
25- clear_pl3_8bit.g8b \
26- clear_rgbx.g8b \
27- clear_yuy2.g8b \
28- clear_uyvy.g8b \
29- $(NULL)
30-
3122 INTEL_PP_G8A = \
3223 EOT.g8a \
3324 PL2_AVS_Buf_0.g8a \
@@ -61,12 +52,9 @@ INTEL_PP_G8A = \
6152 INTEL_PP_ASM = $(INTEL_PP_G8B:%.g8b=%.asm)
6253 INTEL_PP_GEN8_ASM = $(INTEL_PP_G8B:%.g8b=%.g8s)
6354
64-INTEL_PP2_GXA = $(INTEL_PP2_G8B:%.g8b=%.gxa)
65-INTEL_PP2_GXS = $(INTEL_PP2_G8B:%.gxa=%.gxs)
66-
6755 TARGETS =
6856 if HAVE_GEN4ASM
69-TARGETS += $(INTEL_PP_G8B) $(INTEL_PP2_G8B)
57+TARGETS += $(INTEL_PP_G8B)
7058 endif
7159
7260 all-local: $(TARGETS)
@@ -81,16 +69,9 @@ $(INTEL_PP_GEN8_ASM): $(INTEL_PP_ASM) $(INTEL_PP_G8A)
8169 rm _pp0.$@
8270 .g8s.g8b:
8371 $(AM_V_GEN)$(GEN4ASM) -a -o $@ -g 8 $<
84-
85-.gxa.gxs:
86- $(AM_V_GEN)cpp -P $< > _tmp.$@ && \
87- m4 _tmp.$@ > $@ && \
88- rm _tmp.$@
89-.gxs.g8b:
90- $(AM_V_GEN)$(GEN4ASM) -o $@ -g 8 $<
9172 endif
9273
93-CLEANFILES = $(INTEL_PP_GEN7_ASM) $(INTEL_PP_GEN8_ASM) $(INTEL_PP2_GXS)
74+CLEANFILES = $(INTEL_PP_GEN7_ASM) $(INTEL_PP_GEN8_ASM)
9475
9576 DISTCLEANFILES = $(TARGETS)
9677
@@ -98,9 +79,7 @@ EXTRA_DIST = \
9879 $(INTEL_PP_ASM) \
9980 $(INTEL_PP_G8A) \
10081 $(INTEL_PP_G8B) \
101- $(INTEL_PP_PRE_G8B) \
102- $(INTEL_PP2_G8B) \
103- $(NULL)
82+ $(INTEL_PP_PRE_G8B)
10483
10584 # Extra clean files so that maintainer-clean removes *everything*
10685 MAINTAINERCLEANFILES = Makefile.in
--- a/src/shaders/post_processing/gen8/clear_bgrx.g8b
+++ /dev/null
@@ -1,21 +0,0 @@
1- { 0x00600001, 0x22000208, 0x008d0000, 0x00000000 },
2- { 0x00000009, 0x22001208, 0x1e000004, 0x00060006 },
3- { 0x00000009, 0x22041208, 0x1e000006, 0x00040004 },
4- { 0x00000001, 0x22080608, 0x00000000, 0x000f000f },
5- { 0x00000001, 0x22232288, 0x00000023, 0x00000000 },
6- { 0x00000001, 0x22222288, 0x00000020, 0x00000000 },
7- { 0x00000001, 0x22212288, 0x00000021, 0x00000000 },
8- { 0x00000001, 0x22202288, 0x00000022, 0x00000000 },
9- { 0x00800001, 0x22200208, 0x00000220, 0x00000000 },
10- { 0x00800001, 0x22600208, 0x00000220, 0x00000000 },
11- { 0x00800001, 0x22a00208, 0x00000220, 0x00000000 },
12- { 0x00800001, 0x22e00208, 0x00000220, 0x00000000 },
13- { 0x0c800031, 0x24000a40, 0x0e000200, 0x120a8001 },
14- { 0x00000040, 0x22000208, 0x1e000200, 0x00100010 },
15- { 0x0c800031, 0x24000a40, 0x0e000200, 0x120a8001 },
16- { 0x00000040, 0x22000208, 0x1e000200, 0x00100010 },
17- { 0x0c800031, 0x24000a40, 0x0e000200, 0x120a8001 },
18- { 0x00000040, 0x22000208, 0x1e000200, 0x00100010 },
19- { 0x0c800031, 0x24000a40, 0x0e000200, 0x120a8001 },
20- { 0x00600001, 0x2e000208, 0x008d0000, 0x00000000 },
21- { 0x07800031, 0x20000a40, 0x0e000e00, 0x82000010 },
--- a/src/shaders/post_processing/gen8/clear_bgrx.gxa
+++ /dev/null
@@ -1,87 +0,0 @@
1-/*
2- * Copyright © 2018 Intel Corporation
3- *
4- * Permission is hereby granted, free of charge, to any person obtaining a
5- * copy of this software and associated documentation files (the
6- * "Software"), to deal in the Software without restriction, including
7- * without limitation the rights to use, copy, modify, merge, publish,
8- * distribute, sub license, and/or sell copies of the Software, and to
9- * permit persons to whom the Software is furnished to do so, subject to
10- * the following conditions:
11- *
12- * The above copyright notice and this permission notice (including the
13- * next paragraph) shall be included in all copies or substantial portions
14- * of the Software.
15- *
16- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19- * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
20- * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23- *
24- * Authors:
25- * Xiang Haihao <haihao.xiang@intel.com>
26- *
27- */
28-
29-/*
30- * Registers
31- * g0 header
32- * g1-g3 static parameters (constant)
33- * g16-g24 payload for write message
34- */
35-define(`ORIG', `g0.4<2,2,1>UW')
36-define(`ORIGX', `g0.4<0,1,0>UW')
37-define(`ORIGY', `g0.6<0,1,0>UW')
38-
39-define(`ALPHA', `g1.3<0,1,0>UB')
40-/* Red */
41-define(`R', `g1.2<0,1,0>UB')
42-/* Green */
43-define(`G', `g1.1<0,1,0>UB')
44-/* Blue */
45-define(`B', `g1.0<0,1,0>UB')
46-
47-define(`BGRX_BTI', `1')
48-
49-/* Thread header */
50-mov(8) g16.0<1>UD g0.0<8,8,1>UD {align1};
51-
52-/* RGBA/RGBX */
53-shl(1) g16.0<1>UD ORIGX 6:w {align1};
54-shl(1) g16.4<1>UD ORIGY 4:w {align1};
55-
56-/* 16x16 block */
57-mov(1) g16.8<1>UD 0x000f000fUD {align1};
58-
59-mov(1) g17.3<1>UB ALPHA {align1};
60-mov(1) g17.2<1>UB B {align1};
61-mov(1) g17.1<1>UB G {align1};
62-mov(1) g17.0<1>UB R {align1};
63-mov(16) g17.0<1>UD g17.0<0,1,0>UD {align1 compr};
64-mov(16) g19.0<1>UD g17.0<0,1,0>UD {align1 compr};
65-mov(16) g21.0<1>UD g17.0<0,1,0>UD {align1 compr};
66-mov(16) g23.0<1>UD g17.0<0,1,0>UD {align1 compr};
67-/*
68- * write(p0, p1, p2, p3)
69- * p0: binding table index
70- * p1: message control, default is 0,
71- * p2: message type, 10 is media_block_write
72- * p3: cache type, 12 is data cache data port 1
73- */
74-send(16) 16 acc0<1>UW null write(BGRX_BTI, 0, 10, 12) mlen 9 rlen 0 {align1};
75-
76-add(1) g16.0<1>UD g16.0<0,1,0>UD 16:w {align1};
77-send(16) 16 acc0<1>UW null write(BGRX_BTI, 0, 10, 12) mlen 9 rlen 0 {align1};
78-
79-add(1) g16.0<1>UD g16.0<0,1,0>UD 16:w {align1};
80-send(16) 16 acc0<1>UW null write(BGRX_BTI, 0, 10, 12) mlen 9 rlen 0 {align1};
81-
82-add(1) g16.0<1>UD g16.0<0,1,0>UD 16:w {align1};
83-send(16) 16 acc0<1>UW null write(BGRX_BTI, 0, 10, 12) mlen 9 rlen 0 {align1};
84-
85-/* EOT */
86-mov(8) g112.0<1>UD g0.0<8,8,1>UD {align1};
87-send(16) 112 null<1>UW null thread_spawner(0, 0, 1) mlen 1 rlen 0 {align1 EOT};
--- a/src/shaders/post_processing/gen8/clear_pl2_8bit.g8b
+++ /dev/null
@@ -1,18 +0,0 @@
1- { 0x00600001, 0x22000208, 0x008d0000, 0x00000000 },
2- { 0x00200009, 0x22001208, 0x1e450004, 0x00040004 },
3- { 0x00000001, 0x22080608, 0x00000000, 0x000f000f },
4- { 0x00400001, 0x22202288, 0x00000022, 0x00000000 },
5- { 0x00800001, 0x22200208, 0x00000220, 0x00000000 },
6- { 0x00800001, 0x22600208, 0x00000220, 0x00000000 },
7- { 0x00800001, 0x22a00208, 0x00000220, 0x00000000 },
8- { 0x00800001, 0x22e00208, 0x00000220, 0x00000000 },
9- { 0x0c800031, 0x24000a40, 0x0e000200, 0x120a8001 },
10- { 0x00000009, 0x22001208, 0x1e000004, 0x00040004 },
11- { 0x00000009, 0x22041208, 0x1e000006, 0x00030003 },
12- { 0x00000001, 0x22080608, 0x00000000, 0x0007000f },
13- { 0x00200001, 0x22201248, 0x00000020, 0x00000000 },
14- { 0x00800001, 0x22200208, 0x00000220, 0x00000000 },
15- { 0x00800001, 0x22600208, 0x00000220, 0x00000000 },
16- { 0x0c800031, 0x24000a40, 0x0e000200, 0x0a0a8002 },
17- { 0x00600001, 0x2e000208, 0x008d0000, 0x00000000 },
18- { 0x07800031, 0x20000a40, 0x0e000e00, 0x82000010 },
--- a/src/shaders/post_processing/gen8/clear_pl2_8bit.gxa
+++ /dev/null
@@ -1,96 +0,0 @@
1-/*
2- * Copyright © 2018 Intel Corporation
3- *
4- * Permission is hereby granted, free of charge, to any person obtaining a
5- * copy of this software and associated documentation files (the
6- * "Software"), to deal in the Software without restriction, including
7- * without limitation the rights to use, copy, modify, merge, publish,
8- * distribute, sub license, and/or sell copies of the Software, and to
9- * permit persons to whom the Software is furnished to do so, subject to
10- * the following conditions:
11- *
12- * The above copyright notice and this permission notice (including the
13- * next paragraph) shall be included in all copies or substantial portions
14- * of the Software.
15- *
16- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19- * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
20- * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23- *
24- * Authors:
25- * Xiang Haihao <haihao.xiang@intel.com>
26- *
27- */
28-
29-/*
30- * Registers
31- * g0 header
32- * g1-g3 static parameters (constant)
33- * g16-g24 payload for write message
34- */
35-define(`ORIG', `g0.4<2,2,1>UW')
36-define(`ORIGX', `g0.4<0,1,0>UW')
37-define(`ORIGY', `g0.6<0,1,0>UW')
38-
39-define(`ALPHA', `g1.3<0,1,0>UB')
40-/* Y */
41-define(`Y', `g1.2<0,1,0>UB')
42-/* V */
43-define(`CR', `g1.1<0,1,0>UB')
44-/* U */
45-define(`CB', `g1.0<0,1,0>UB')
46-define(`CBCR', `g1.0<0,1,0>UW')
47-
48-define(`Y_BTI', `1')
49-define(`CB_BTI', `2')
50-define(`CBCR_BTI', `2')
51-define(`CR_BTI', `3')
52-
53-/* Thread header */
54-mov(8) g16.0<1>UD g0.0<8,8,1>UD {align1};
55-
56-/* Y */
57-shl(2) g16.0<1>UD ORIG 4:w {align1};
58-/* 16x16 block */
59-mov(1) g16.8<1>UD 0x000f000fUD {align1};
60-
61-mov(4) g17.0<1>UB Y {align1};
62-mov(16) g17.0<1>UD g17.0<0,1,0>UD {align1 compr};
63-mov(16) g19.0<1>UD g17.0<0,1,0>UD {align1 compr};
64-mov(16) g21.0<1>UD g17.0<0,1,0>UD {align1 compr};
65-mov(16) g23.0<1>UD g17.0<0,1,0>UD {align1 compr};
66-/*
67- * write(p0, p1, p2, p3)
68- * p0: binding table index
69- * p1: message control, default is 0,
70- * p2: message type, 10 is media_block_write
71- * p3: cache type, 12 is data cache data port 1
72- */
73-send(16) 16 acc0<1>UW null write(Y_BTI, 0, 10, 12) mlen 9 rlen 0 {align1};
74-
75-/* UV */
76-shl(1) g16.0<1>UD ORIGX 4:w {align1};
77-shl(1) g16.4<1>UD ORIGY 3:w {align1};
78-
79-/* 16x8 block */
80-mov(1) g16.8<1>UD 0x0007000fUD {align1};
81-
82-mov(2) g17.0<1>UW CBCR {align1};
83-mov(16) g17.0<1>UD g17.0<0,1,0>UD {align1 compr};
84-mov(16) g19.0<1>UD g17.0<0,1,0>UD {align1 compr};
85-/*
86- * write(p0, p1, p2, p3)
87- * p0: binding table index
88- * p1: message control, default is 0,
89- * p2: message type, 10 is media_block_write
90- * p3: cache type, 12 is data cache data port 1
91- */
92-send(16) 16 acc0<1>UW null write(CBCR_BTI, 0, 10, 12) mlen 5 rlen 0 {align1};
93-
94-/* EOT */
95-mov(8) g112.0<1>UD g0.0<8,8,1>UD {align1};
96-send(16) 112 null<1>UW null thread_spawner(0, 0, 1) mlen 1 rlen 0 {align1 EOT};
--- a/src/shaders/post_processing/gen8/clear_pl3_8bit.g8b
+++ /dev/null
@@ -1,20 +0,0 @@
1- { 0x00600001, 0x22000208, 0x008d0000, 0x00000000 },
2- { 0x00200009, 0x22001208, 0x1e450004, 0x00040004 },
3- { 0x00000001, 0x22080608, 0x00000000, 0x000f000f },
4- { 0x00400001, 0x22202288, 0x00000022, 0x00000000 },
5- { 0x00800001, 0x22200208, 0x00000220, 0x00000000 },
6- { 0x00800001, 0x22600208, 0x00000220, 0x00000000 },
7- { 0x00800001, 0x22a00208, 0x00000220, 0x00000000 },
8- { 0x00800001, 0x22e00208, 0x00000220, 0x00000000 },
9- { 0x0c800031, 0x24000a40, 0x0e000200, 0x120a8001 },
10- { 0x00000009, 0x22001208, 0x1e000004, 0x00030003 },
11- { 0x00000009, 0x22041208, 0x1e000006, 0x00030003 },
12- { 0x00000001, 0x22080608, 0x00000000, 0x00070007 },
13- { 0x00400001, 0x22202288, 0x00000020, 0x00000000 },
14- { 0x00800001, 0x22200208, 0x00000220, 0x00000000 },
15- { 0x0c800031, 0x24000a40, 0x0e000200, 0x060a8002 },
16- { 0x00400001, 0x22202288, 0x00000021, 0x00000000 },
17- { 0x00800001, 0x22200208, 0x00000220, 0x00000000 },
18- { 0x0c800031, 0x24000a40, 0x0e000200, 0x060a8003 },
19- { 0x00600001, 0x2e000208, 0x008d0000, 0x00000000 },
20- { 0x07800031, 0x20000a40, 0x0e000e00, 0x82000010 },
--- a/src/shaders/post_processing/gen8/clear_pl3_8bit.gxa
+++ /dev/null
@@ -1,109 +0,0 @@
1-/*
2- * Copyright © 2018 Intel Corporation
3- *
4- * Permission is hereby granted, free of charge, to any person obtaining a
5- * copy of this software and associated documentation files (the
6- * "Software"), to deal in the Software without restriction, including
7- * without limitation the rights to use, copy, modify, merge, publish,
8- * distribute, sub license, and/or sell copies of the Software, and to
9- * permit persons to whom the Software is furnished to do so, subject to
10- * the following conditions:
11- *
12- * The above copyright notice and this permission notice (including the
13- * next paragraph) shall be included in all copies or substantial portions
14- * of the Software.
15- *
16- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19- * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
20- * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23- *
24- * Authors:
25- * Xiang Haihao <haihao.xiang@intel.com>
26- *
27- */
28-
29-/*
30- * Registers
31- * g0 header
32- * g1-g3 static parameters (constant)
33- * g16-g24 payload for write message
34- */
35-define(`ORIG', `g0.4<2,2,1>UW')
36-define(`ORIGX', `g0.4<0,1,0>UW')
37-define(`ORIGY', `g0.6<0,1,0>UW')
38-
39-define(`ALPHA', `g1.3<0,1,0>UB')
40-/* Y */
41-define(`Y', `g1.2<0,1,0>UB')
42-/* V */
43-define(`CR', `g1.1<0,1,0>UB')
44-/* U */
45-define(`CB', `g1.0<0,1,0>UB')
46-define(`CBCR', `g1.0<0,1,0>UW')
47-
48-define(`Y_BTI', `1')
49-define(`CB_BTI', `2')
50-define(`CBCR_BTI', `2')
51-define(`CR_BTI', `3')
52-
53-/* Thread header */
54-mov(8) g16.0<1>UD g0.0<8,8,1>UD {align1};
55-
56-/* Y */
57-shl(2) g16.0<1>UD ORIG 4:w {align1};
58-/* 16x16 block */
59-mov(1) g16.8<1>UD 0x000f000fUD {align1};
60-
61-mov(4) g17.0<1>UB Y {align1};
62-mov(16) g17.0<1>UD g17.0<0,1,0>UD {align1 compr};
63-mov(16) g19.0<1>UD g17.0<0,1,0>UD {align1 compr};
64-mov(16) g21.0<1>UD g17.0<0,1,0>UD {align1 compr};
65-mov(16) g23.0<1>UD g17.0<0,1,0>UD {align1 compr};
66-/*
67- * write(p0, p1, p2, p3)
68- * p0: binding table index
69- * p1: message control, default is 0,
70- * p2: message type, 10 is media_block_write
71- * p3: cache type, 12 is data cache data port 1
72- */
73-send(16) 16 acc0<1>UW null write(Y_BTI, 0, 10, 12) mlen 9 rlen 0 {align1};
74-
75-/* U */
76-shl(1) g16.0<1>UD ORIGX 3:w {align1};
77-shl(1) g16.4<1>UD ORIGY 3:w {align1};
78-
79-/* 8x8 block */
80-mov(1) g16.8<1>UD 0x00070007UD {align1};
81-
82-mov(4) g17.0<1>UB CB {align1};
83-mov(16) g17.0<1>UD g17.0<0,1,0>UD {align1 compr};
84-
85-/*
86- * write(p0, p1, p2, p3)
87- * p0: binding table index
88- * p1: message control, default is 0,
89- * p2: message type, 10 is media_block_write
90- * p3: cache type, 12 is data cache data port 1
91- */
92-send(16) 16 acc0<1>UW null write(CB_BTI, 0, 10, 12) mlen 3 rlen 0 {align1};
93-
94-/* V */
95-mov(4) g17.0<1>UB CR {align1};
96-mov(16) g17.0<1>UD g17.0<0,1,0>UD {align1 compr};
97-
98-/*
99- * write(p0, p1, p2, p3)
100- * p0: binding table index
101- * p1: message control, default is 0,
102- * p2: message type, 10 is media_block_write
103- * p3: cache type, 12 is data cache data port 1
104- */
105-send(16) 16 acc0<1>UW null write(CR_BTI, 0, 10, 12) mlen 3 rlen 0 {align1};
106-
107-/* EOT */
108-mov(8) g112.0<1>UD g0.0<8,8,1>UD {align1};
109-send(16) 112 null<1>UW null thread_spawner(0, 0, 1) mlen 1 rlen 0 {align1 EOT};
--- a/src/shaders/post_processing/gen8/clear_rgbx.g8b
+++ /dev/null
@@ -1,21 +0,0 @@
1- { 0x00600001, 0x22000208, 0x008d0000, 0x00000000 },
2- { 0x00000009, 0x22001208, 0x1e000004, 0x00060006 },
3- { 0x00000009, 0x22041208, 0x1e000006, 0x00040004 },
4- { 0x00000001, 0x22080608, 0x00000000, 0x000f000f },
5- { 0x00000001, 0x22232288, 0x00000023, 0x00000000 },
6- { 0x00000001, 0x22222288, 0x00000020, 0x00000000 },
7- { 0x00000001, 0x22212288, 0x00000021, 0x00000000 },
8- { 0x00000001, 0x22202288, 0x00000022, 0x00000000 },
9- { 0x00800001, 0x22200208, 0x00000220, 0x00000000 },
10- { 0x00800001, 0x22600208, 0x00000220, 0x00000000 },
11- { 0x00800001, 0x22a00208, 0x00000220, 0x00000000 },
12- { 0x00800001, 0x22e00208, 0x00000220, 0x00000000 },
13- { 0x0c800031, 0x24000a40, 0x0e000200, 0x120a8001 },
14- { 0x00000040, 0x22000208, 0x1e000200, 0x00100010 },
15- { 0x0c800031, 0x24000a40, 0x0e000200, 0x120a8001 },
16- { 0x00000040, 0x22000208, 0x1e000200, 0x00100010 },
17- { 0x0c800031, 0x24000a40, 0x0e000200, 0x120a8001 },
18- { 0x00000040, 0x22000208, 0x1e000200, 0x00100010 },
19- { 0x0c800031, 0x24000a40, 0x0e000200, 0x120a8001 },
20- { 0x00600001, 0x2e000208, 0x008d0000, 0x00000000 },
21- { 0x07800031, 0x20000a40, 0x0e000e00, 0x82000010 },
--- a/src/shaders/post_processing/gen8/clear_rgbx.gxa
+++ /dev/null
@@ -1,87 +0,0 @@
1-/*
2- * Copyright © 2018 Intel Corporation
3- *
4- * Permission is hereby granted, free of charge, to any person obtaining a
5- * copy of this software and associated documentation files (the
6- * "Software"), to deal in the Software without restriction, including
7- * without limitation the rights to use, copy, modify, merge, publish,
8- * distribute, sub license, and/or sell copies of the Software, and to
9- * permit persons to whom the Software is furnished to do so, subject to
10- * the following conditions:
11- *
12- * The above copyright notice and this permission notice (including the
13- * next paragraph) shall be included in all copies or substantial portions
14- * of the Software.
15- *
16- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19- * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
20- * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23- *
24- * Authors:
25- * Xiang Haihao <haihao.xiang@intel.com>
26- *
27- */
28-
29-/*
30- * Registers
31- * g0 header
32- * g1-g3 static parameters (constant)
33- * g16-g24 payload for write message
34- */
35-define(`ORIG', `g0.4<2,2,1>UW')
36-define(`ORIGX', `g0.4<0,1,0>UW')
37-define(`ORIGY', `g0.6<0,1,0>UW')
38-
39-define(`ALPHA', `g1.3<0,1,0>UB')
40-/* Red */
41-define(`R', `g1.2<0,1,0>UB')
42-/* Green */
43-define(`G', `g1.1<0,1,0>UB')
44-/* Blue */
45-define(`B', `g1.0<0,1,0>UB')
46-
47-define(`RGBX_BTI', `1')
48-
49-/* Thread header */
50-mov(8) g16.0<1>UD g0.0<8,8,1>UD {align1};
51-
52-/* RGBA/RGBX */
53-shl(1) g16.0<1>UD ORIGX 6:w {align1};
54-shl(1) g16.4<1>UD ORIGY 4:w {align1};
55-
56-/* 16x16 block */
57-mov(1) g16.8<1>UD 0x000f000fUD {align1};
58-
59-mov(1) g17.3<1>UB ALPHA {align1};
60-mov(1) g17.2<1>UB B {align1};
61-mov(1) g17.1<1>UB G {align1};
62-mov(1) g17.0<1>UB R {align1};
63-mov(16) g17.0<1>UD g17.0<0,1,0>UD {align1 compr};
64-mov(16) g19.0<1>UD g17.0<0,1,0>UD {align1 compr};
65-mov(16) g21.0<1>UD g17.0<0,1,0>UD {align1 compr};
66-mov(16) g23.0<1>UD g17.0<0,1,0>UD {align1 compr};
67-/*
68- * write(p0, p1, p2, p3)
69- * p0: binding table index
70- * p1: message control, default is 0,
71- * p2: message type, 10 is media_block_write
72- * p3: cache type, 12 is data cache data port 1
73- */
74-send(16) 16 acc0<1>UW null write(RGBX_BTI, 0, 10, 12) mlen 9 rlen 0 {align1};
75-
76-add(1) g16.0<1>UD g16.0<0,1,0>UD 16:w {align1};
77-send(16) 16 acc0<1>UW null write(RGBX_BTI, 0, 10, 12) mlen 9 rlen 0 {align1};
78-
79-add(1) g16.0<1>UD g16.0<0,1,0>UD 16:w {align1};
80-send(16) 16 acc0<1>UW null write(RGBX_BTI, 0, 10, 12) mlen 9 rlen 0 {align1};
81-
82-add(1) g16.0<1>UD g16.0<0,1,0>UD 16:w {align1};
83-send(16) 16 acc0<1>UW null write(RGBX_BTI, 0, 10, 12) mlen 9 rlen 0 {align1};
84-
85-/* EOT */
86-mov(8) g112.0<1>UD g0.0<8,8,1>UD {align1};
87-send(16) 112 null<1>UW null thread_spawner(0, 0, 1) mlen 1 rlen 0 {align1 EOT};
--- a/src/shaders/post_processing/gen8/clear_uyvy.g8b
+++ /dev/null
@@ -1,16 +0,0 @@
1- { 0x00600001, 0x22000208, 0x008d0000, 0x00000000 },
2- { 0x00000009, 0x22001208, 0x1e000004, 0x00050005 },
3- { 0x00000009, 0x22041208, 0x1e000006, 0x00040004 },
4- { 0x00000001, 0x22080608, 0x00000000, 0x000f000f },
5- { 0x00200001, 0x42212288, 0x00000022, 0x00000000 },
6- { 0x00000001, 0x22202288, 0x00000020, 0x00000000 },
7- { 0x00000001, 0x22222288, 0x00000021, 0x00000000 },
8- { 0x00800001, 0x22200208, 0x00000220, 0x00000000 },
9- { 0x00800001, 0x22600208, 0x00000220, 0x00000000 },
10- { 0x00800001, 0x22a00208, 0x00000220, 0x00000000 },
11- { 0x00800001, 0x22e00208, 0x00000220, 0x00000000 },
12- { 0x0c800031, 0x24000a40, 0x0e000200, 0x120a8001 },
13- { 0x00000040, 0x22000208, 0x1e000200, 0x00100010 },
14- { 0x0c800031, 0x24000a40, 0x0e000200, 0x120a8001 },
15- { 0x00600001, 0x2e000208, 0x008d0000, 0x00000000 },
16- { 0x07800031, 0x20000a40, 0x0e000e00, 0x82000010 },
--- a/src/shaders/post_processing/gen8/clear_uyvy.gxa
+++ /dev/null
@@ -1,84 +0,0 @@
1-/*
2- * Copyright © 2018 Intel Corporation
3- *
4- * Permission is hereby granted, free of charge, to any person obtaining a
5- * copy of this software and associated documentation files (the
6- * "Software"), to deal in the Software without restriction, including
7- * without limitation the rights to use, copy, modify, merge, publish,
8- * distribute, sub license, and/or sell copies of the Software, and to
9- * permit persons to whom the Software is furnished to do so, subject to
10- * the following conditions:
11- *
12- * The above copyright notice and this permission notice (including the
13- * next paragraph) shall be included in all copies or substantial portions
14- * of the Software.
15- *
16- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19- * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
20- * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23- *
24- * Authors:
25- * Xiang Haihao <haihao.xiang@intel.com>
26- *
27- */
28-
29-/*
30- * Registers
31- * g0 header
32- * g1-g3 static parameters (constant)
33- * g16-g24 payload for write message
34- */
35-define(`ORIG', `g0.4<2,2,1>UW')
36-define(`ORIGX', `g0.4<0,1,0>UW')
37-define(`ORIGY', `g0.6<0,1,0>UW')
38-
39-define(`ALPHA', `g1.3<0,1,0>UB')
40-/* Y */
41-define(`Y', `g1.2<0,1,0>UB')
42-/* V */
43-define(`CR', `g1.1<0,1,0>UB')
44-/* U */
45-define(`CB', `g1.0<0,1,0>UB')
46-define(`CBCR', `g1.0<0,1,0>UW')
47-
48-define(`Y_BTI', `1')
49-define(`CB_BTI', `2')
50-define(`CBCR_BTI', `2')
51-define(`CR_BTI', `3')
52-
53-/* Thread header */
54-mov(8) g16.0<1>UD g0.0<8,8,1>UD {align1};
55-
56-/* Y */
57-shl(1) g16.0<1>UD ORIGX 5:w {align1};
58-shl(1) g16.4<1>UD ORIGY 4:w {align1};
59-
60-/* 16x16 block */
61-mov(1) g16.8<1>UD 0x000f000fUD {align1};
62-
63-mov(2) g17.1<2>UB Y {align1};
64-mov(1) g17.0<1>UB CB {align1};
65-mov(1) g17.2<1>UB CR {align1};
66-mov(16) g17.0<1>UD g17.0<0,1,0>UD {align1 compr};
67-mov(16) g19.0<1>UD g17.0<0,1,0>UD {align1 compr};
68-mov(16) g21.0<1>UD g17.0<0,1,0>UD {align1 compr};
69-mov(16) g23.0<1>UD g17.0<0,1,0>UD {align1 compr};
70-/*
71- * write(p0, p1, p2, p3)
72- * p0: binding table index
73- * p1: message control, default is 0,
74- * p2: message type, 10 is media_block_write
75- * p3: cache type, 12 is data cache data port 1
76- */
77-send(16) 16 acc0<1>UW null write(Y_BTI, 0, 10, 12) mlen 9 rlen 0 {align1};
78-
79-add(1) g16.0<1>UD g16.0<0,1,0>UD 16:w {align1};
80-send(16) 16 acc0<1>UW null write(Y_BTI, 0, 10, 12) mlen 9 rlen 0 {align1};
81-
82-/* EOT */
83-mov(8) g112.0<1>UD g0.0<8,8,1>UD {align1};
84-send(16) 112 null<1>UW null thread_spawner(0, 0, 1) mlen 1 rlen 0 {align1 EOT};
--- a/src/shaders/post_processing/gen8/clear_yuy2.g8b
+++ /dev/null
@@ -1,16 +0,0 @@
1- { 0x00600001, 0x22000208, 0x008d0000, 0x00000000 },
2- { 0x00000009, 0x22001208, 0x1e000004, 0x00050005 },
3- { 0x00000009, 0x22041208, 0x1e000006, 0x00040004 },
4- { 0x00000001, 0x22080608, 0x00000000, 0x000f000f },
5- { 0x00200001, 0x42202288, 0x00000022, 0x00000000 },
6- { 0x00000001, 0x22212288, 0x00000020, 0x00000000 },
7- { 0x00000001, 0x22232288, 0x00000021, 0x00000000 },
8- { 0x00800001, 0x22200208, 0x00000220, 0x00000000 },
9- { 0x00800001, 0x22600208, 0x00000220, 0x00000000 },
10- { 0x00800001, 0x22a00208, 0x00000220, 0x00000000 },
11- { 0x00800001, 0x22e00208, 0x00000220, 0x00000000 },
12- { 0x0c800031, 0x24000a40, 0x0e000200, 0x120a8001 },
13- { 0x00000040, 0x22000208, 0x1e000200, 0x00100010 },
14- { 0x0c800031, 0x24000a40, 0x0e000200, 0x120a8001 },
15- { 0x00600001, 0x2e000208, 0x008d0000, 0x00000000 },
16- { 0x07800031, 0x20000a40, 0x0e000e00, 0x82000010 },
--- a/src/shaders/post_processing/gen8/clear_yuy2.gxa
+++ /dev/null
@@ -1,84 +0,0 @@
1-/*
2- * Copyright © 2018 Intel Corporation
3- *
4- * Permission is hereby granted, free of charge, to any person obtaining a
5- * copy of this software and associated documentation files (the
6- * "Software"), to deal in the Software without restriction, including
7- * without limitation the rights to use, copy, modify, merge, publish,
8- * distribute, sub license, and/or sell copies of the Software, and to
9- * permit persons to whom the Software is furnished to do so, subject to
10- * the following conditions:
11- *
12- * The above copyright notice and this permission notice (including the
13- * next paragraph) shall be included in all copies or substantial portions
14- * of the Software.
15- *
16- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19- * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
20- * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23- *
24- * Authors:
25- * Xiang Haihao <haihao.xiang@intel.com>
26- *
27- */
28-
29-/*
30- * Registers
31- * g0 header
32- * g1-g3 static parameters (constant)
33- * g16-g24 payload for write message
34- */
35-define(`ORIG', `g0.4<2,2,1>UW')
36-define(`ORIGX', `g0.4<0,1,0>UW')
37-define(`ORIGY', `g0.6<0,1,0>UW')
38-
39-define(`ALPHA', `g1.3<0,1,0>UB')
40-/* Y */
41-define(`Y', `g1.2<0,1,0>UB')
42-/* V */
43-define(`CR', `g1.1<0,1,0>UB')
44-/* U */
45-define(`CB', `g1.0<0,1,0>UB')
46-define(`CBCR', `g1.0<0,1,0>UW')
47-
48-define(`Y_BTI', `1')
49-define(`CB_BTI', `2')
50-define(`CBCR_BTI', `2')
51-define(`CR_BTI', `3')
52-
53-/* Thread header */
54-mov(8) g16.0<1>UD g0.0<8,8,1>UD {align1};
55-
56-/* Y */
57-shl(1) g16.0<1>UD ORIGX 5:w {align1};
58-shl(1) g16.4<1>UD ORIGY 4:w {align1};
59-
60-/* 16x16 block */
61-mov(1) g16.8<1>UD 0x000f000fUD {align1};
62-
63-mov(2) g17.0<2>UB Y {align1};
64-mov(1) g17.1<1>UB CB {align1};
65-mov(1) g17.3<1>UB CR {align1};
66-mov(16) g17.0<1>UD g17.0<0,1,0>UD {align1 compr};
67-mov(16) g19.0<1>UD g17.0<0,1,0>UD {align1 compr};
68-mov(16) g21.0<1>UD g17.0<0,1,0>UD {align1 compr};
69-mov(16) g23.0<1>UD g17.0<0,1,0>UD {align1 compr};
70-/*
71- * write(p0, p1, p2, p3)
72- * p0: binding table index
73- * p1: message control, default is 0,
74- * p2: message type, 10 is media_block_write
75- * p3: cache type, 12 is data cache data port 1
76- */
77-send(16) 16 acc0<1>UW null write(Y_BTI, 0, 10, 12) mlen 9 rlen 0 {align1};
78-
79-add(1) g16.0<1>UD g16.0<0,1,0>UD 16:w {align1};
80-send(16) 16 acc0<1>UW null write(Y_BTI, 0, 10, 12) mlen 9 rlen 0 {align1};
81-
82-/* EOT */
83-mov(8) g112.0<1>UD g0.0<8,8,1>UD {align1};
84-send(16) 112 null<1>UW null thread_spawner(0, 0, 1) mlen 1 rlen 0 {align1 EOT};
--- a/src/shaders/post_processing/gen9/Makefile.am
+++ b/src/shaders/post_processing/gen9/Makefile.am
@@ -21,15 +21,6 @@ INTEL_PP_G9B = \
2121 pa_to_pa.g9b \
2222 $(NULL)
2323
24-INTEL_PP2_G9B = \
25- clear_bgrx.g9b \
26- clear_pl2_8bit.g9b \
27- clear_pl3_8bit.g9b \
28- clear_rgbx.g9b \
29- clear_yuy2.g9b \
30- clear_uyvy.g9b \
31- $(NULL)
32-
3324 INTEL_PP_G8A = \
3425 EOT.g8a \
3526 PL2_AVS_Buf_0.g8a \
@@ -62,17 +53,14 @@ INTEL_PP_G9A = $(INTEL_PP_G8A)
6253 INTEL_PP_ASM = $(INTEL_PP_G9B:%.g9b=%.asm)
6354 INTEL_PP_GEN9_ASM = $(INTEL_PP_G9B:%.g9b=%.g9s)
6455
65-INTEL_PP2_GXA = $(INTEL_PP2_G9B:%.g9b=%.gxa)
66-INTEL_PP2_GXS = $(INTEL_PP2_G9B:%.gxa=%.gxs)
67-
6856 TARGETS =
6957 if HAVE_GEN4ASM
70-TARGETS += $(INTEL_PP_G9B) $(INTEL_PP2_G9B)
58+TARGETS += $(INTEL_PP_G9B)
7159 endif
7260
7361 all-local: $(TARGETS)
7462
75-SUFFIXES = .g9b .g9s .asm .gxa .gxs
63+SUFFIXES = .g9b .g9s .asm
7664
7765 if HAVE_GEN4ASM
7866 $(INTEL_PP_GEN9_ASM): $(INTEL_PP_ASM) $(INTEL_PP_G9A)
@@ -82,23 +70,15 @@ $(INTEL_PP_GEN9_ASM): $(INTEL_PP_ASM) $(INTEL_PP_G9A)
8270 rm _pp0.$@
8371 .g9s.g9b:
8472 $(AM_V_GEN)$(GEN4ASM) -a -o $@ -g 9 $<
85-
86-.gxa.gxs:
87- $(AM_V_GEN)cpp -P $< > _tmp.$@ && \
88- m4 _tmp.$@ > $@ && \
89- rm _tmp.$@
90-.gxs.g9b:
91- $(AM_V_GEN)$(GEN4ASM) -o $@ -g 9 $<
9273 endif
9374
94-CLEANFILES = $(INTEL_PP_GEN9_ASM) $(INTEL_PP2_GXS)
75+CLEANFILES = $(INTEL_PP_GEN9_ASM)
9576
9677 DISTCLEANFILES = $(TARGETS)
9778
9879 EXTRA_DIST = \
9980 $(INTEL_PP_G9B) \
10081 $(INTEL_PP_PRE_G9B) \
101- $(INTEL_PP2_G9B) \
10282 $(NULL)
10383
10484 # Extra clean files so that maintainer-clean removes *everything*
--- a/src/shaders/post_processing/gen9/clear_bgrx.g9b
+++ /dev/null
@@ -1,21 +0,0 @@
1- { 0x00600001, 0x22000208, 0x008d0000, 0x00000000 },
2- { 0x00000009, 0x22001208, 0x1e000004, 0x00060006 },
3- { 0x00000009, 0x22041208, 0x1e000006, 0x00040004 },
4- { 0x00000001, 0x22080608, 0x00000000, 0x000f000f },
5- { 0x00000001, 0x22232288, 0x00000023, 0x00000000 },
6- { 0x00000001, 0x22222288, 0x00000020, 0x00000000 },
7- { 0x00000001, 0x22212288, 0x00000021, 0x00000000 },
8- { 0x00000001, 0x22202288, 0x00000022, 0x00000000 },
9- { 0x00800001, 0x22200208, 0x00000220, 0x00000000 },
10- { 0x00800001, 0x22600208, 0x00000220, 0x00000000 },
11- { 0x00800001, 0x22a00208, 0x00000220, 0x00000000 },
12- { 0x00800001, 0x22e00208, 0x00000220, 0x00000000 },
13- { 0x0c800031, 0x24000a40, 0x06000200, 0x120a8001 },
14- { 0x00000040, 0x22000208, 0x1e000200, 0x00100010 },
15- { 0x0c800031, 0x24000a40, 0x06000200, 0x120a8001 },
16- { 0x00000040, 0x22000208, 0x1e000200, 0x00100010 },
17- { 0x0c800031, 0x24000a40, 0x06000200, 0x120a8001 },
18- { 0x00000040, 0x22000208, 0x1e000200, 0x00100010 },
19- { 0x0c800031, 0x24000a40, 0x06000200, 0x120a8001 },
20- { 0x00600001, 0x2e000208, 0x008d0000, 0x00000000 },
21- { 0x07800031, 0x20000a40, 0x06000e00, 0x82000010 },
--- a/src/shaders/post_processing/gen9/clear_bgrx.gxa
+++ /dev/null
@@ -1,87 +0,0 @@
1-/*
2- * Copyright © 2018 Intel Corporation
3- *
4- * Permission is hereby granted, free of charge, to any person obtaining a
5- * copy of this software and associated documentation files (the
6- * "Software"), to deal in the Software without restriction, including
7- * without limitation the rights to use, copy, modify, merge, publish,
8- * distribute, sub license, and/or sell copies of the Software, and to
9- * permit persons to whom the Software is furnished to do so, subject to
10- * the following conditions:
11- *
12- * The above copyright notice and this permission notice (including the
13- * next paragraph) shall be included in all copies or substantial portions
14- * of the Software.
15- *
16- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19- * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
20- * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23- *
24- * Authors:
25- * Xiang Haihao <haihao.xiang@intel.com>
26- *
27- */
28-
29-/*
30- * Registers
31- * g0 header
32- * g1-g3 static parameters (constant)
33- * g16-g24 payload for write message
34- */
35-define(`ORIG', `g0.4<2,2,1>UW')
36-define(`ORIGX', `g0.4<0,1,0>UW')
37-define(`ORIGY', `g0.6<0,1,0>UW')
38-
39-define(`ALPHA', `g1.3<0,1,0>UB')
40-/* Red */
41-define(`R', `g1.2<0,1,0>UB')
42-/* Green */
43-define(`G', `g1.1<0,1,0>UB')
44-/* Blue */
45-define(`B', `g1.0<0,1,0>UB')
46-
47-define(`BGRX_BTI', `1')
48-
49-/* Thread header */
50-mov(8) g16.0<1>UD g0.0<8,8,1>UD {align1};
51-
52-/* RGBA/RGBX */
53-shl(1) g16.0<1>UD ORIGX 6:w {align1};
54-shl(1) g16.4<1>UD ORIGY 4:w {align1};
55-
56-/* 16x16 block */
57-mov(1) g16.8<1>UD 0x000f000fUD {align1};
58-
59-mov(1) g17.3<1>UB ALPHA {align1};
60-mov(1) g17.2<1>UB B {align1};
61-mov(1) g17.1<1>UB G {align1};
62-mov(1) g17.0<1>UB R {align1};
63-mov(16) g17.0<1>UD g17.0<0,1,0>UD {align1 compr};
64-mov(16) g19.0<1>UD g17.0<0,1,0>UD {align1 compr};
65-mov(16) g21.0<1>UD g17.0<0,1,0>UD {align1 compr};
66-mov(16) g23.0<1>UD g17.0<0,1,0>UD {align1 compr};
67-/*
68- * write(p0, p1, p2, p3)
69- * p0: binding table index
70- * p1: message control, default is 0,
71- * p2: message type, 10 is media_block_write
72- * p3: cache type, 12 is data cache data port 1
73- */
74-send(16) 16 acc0<1>UW null write(BGRX_BTI, 0, 10, 12) mlen 9 rlen 0 {align1};
75-
76-add(1) g16.0<1>UD g16.0<0,1,0>UD 16:w {align1};
77-send(16) 16 acc0<1>UW null write(BGRX_BTI, 0, 10, 12) mlen 9 rlen 0 {align1};
78-
79-add(1) g16.0<1>UD g16.0<0,1,0>UD 16:w {align1};
80-send(16) 16 acc0<1>UW null write(BGRX_BTI, 0, 10, 12) mlen 9 rlen 0 {align1};
81-
82-add(1) g16.0<1>UD g16.0<0,1,0>UD 16:w {align1};
83-send(16) 16 acc0<1>UW null write(BGRX_BTI, 0, 10, 12) mlen 9 rlen 0 {align1};
84-
85-/* EOT */
86-mov(8) g112.0<1>UD g0.0<8,8,1>UD {align1};
87-send(16) 112 null<1>UW null thread_spawner(0, 0, 1) mlen 1 rlen 0 {align1 EOT};
--- a/src/shaders/post_processing/gen9/clear_pl2_8bit.g9b
+++ /dev/null
@@ -1,18 +0,0 @@
1- { 0x00600001, 0x22000208, 0x008d0000, 0x00000000 },
2- { 0x00200009, 0x22001208, 0x1e450004, 0x00040004 },
3- { 0x00000001, 0x22080608, 0x00000000, 0x000f000f },
4- { 0x00400001, 0x22202288, 0x00000022, 0x00000000 },
5- { 0x00800001, 0x22200208, 0x00000220, 0x00000000 },
6- { 0x00800001, 0x22600208, 0x00000220, 0x00000000 },
7- { 0x00800001, 0x22a00208, 0x00000220, 0x00000000 },
8- { 0x00800001, 0x22e00208, 0x00000220, 0x00000000 },
9- { 0x0c800031, 0x24000a40, 0x06000200, 0x120a8001 },
10- { 0x00000009, 0x22001208, 0x1e000004, 0x00040004 },
11- { 0x00000009, 0x22041208, 0x1e000006, 0x00030003 },
12- { 0x00000001, 0x22080608, 0x00000000, 0x0007000f },
13- { 0x00200001, 0x22201248, 0x00000020, 0x00000000 },
14- { 0x00800001, 0x22200208, 0x00000220, 0x00000000 },
15- { 0x00800001, 0x22600208, 0x00000220, 0x00000000 },
16- { 0x0c800031, 0x24000a40, 0x06000200, 0x0a0a8002 },
17- { 0x00600001, 0x2e000208, 0x008d0000, 0x00000000 },
18- { 0x07800031, 0x20000a40, 0x06000e00, 0x82000010 },
--- a/src/shaders/post_processing/gen9/clear_pl2_8bit.gxa
+++ /dev/null
@@ -1,96 +0,0 @@
1-/*
2- * Copyright © 2018 Intel Corporation
3- *
4- * Permission is hereby granted, free of charge, to any person obtaining a
5- * copy of this software and associated documentation files (the
6- * "Software"), to deal in the Software without restriction, including
7- * without limitation the rights to use, copy, modify, merge, publish,
8- * distribute, sub license, and/or sell copies of the Software, and to
9- * permit persons to whom the Software is furnished to do so, subject to
10- * the following conditions:
11- *
12- * The above copyright notice and this permission notice (including the
13- * next paragraph) shall be included in all copies or substantial portions
14- * of the Software.
15- *
16- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19- * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
20- * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23- *
24- * Authors:
25- * Xiang Haihao <haihao.xiang@intel.com>
26- *
27- */
28-
29-/*
30- * Registers
31- * g0 header
32- * g1-g3 static parameters (constant)
33- * g16-g24 payload for write message
34- */
35-define(`ORIG', `g0.4<2,2,1>UW')
36-define(`ORIGX', `g0.4<0,1,0>UW')
37-define(`ORIGY', `g0.6<0,1,0>UW')
38-
39-define(`ALPHA', `g1.3<0,1,0>UB')
40-/* Y */
41-define(`Y', `g1.2<0,1,0>UB')
42-/* V */
43-define(`CR', `g1.1<0,1,0>UB')
44-/* U */
45-define(`CB', `g1.0<0,1,0>UB')
46-define(`CBCR', `g1.0<0,1,0>UW')
47-
48-define(`Y_BTI', `1')
49-define(`CB_BTI', `2')
50-define(`CBCR_BTI', `2')
51-define(`CR_BTI', `3')
52-
53-/* Thread header */
54-mov(8) g16.0<1>UD g0.0<8,8,1>UD {align1};
55-
56-/* Y */
57-shl(2) g16.0<1>UD ORIG 4:w {align1};
58-/* 16x16 block */
59-mov(1) g16.8<1>UD 0x000f000fUD {align1};
60-
61-mov(4) g17.0<1>UB Y {align1};
62-mov(16) g17.0<1>UD g17.0<0,1,0>UD {align1 compr};
63-mov(16) g19.0<1>UD g17.0<0,1,0>UD {align1 compr};
64-mov(16) g21.0<1>UD g17.0<0,1,0>UD {align1 compr};
65-mov(16) g23.0<1>UD g17.0<0,1,0>UD {align1 compr};
66-/*
67- * write(p0, p1, p2, p3)
68- * p0: binding table index
69- * p1: message control, default is 0,
70- * p2: message type, 10 is media_block_write
71- * p3: cache type, 12 is data cache data port 1
72- */
73-send(16) 16 acc0<1>UW null write(Y_BTI, 0, 10, 12) mlen 9 rlen 0 {align1};
74-
75-/* UV */
76-shl(1) g16.0<1>UD ORIGX 4:w {align1};
77-shl(1) g16.4<1>UD ORIGY 3:w {align1};
78-
79-/* 16x8 block */
80-mov(1) g16.8<1>UD 0x0007000fUD {align1};
81-
82-mov(2) g17.0<1>UW CBCR {align1};
83-mov(16) g17.0<1>UD g17.0<0,1,0>UD {align1 compr};
84-mov(16) g19.0<1>UD g17.0<0,1,0>UD {align1 compr};
85-/*
86- * write(p0, p1, p2, p3)
87- * p0: binding table index
88- * p1: message control, default is 0,
89- * p2: message type, 10 is media_block_write
90- * p3: cache type, 12 is data cache data port 1
91- */
92-send(16) 16 acc0<1>UW null write(CBCR_BTI, 0, 10, 12) mlen 5 rlen 0 {align1};
93-
94-/* EOT */
95-mov(8) g112.0<1>UD g0.0<8,8,1>UD {align1};
96-send(16) 112 null<1>UW null thread_spawner(0, 0, 1) mlen 1 rlen 0 {align1 EOT};
--- a/src/shaders/post_processing/gen9/clear_pl3_8bit.g9b
+++ /dev/null
@@ -1,20 +0,0 @@
1- { 0x00600001, 0x22000208, 0x008d0000, 0x00000000 },
2- { 0x00200009, 0x22001208, 0x1e450004, 0x00040004 },
3- { 0x00000001, 0x22080608, 0x00000000, 0x000f000f },
4- { 0x00400001, 0x22202288, 0x00000022, 0x00000000 },
5- { 0x00800001, 0x22200208, 0x00000220, 0x00000000 },
6- { 0x00800001, 0x22600208, 0x00000220, 0x00000000 },
7- { 0x00800001, 0x22a00208, 0x00000220, 0x00000000 },
8- { 0x00800001, 0x22e00208, 0x00000220, 0x00000000 },
9- { 0x0c800031, 0x24000a40, 0x06000200, 0x120a8001 },
10- { 0x00000009, 0x22001208, 0x1e000004, 0x00030003 },
11- { 0x00000009, 0x22041208, 0x1e000006, 0x00030003 },
12- { 0x00000001, 0x22080608, 0x00000000, 0x00070007 },
13- { 0x00400001, 0x22202288, 0x00000020, 0x00000000 },
14- { 0x00800001, 0x22200208, 0x00000220, 0x00000000 },
15- { 0x0c800031, 0x24000a40, 0x06000200, 0x060a8002 },
16- { 0x00400001, 0x22202288, 0x00000021, 0x00000000 },
17- { 0x00800001, 0x22200208, 0x00000220, 0x00000000 },
18- { 0x0c800031, 0x24000a40, 0x06000200, 0x060a8003 },
19- { 0x00600001, 0x2e000208, 0x008d0000, 0x00000000 },
20- { 0x07800031, 0x20000a40, 0x06000e00, 0x82000010 },
--- a/src/shaders/post_processing/gen9/clear_pl3_8bit.gxa
+++ /dev/null
@@ -1,109 +0,0 @@
1-/*
2- * Copyright © 2018 Intel Corporation
3- *
4- * Permission is hereby granted, free of charge, to any person obtaining a
5- * copy of this software and associated documentation files (the
6- * "Software"), to deal in the Software without restriction, including
7- * without limitation the rights to use, copy, modify, merge, publish,
8- * distribute, sub license, and/or sell copies of the Software, and to
9- * permit persons to whom the Software is furnished to do so, subject to
10- * the following conditions:
11- *
12- * The above copyright notice and this permission notice (including the
13- * next paragraph) shall be included in all copies or substantial portions
14- * of the Software.
15- *
16- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19- * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
20- * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23- *
24- * Authors:
25- * Xiang Haihao <haihao.xiang@intel.com>
26- *
27- */
28-
29-/*
30- * Registers
31- * g0 header
32- * g1-g3 static parameters (constant)
33- * g16-g24 payload for write message
34- */
35-define(`ORIG', `g0.4<2,2,1>UW')
36-define(`ORIGX', `g0.4<0,1,0>UW')
37-define(`ORIGY', `g0.6<0,1,0>UW')
38-
39-define(`ALPHA', `g1.3<0,1,0>UB')
40-/* Y */
41-define(`Y', `g1.2<0,1,0>UB')
42-/* V */
43-define(`CR', `g1.1<0,1,0>UB')
44-/* U */
45-define(`CB', `g1.0<0,1,0>UB')
46-define(`CBCR', `g1.0<0,1,0>UW')
47-
48-define(`Y_BTI', `1')
49-define(`CB_BTI', `2')
50-define(`CBCR_BTI', `2')
51-define(`CR_BTI', `3')
52-
53-/* Thread header */
54-mov(8) g16.0<1>UD g0.0<8,8,1>UD {align1};
55-
56-/* Y */
57-shl(2) g16.0<1>UD ORIG 4:w {align1};
58-/* 16x16 block */
59-mov(1) g16.8<1>UD 0x000f000fUD {align1};
60-
61-mov(4) g17.0<1>UB Y {align1};
62-mov(16) g17.0<1>UD g17.0<0,1,0>UD {align1 compr};
63-mov(16) g19.0<1>UD g17.0<0,1,0>UD {align1 compr};
64-mov(16) g21.0<1>UD g17.0<0,1,0>UD {align1 compr};
65-mov(16) g23.0<1>UD g17.0<0,1,0>UD {align1 compr};
66-/*
67- * write(p0, p1, p2, p3)
68- * p0: binding table index
69- * p1: message control, default is 0,
70- * p2: message type, 10 is media_block_write
71- * p3: cache type, 12 is data cache data port 1
72- */
73-send(16) 16 acc0<1>UW null write(Y_BTI, 0, 10, 12) mlen 9 rlen 0 {align1};
74-
75-/* U */
76-shl(1) g16.0<1>UD ORIGX 3:w {align1};
77-shl(1) g16.4<1>UD ORIGY 3:w {align1};
78-
79-/* 8x8 block */
80-mov(1) g16.8<1>UD 0x00070007UD {align1};
81-
82-mov(4) g17.0<1>UB CB {align1};
83-mov(16) g17.0<1>UD g17.0<0,1,0>UD {align1 compr};
84-
85-/*
86- * write(p0, p1, p2, p3)
87- * p0: binding table index
88- * p1: message control, default is 0,
89- * p2: message type, 10 is media_block_write
90- * p3: cache type, 12 is data cache data port 1
91- */
92-send(16) 16 acc0<1>UW null write(CB_BTI, 0, 10, 12) mlen 3 rlen 0 {align1};
93-
94-/* V */
95-mov(4) g17.0<1>UB CR {align1};
96-mov(16) g17.0<1>UD g17.0<0,1,0>UD {align1 compr};
97-
98-/*
99- * write(p0, p1, p2, p3)
100- * p0: binding table index
101- * p1: message control, default is 0,
102- * p2: message type, 10 is media_block_write
103- * p3: cache type, 12 is data cache data port 1
104- */
105-send(16) 16 acc0<1>UW null write(CR_BTI, 0, 10, 12) mlen 3 rlen 0 {align1};
106-
107-/* EOT */
108-mov(8) g112.0<1>UD g0.0<8,8,1>UD {align1};
109-send(16) 112 null<1>UW null thread_spawner(0, 0, 1) mlen 1 rlen 0 {align1 EOT};
--- a/src/shaders/post_processing/gen9/clear_rgbx.g9b
+++ /dev/null
@@ -1,21 +0,0 @@
1- { 0x00600001, 0x22000208, 0x008d0000, 0x00000000 },
2- { 0x00000009, 0x22001208, 0x1e000004, 0x00060006 },
3- { 0x00000009, 0x22041208, 0x1e000006, 0x00040004 },
4- { 0x00000001, 0x22080608, 0x00000000, 0x000f000f },
5- { 0x00000001, 0x22232288, 0x00000023, 0x00000000 },
6- { 0x00000001, 0x22222288, 0x00000020, 0x00000000 },
7- { 0x00000001, 0x22212288, 0x00000021, 0x00000000 },
8- { 0x00000001, 0x22202288, 0x00000022, 0x00000000 },
9- { 0x00800001, 0x22200208, 0x00000220, 0x00000000 },
10- { 0x00800001, 0x22600208, 0x00000220, 0x00000000 },
11- { 0x00800001, 0x22a00208, 0x00000220, 0x00000000 },
12- { 0x00800001, 0x22e00208, 0x00000220, 0x00000000 },
13- { 0x0c800031, 0x24000a40, 0x06000200, 0x120a8001 },
14- { 0x00000040, 0x22000208, 0x1e000200, 0x00100010 },
15- { 0x0c800031, 0x24000a40, 0x06000200, 0x120a8001 },
16- { 0x00000040, 0x22000208, 0x1e000200, 0x00100010 },
17- { 0x0c800031, 0x24000a40, 0x06000200, 0x120a8001 },
18- { 0x00000040, 0x22000208, 0x1e000200, 0x00100010 },
19- { 0x0c800031, 0x24000a40, 0x06000200, 0x120a8001 },
20- { 0x00600001, 0x2e000208, 0x008d0000, 0x00000000 },
21- { 0x07800031, 0x20000a40, 0x06000e00, 0x82000010 },
--- a/src/shaders/post_processing/gen9/clear_rgbx.gxa
+++ /dev/null
@@ -1,87 +0,0 @@
1-/*
2- * Copyright © 2018 Intel Corporation
3- *
4- * Permission is hereby granted, free of charge, to any person obtaining a
5- * copy of this software and associated documentation files (the
6- * "Software"), to deal in the Software without restriction, including
7- * without limitation the rights to use, copy, modify, merge, publish,
8- * distribute, sub license, and/or sell copies of the Software, and to
9- * permit persons to whom the Software is furnished to do so, subject to
10- * the following conditions:
11- *
12- * The above copyright notice and this permission notice (including the
13- * next paragraph) shall be included in all copies or substantial portions
14- * of the Software.
15- *
16- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19- * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
20- * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23- *
24- * Authors:
25- * Xiang Haihao <haihao.xiang@intel.com>
26- *
27- */
28-
29-/*
30- * Registers
31- * g0 header
32- * g1-g3 static parameters (constant)
33- * g16-g24 payload for write message
34- */
35-define(`ORIG', `g0.4<2,2,1>UW')
36-define(`ORIGX', `g0.4<0,1,0>UW')
37-define(`ORIGY', `g0.6<0,1,0>UW')
38-
39-define(`ALPHA', `g1.3<0,1,0>UB')
40-/* Red */
41-define(`R', `g1.2<0,1,0>UB')
42-/* Green */
43-define(`G', `g1.1<0,1,0>UB')
44-/* Blue */
45-define(`B', `g1.0<0,1,0>UB')
46-
47-define(`RGBX_BTI', `1')
48-
49-/* Thread header */
50-mov(8) g16.0<1>UD g0.0<8,8,1>UD {align1};
51-
52-/* RGBA/RGBX */
53-shl(1) g16.0<1>UD ORIGX 6:w {align1};
54-shl(1) g16.4<1>UD ORIGY 4:w {align1};
55-
56-/* 16x16 block */
57-mov(1) g16.8<1>UD 0x000f000fUD {align1};
58-
59-mov(1) g17.3<1>UB ALPHA {align1};
60-mov(1) g17.2<1>UB B {align1};
61-mov(1) g17.1<1>UB G {align1};
62-mov(1) g17.0<1>UB R {align1};
63-mov(16) g17.0<1>UD g17.0<0,1,0>UD {align1 compr};
64-mov(16) g19.0<1>UD g17.0<0,1,0>UD {align1 compr};
65-mov(16) g21.0<1>UD g17.0<0,1,0>UD {align1 compr};
66-mov(16) g23.0<1>UD g17.0<0,1,0>UD {align1 compr};
67-/*
68- * write(p0, p1, p2, p3)
69- * p0: binding table index
70- * p1: message control, default is 0,
71- * p2: message type, 10 is media_block_write
72- * p3: cache type, 12 is data cache data port 1
73- */
74-send(16) 16 acc0<1>UW null write(RGBX_BTI, 0, 10, 12) mlen 9 rlen 0 {align1};
75-
76-add(1) g16.0<1>UD g16.0<0,1,0>UD 16:w {align1};
77-send(16) 16 acc0<1>UW null write(RGBX_BTI, 0, 10, 12) mlen 9 rlen 0 {align1};
78-
79-add(1) g16.0<1>UD g16.0<0,1,0>UD 16:w {align1};
80-send(16) 16 acc0<1>UW null write(RGBX_BTI, 0, 10, 12) mlen 9 rlen 0 {align1};
81-
82-add(1) g16.0<1>UD g16.0<0,1,0>UD 16:w {align1};
83-send(16) 16 acc0<1>UW null write(RGBX_BTI, 0, 10, 12) mlen 9 rlen 0 {align1};
84-
85-/* EOT */
86-mov(8) g112.0<1>UD g0.0<8,8,1>UD {align1};
87-send(16) 112 null<1>UW null thread_spawner(0, 0, 1) mlen 1 rlen 0 {align1 EOT};
--- a/src/shaders/post_processing/gen9/clear_uyvy.g9b
+++ /dev/null
@@ -1,16 +0,0 @@
1- { 0x00600001, 0x22000208, 0x008d0000, 0x00000000 },
2- { 0x00000009, 0x22001208, 0x1e000004, 0x00050005 },
3- { 0x00000009, 0x22041208, 0x1e000006, 0x00040004 },
4- { 0x00000001, 0x22080608, 0x00000000, 0x000f000f },
5- { 0x00200001, 0x42212288, 0x00000022, 0x00000000 },
6- { 0x00000001, 0x22202288, 0x00000020, 0x00000000 },
7- { 0x00000001, 0x22222288, 0x00000021, 0x00000000 },
8- { 0x00800001, 0x22200208, 0x00000220, 0x00000000 },
9- { 0x00800001, 0x22600208, 0x00000220, 0x00000000 },
10- { 0x00800001, 0x22a00208, 0x00000220, 0x00000000 },
11- { 0x00800001, 0x22e00208, 0x00000220, 0x00000000 },
12- { 0x0c800031, 0x24000a40, 0x06000200, 0x120a8001 },
13- { 0x00000040, 0x22000208, 0x1e000200, 0x00100010 },
14- { 0x0c800031, 0x24000a40, 0x06000200, 0x120a8001 },
15- { 0x00600001, 0x2e000208, 0x008d0000, 0x00000000 },
16- { 0x07800031, 0x20000a40, 0x06000e00, 0x82000010 },
--- a/src/shaders/post_processing/gen9/clear_uyvy.gxa
+++ /dev/null
@@ -1,84 +0,0 @@
1-/*
2- * Copyright © 2018 Intel Corporation
3- *
4- * Permission is hereby granted, free of charge, to any person obtaining a
5- * copy of this software and associated documentation files (the
6- * "Software"), to deal in the Software without restriction, including
7- * without limitation the rights to use, copy, modify, merge, publish,
8- * distribute, sub license, and/or sell copies of the Software, and to
9- * permit persons to whom the Software is furnished to do so, subject to
10- * the following conditions:
11- *
12- * The above copyright notice and this permission notice (including the
13- * next paragraph) shall be included in all copies or substantial portions
14- * of the Software.
15- *
16- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19- * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
20- * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23- *
24- * Authors:
25- * Xiang Haihao <haihao.xiang@intel.com>
26- *
27- */
28-
29-/*
30- * Registers
31- * g0 header
32- * g1-g3 static parameters (constant)
33- * g16-g24 payload for write message
34- */
35-define(`ORIG', `g0.4<2,2,1>UW')
36-define(`ORIGX', `g0.4<0,1,0>UW')
37-define(`ORIGY', `g0.6<0,1,0>UW')
38-
39-define(`ALPHA', `g1.3<0,1,0>UB')
40-/* Y */
41-define(`Y', `g1.2<0,1,0>UB')
42-/* V */
43-define(`CR', `g1.1<0,1,0>UB')
44-/* U */
45-define(`CB', `g1.0<0,1,0>UB')
46-define(`CBCR', `g1.0<0,1,0>UW')
47-
48-define(`Y_BTI', `1')
49-define(`CB_BTI', `2')
50-define(`CBCR_BTI', `2')
51-define(`CR_BTI', `3')
52-
53-/* Thread header */
54-mov(8) g16.0<1>UD g0.0<8,8,1>UD {align1};
55-
56-/* Y */
57-shl(1) g16.0<1>UD ORIGX 5:w {align1};
58-shl(1) g16.4<1>UD ORIGY 4:w {align1};
59-
60-/* 16x16 block */
61-mov(1) g16.8<1>UD 0x000f000fUD {align1};
62-
63-mov(2) g17.1<2>UB Y {align1};
64-mov(1) g17.0<1>UB CB {align1};
65-mov(1) g17.2<1>UB CR {align1};
66-mov(16) g17.0<1>UD g17.0<0,1,0>UD {align1 compr};
67-mov(16) g19.0<1>UD g17.0<0,1,0>UD {align1 compr};
68-mov(16) g21.0<1>UD g17.0<0,1,0>UD {align1 compr};
69-mov(16) g23.0<1>UD g17.0<0,1,0>UD {align1 compr};
70-/*
71- * write(p0, p1, p2, p3)
72- * p0: binding table index
73- * p1: message control, default is 0,
74- * p2: message type, 10 is media_block_write
75- * p3: cache type, 12 is data cache data port 1
76- */
77-send(16) 16 acc0<1>UW null write(Y_BTI, 0, 10, 12) mlen 9 rlen 0 {align1};
78-
79-add(1) g16.0<1>UD g16.0<0,1,0>UD 16:w {align1};
80-send(16) 16 acc0<1>UW null write(Y_BTI, 0, 10, 12) mlen 9 rlen 0 {align1};
81-
82-/* EOT */
83-mov(8) g112.0<1>UD g0.0<8,8,1>UD {align1};
84-send(16) 112 null<1>UW null thread_spawner(0, 0, 1) mlen 1 rlen 0 {align1 EOT};
--- a/src/shaders/post_processing/gen9/clear_yuy2.g9b
+++ /dev/null
@@ -1,16 +0,0 @@
1- { 0x00600001, 0x22000208, 0x008d0000, 0x00000000 },
2- { 0x00000009, 0x22001208, 0x1e000004, 0x00050005 },
3- { 0x00000009, 0x22041208, 0x1e000006, 0x00040004 },
4- { 0x00000001, 0x22080608, 0x00000000, 0x000f000f },
5- { 0x00200001, 0x42202288, 0x00000022, 0x00000000 },
6- { 0x00000001, 0x22212288, 0x00000020, 0x00000000 },
7- { 0x00000001, 0x22232288, 0x00000021, 0x00000000 },
8- { 0x00800001, 0x22200208, 0x00000220, 0x00000000 },
9- { 0x00800001, 0x22600208, 0x00000220, 0x00000000 },
10- { 0x00800001, 0x22a00208, 0x00000220, 0x00000000 },
11- { 0x00800001, 0x22e00208, 0x00000220, 0x00000000 },
12- { 0x0c800031, 0x24000a40, 0x06000200, 0x120a8001 },
13- { 0x00000040, 0x22000208, 0x1e000200, 0x00100010 },
14- { 0x0c800031, 0x24000a40, 0x06000200, 0x120a8001 },
15- { 0x00600001, 0x2e000208, 0x008d0000, 0x00000000 },
16- { 0x07800031, 0x20000a40, 0x06000e00, 0x82000010 },
--- a/src/shaders/post_processing/gen9/clear_yuy2.gxa
+++ /dev/null
@@ -1,84 +0,0 @@
1-/*
2- * Copyright © 2018 Intel Corporation
3- *
4- * Permission is hereby granted, free of charge, to any person obtaining a
5- * copy of this software and associated documentation files (the
6- * "Software"), to deal in the Software without restriction, including
7- * without limitation the rights to use, copy, modify, merge, publish,
8- * distribute, sub license, and/or sell copies of the Software, and to
9- * permit persons to whom the Software is furnished to do so, subject to
10- * the following conditions:
11- *
12- * The above copyright notice and this permission notice (including the
13- * next paragraph) shall be included in all copies or substantial portions
14- * of the Software.
15- *
16- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19- * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
20- * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23- *
24- * Authors:
25- * Xiang Haihao <haihao.xiang@intel.com>
26- *
27- */
28-
29-/*
30- * Registers
31- * g0 header
32- * g1-g3 static parameters (constant)
33- * g16-g24 payload for write message
34- */
35-define(`ORIG', `g0.4<2,2,1>UW')
36-define(`ORIGX', `g0.4<0,1,0>UW')
37-define(`ORIGY', `g0.6<0,1,0>UW')
38-
39-define(`ALPHA', `g1.3<0,1,0>UB')
40-/* Y */
41-define(`Y', `g1.2<0,1,0>UB')
42-/* V */
43-define(`CR', `g1.1<0,1,0>UB')
44-/* U */
45-define(`CB', `g1.0<0,1,0>UB')
46-define(`CBCR', `g1.0<0,1,0>UW')
47-
48-define(`Y_BTI', `1')
49-define(`CB_BTI', `2')
50-define(`CBCR_BTI', `2')
51-define(`CR_BTI', `3')
52-
53-/* Thread header */
54-mov(8) g16.0<1>UD g0.0<8,8,1>UD {align1};
55-
56-/* Y */
57-shl(1) g16.0<1>UD ORIGX 5:w {align1};
58-shl(1) g16.4<1>UD ORIGY 4:w {align1};
59-
60-/* 16x16 block */
61-mov(1) g16.8<1>UD 0x000f000fUD {align1};
62-
63-mov(2) g17.0<2>UB Y {align1};
64-mov(1) g17.1<1>UB CB {align1};
65-mov(1) g17.3<1>UB CR {align1};
66-mov(16) g17.0<1>UD g17.0<0,1,0>UD {align1 compr};
67-mov(16) g19.0<1>UD g17.0<0,1,0>UD {align1 compr};
68-mov(16) g21.0<1>UD g17.0<0,1,0>UD {align1 compr};
69-mov(16) g23.0<1>UD g17.0<0,1,0>UD {align1 compr};
70-/*
71- * write(p0, p1, p2, p3)
72- * p0: binding table index
73- * p1: message control, default is 0,
74- * p2: message type, 10 is media_block_write
75- * p3: cache type, 12 is data cache data port 1
76- */
77-send(16) 16 acc0<1>UW null write(Y_BTI, 0, 10, 12) mlen 9 rlen 0 {align1};
78-
79-add(1) g16.0<1>UD g16.0<0,1,0>UD 16:w {align1};
80-send(16) 16 acc0<1>UW null write(Y_BTI, 0, 10, 12) mlen 9 rlen 0 {align1};
81-
82-/* EOT */
83-mov(8) g112.0<1>UD g0.0<8,8,1>UD {align1};
84-send(16) 112 null<1>UW null thread_spawner(0, 0, 1) mlen 1 rlen 0 {align1 EOT};
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