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external-mesa: Commit

external/mesa


Commit MetaInfo

Revision773abf86556db420a3778132816f16beb317d81f (tree)
Time2019-02-20 12:24:22
AuthorChih-Wei Huang <cwhuang@linu...>
CommiterChih-Wei Huang

Log Message

Merge remote-tracking branch 'mesa/18.3' into oreo-x86

Change Summary

Incremental Difference

--- a/VERSION
+++ b/VERSION
@@ -1 +1 @@
1-18.3.3
1+18.3.4
--- a/bin/.cherry-ignore
+++ b/bin/.cherry-ignore
@@ -14,3 +14,25 @@ abfe674c54bee6f8fdcae411b07db89c10b9d530 spirv: Handle arbitrary bit sizes for d
1414 # warn The commits refer stale sha, yet don't fix anything in particular.
1515 98984b7cdd79c15cc7331c791f8be61e873b8bbd Revert "mapi/new: sort by slot number"
1616 9f86f1da7c68b5b900cd6f60925610ff1225a72d egl: add glvnd entrypoints for EGL_MESA_query_driver
17+
18+# stable Explicit 19.0 only nomination.
19+38f542783faa360020b77fdd76b97f207a9e0068 v50,nvc0: add explicit settings for recent caps
20+
21+# stable Explicit 19.0 only nominations.
22+399215eb7a0517463e5757c598d6cff6ae2301d0 nvc0: add support for handling indirect draws with attrib conversion
23+4443b6ddf2e08d06f3d0457cf20a2e04244cde37 nvc0/ir: always use CG mode for loads from atomic-only buffers
24+5de5beedf21306b01730085f8e03d8f424729016 nvc0/ir: fix second tex argument after levelZero optimization
25+162352e6711b3ceab114686f7a3248074339e7f7 nvc0: fix 3d images on kepler
26+e00799d3dc0595dc3998dbf199ceec8b1eece966 nv50,nvc0: use condition for occlusion queries when already complete
27+6adb9b38bfb1f6ee4c94596bf0744225aa8e967a nvc0: stick zero values for the compute invocation counts
28+04593d9a73ea257a36cc3b9fb5cd41427beaaea5 gk110/ir: Add rcp f64 implementation
29+7937408052a1896f0b08b0110bb8a1790eeee351 gk110/ir: Add rsq f64 implementation
30+656ad060518d067a3b311db8c2de2a396fb41898 gk110/ir: Use the new rcp/rsq in library
31+12669d29705a26478aa691cb454149628be65f17 gk104/ir: Use the new rcp/rsq in library
32+815a8e59c6d462a7008653ea9e3010d40b6ba589 gm107/ir: add fp64 rcp
33+cce495572136a606dd2a35e79f45080c3796e2cc gm107/ir: add fp64 rsq
34+6010d7b8e8bee1bcea2b329cf6d3b44c5fc3ca66 gallium: add PIPE_CAP_MAX_VARYINGS
35+cbd1ad6165f0aea7fb7c6fd1b36ad5317dd65cb7 st/mesa: require RGBA2, RGB4, and RGBA4 to be renderable
36+
37+# stable The commit addresses functionality not present in branch
38+1b8983c25be19073c02fe9630e949be55f8280fa radv: fix using LOAD_CONTEXT_REG with old GFX ME firmwares on GFX8
--- a/bin/get-pick-list.sh
+++ b/bin/get-pick-list.sh
@@ -13,12 +13,12 @@
1313
1414 is_stable_nomination()
1515 {
16- git show --summary "$1" | grep -q -i -o "CC:.*mesa-stable"
16+ git show --pretty=medium --summary "$1" | grep -q -i -o "CC:.*mesa-stable"
1717 }
1818
1919 is_typod_nomination()
2020 {
21- git show --summary "$1" | grep -q -i -o "CC:.*mesa-dev"
21+ git show --pretty=medium --summary "$1" | grep -q -i -o "CC:.*mesa-dev"
2222 }
2323
2424 fixes=
--- /dev/null
+++ b/docs/relnotes/18.3.4.html
@@ -0,0 +1,180 @@
1+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
2+<html lang="en">
3+<head>
4+ <meta http-equiv="content-type" content="text/html; charset=utf-8">
5+ <title>Mesa Release Notes</title>
6+ <link rel="stylesheet" type="text/css" href="../mesa.css">
7+</head>
8+<body>
9+
10+<div class="header">
11+ <h1>The Mesa 3D Graphics Library</h1>
12+</div>
13+
14+<iframe src="../contents.html"></iframe>
15+<div class="content">
16+
17+<h1>Mesa 18.3.4 Release Notes / February 18, 2019</h1>
18+
19+<p>
20+Mesa 18.3.4 is a bug fix release which fixes bugs found since the 18.3.3 release.
21+</p>
22+<p>
23+Mesa 18.3.4 implements the OpenGL 4.5 API, but the version reported by
24+glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
25+glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
26+Some drivers don't support all the features required in OpenGL 4.5. OpenGL
27+4.5 is <strong>only</strong> available if requested at context creation.
28+Compatibility contexts may report a lower version depending on each driver.
29+</p>
30+
31+
32+<h2>SHA256 checksums</h2>
33+<pre>
34+e22e6fe4c3aca80fe872a0a7285b6c5523e0cfc0bfb57ffcc3b3d66d292593e4 mesa-18.3.4.tar.gz
35+32314da4365d37f80d84f599bd9625b00161c273c39600ba63b45002d500bb07 mesa-18.3.4.tar.xz
36+</pre>
37+
38+
39+<h2>New features</h2>
40+<p>None</p>
41+
42+
43+<h2>Bug fixes</h2>
44+
45+<ul>
46+
47+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=109107">Bug 109107</a> - gallium/st/va: change va max_profiles when using Radeon VCN Hardware</li>
48+
49+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=109401">Bug 109401</a> - [DXVK] Project Cars rendering problems</li>
50+
51+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=109543">Bug 109543</a> - After upgrade mesa to 19.0.0~rc1 all vulkan based application stop working [&quot;vulkan-cube&quot; received SIGSEGV in radv_pipeline_init_blend_state at ../src/amd/vulkan/radv_pipeline.c:699]</li>
52+
53+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=109603">Bug 109603</a> - nir_instr_as_deref: Assertion `parent &amp;&amp; parent-&gt;type == nir_instr_type_deref' failed.</li>
54+
55+</ul>
56+
57+
58+<h2>Changes</h2>
59+
60+<p>Bart Oldeman (1):</p>
61+<ul>
62+ <li>gallium-xlib: query MIT-SHM before using it.</li>
63+</ul>
64+
65+<p>Bas Nieuwenhuizen (2):</p>
66+<ul>
67+ <li>radv: Only look at pImmutableSamples if the descriptor has a sampler.</li>
68+ <li>amd/common: Use correct writemask for shared memory stores.</li>
69+</ul>
70+
71+<p>Dylan Baker (2):</p>
72+<ul>
73+ <li>get-pick-list: Add --pretty=medium to the arguments for Cc patches</li>
74+ <li>meson: Add dependency on genxml to anvil</li>
75+</ul>
76+
77+<p>Emil Velikov (5):</p>
78+<ul>
79+ <li>docs: add sha256 checksums for 18.3.3</li>
80+ <li>cherry-ignore: nv50,nvc0: add explicit settings for recent caps</li>
81+ <li>cherry-ignore: add more 19.0 only nominations from Ilia</li>
82+ <li>cherry-ignore: radv: fix using LOAD_CONTEXT_REG with old GFX ME firmwares on GFX8</li>
83+ <li>Update version to 18.3.4</li>
84+</ul>
85+
86+<p>Eric Anholt (1):</p>
87+<ul>
88+ <li>vc4: Fix copy-and-paste fail in backport of NEON asm fixes.</li>
89+</ul>
90+
91+<p>Eric Engestrom (2):</p>
92+<ul>
93+ <li>xvmc: fix string comparison</li>
94+ <li>xvmc: fix string comparison</li>
95+</ul>
96+
97+<p>Ernestas Kulik (2):</p>
98+<ul>
99+ <li>vc4: Fix leak in HW queries error path</li>
100+ <li>v3d: Fix leak in resource setup error path</li>
101+</ul>
102+
103+<p>Iago Toral Quiroga (1):</p>
104+<ul>
105+ <li>intel/compiler: do not copy-propagate strided regions to ddx/ddy arguments</li>
106+</ul>
107+
108+<p>Ilia Mirkin (1):</p>
109+<ul>
110+ <li>nvc0: we have 16k-sized framebuffers, fix default scissors</li>
111+</ul>
112+
113+<p>Jason Ekstrand (3):</p>
114+<ul>
115+ <li>intel/fs: Handle IMAGE_SIZE in size_read() and is_send_from_grf()</li>
116+ <li>intel/fs: Do the grf127 hack on SIMD8 instructions in SIMD16 mode</li>
117+ <li>nir/deref: Rematerialize parents in rematerialize_derefs_in_use_blocks</li>
118+</ul>
119+
120+<p>Juan A. Suarez Romero (1):</p>
121+<ul>
122+ <li>anv/cmd_buffer: check for NULL framebuffer</li>
123+</ul>
124+
125+<p>Kenneth Graunke (1):</p>
126+<ul>
127+ <li>st/mesa: Limit GL_MAX_[NATIVE_]PROGRAM_PARAMETERS_ARB to 2048</li>
128+</ul>
129+
130+<p>Kristian H. Kristensen (1):</p>
131+<ul>
132+ <li>freedreno/a6xx: Emit blitter dst with OUT_RELOCW</li>
133+</ul>
134+
135+<p>Leo Liu (2):</p>
136+<ul>
137+ <li>st/va: fix the incorrect max profiles report</li>
138+ <li>st/va/vp9: set max reference as default of VP9 reference number</li>
139+</ul>
140+
141+<p>Marek Olšák (4):</p>
142+<ul>
143+ <li>meson: drop the xcb-xrandr version requirement</li>
144+ <li>gallium/u_threaded: fix EXPLICIT_FLUSH for flush offsets &gt; 0</li>
145+ <li>radeonsi: fix EXPLICIT_FLUSH for flush offsets &gt; 0</li>
146+ <li>winsys/amdgpu: don't drop manually added fence dependencies</li>
147+</ul>
148+
149+<p>Mario Kleiner (2):</p>
150+<ul>
151+ <li>egl/wayland: Allow client-&gt;server format conversion for PRIME offload. (v2)</li>
152+ <li>egl/wayland-drm: Only announce formats via wl_drm which the driver supports.</li>
153+</ul>
154+
155+<p>Oscar Blumberg (1):</p>
156+<ul>
157+ <li>radeonsi: Fix guardband computation for large render targets</li>
158+</ul>
159+
160+<p>Rob Clark (1):</p>
161+<ul>
162+ <li>freedreno: stop frob'ing pipe_resource::nr_samples</li>
163+</ul>
164+
165+<p>Rodrigo Vivi (1):</p>
166+<ul>
167+ <li>intel: Add more PCI Device IDs for Coffee Lake and Ice Lake.</li>
168+</ul>
169+
170+<p>Samuel Pitoiset (2):</p>
171+<ul>
172+ <li>radv: fix compiler issues with GCC 9</li>
173+ <li>radv: always export gl_SampleMask when the fragment shader uses it</li>
174+</ul>
175+
176+
177+
178+</div>
179+</body>
180+</html>
--- a/include/pci_ids/i965_pci_ids.h
+++ b/include/pci_ids/i965_pci_ids.h
@@ -171,6 +171,7 @@ CHIPSET(0x3185, glk_2x6, "Intel(R) UHD Graphics 600 (Geminilake 2x6)")
171171 CHIPSET(0x3E90, cfl_gt1, "Intel(R) UHD Graphics 610 (Coffeelake 2x6 GT1)")
172172 CHIPSET(0x3E93, cfl_gt1, "Intel(R) UHD Graphics 610 (Coffeelake 2x6 GT1)")
173173 CHIPSET(0x3E99, cfl_gt1, "Intel(R) HD Graphics (Coffeelake 2x6 GT1)")
174+CHIPSET(0x3E9C, cfl_gt1, "Intel(R) HD Graphics (Coffeelake 2x6 GT1)")
174175 CHIPSET(0x3E91, cfl_gt2, "Intel(R) UHD Graphics 630 (Coffeelake 3x8 GT2)")
175176 CHIPSET(0x3E92, cfl_gt2, "Intel(R) UHD Graphics 630 (Coffeelake 3x8 GT2)")
176177 CHIPSET(0x3E96, cfl_gt2, "Intel(R) HD Graphics (Coffeelake 3x8 GT2)")
@@ -203,6 +204,10 @@ CHIPSET(0x5A54, cnl_5x8, "Intel(R) HD Graphics (Cannonlake 5x8 GT2)")
203204 CHIPSET(0x8A50, icl_8x8, "Intel(R) HD Graphics (Ice Lake 8x8 GT2)")
204205 CHIPSET(0x8A51, icl_8x8, "Intel(R) HD Graphics (Ice Lake 8x8 GT2)")
205206 CHIPSET(0x8A52, icl_8x8, "Intel(R) HD Graphics (Ice Lake 8x8 GT2)")
207+CHIPSET(0x8A56, icl_4x8, "Intel(R) HD Graphics (Ice Lake 4x8 GT1)")
208+CHIPSET(0x8A57, icl_6x8, "Intel(R) HD Graphics (Ice Lake 6x8 GT1.5)")
209+CHIPSET(0x8A58, icl_4x8, "Intel(R) HD Graphics (Ice Lake 4x8 GT1)")
210+CHIPSET(0x8A59, icl_6x8, "Intel(R) HD Graphics (Ice Lake 6x8 GT1.5)")
206211 CHIPSET(0x8A5A, icl_6x8, "Intel(R) HD Graphics (Ice Lake 6x8 GT1.5)")
207212 CHIPSET(0x8A5B, icl_4x8, "Intel(R) HD Graphics (Ice Lake 4x8 GT1)")
208213 CHIPSET(0x8A5C, icl_6x8, "Intel(R) HD Graphics (Ice Lake 6x8 GT1.5)")
--- a/meson.build
+++ b/meson.build
@@ -1407,7 +1407,7 @@ if with_platform_x11
14071407 dep_xcb_xfixes = dependency('xcb-xfixes')
14081408 endif
14091409 if with_xlib_lease
1410- dep_xcb_xrandr = dependency('xcb-randr', version : '>= 1.12')
1410+ dep_xcb_xrandr = dependency('xcb-randr')
14111411 dep_xlib_xrandr = dependency('xrandr', version : '>= 1.3')
14121412 endif
14131413 endif
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -2072,7 +2072,7 @@ visit_store_var(struct ac_nir_context *ctx,
20722072 int writemask = instr->const_index[0];
20732073 LLVMValueRef address = get_src(ctx, instr->src[0]);
20742074 LLVMValueRef val = get_src(ctx, instr->src[1]);
2075- if (util_is_power_of_two_nonzero(writemask)) {
2075+ if (writemask == (1u << ac_get_llvm_num_components(val)) - 1) {
20762076 val = LLVMBuildBitCast(
20772077 ctx->ac.builder, val,
20782078 LLVMGetElementType(LLVMTypeOf(address)), "");
--- a/src/amd/vulkan/radv_descriptor_set.c
+++ b/src/amd/vulkan/radv_descriptor_set.c
@@ -84,7 +84,9 @@ VkResult radv_CreateDescriptorSetLayout(
8484 uint32_t immutable_sampler_count = 0;
8585 for (uint32_t j = 0; j < pCreateInfo->bindingCount; j++) {
8686 max_binding = MAX2(max_binding, pCreateInfo->pBindings[j].binding);
87- if (pCreateInfo->pBindings[j].pImmutableSamplers)
87+ if ((pCreateInfo->pBindings[j].descriptorType == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER ||
88+ pCreateInfo->pBindings[j].descriptorType == VK_DESCRIPTOR_TYPE_SAMPLER) &&
89+ pCreateInfo->pBindings[j].pImmutableSamplers)
8890 immutable_sampler_count += pCreateInfo->pBindings[j].descriptorCount;
8991 }
9092
@@ -182,7 +184,9 @@ VkResult radv_CreateDescriptorSetLayout(
182184 set_layout->has_variable_descriptors = true;
183185 }
184186
185- if (binding->pImmutableSamplers) {
187+ if ((binding->descriptorType == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER ||
188+ binding->descriptorType == VK_DESCRIPTOR_TYPE_SAMPLER) &&
189+ binding->pImmutableSamplers) {
186190 set_layout->binding[b].immutable_samplers_offset = samplers_offset;
187191 set_layout->binding[b].immutable_samplers_equal =
188192 has_equal_immutable_samplers(binding->pImmutableSamplers, binding->descriptorCount);
--- a/src/amd/vulkan/radv_meta_blit.c
+++ b/src/amd/vulkan/radv_meta_blit.c
@@ -849,54 +849,60 @@ build_pipeline(struct radv_device *device,
849849 .subpass = 0,
850850 };
851851
852- switch(aspect) {
853- case VK_IMAGE_ASPECT_COLOR_BIT:
854- vk_pipeline_info.pColorBlendState = &(VkPipelineColorBlendStateCreateInfo) {
855- .sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO,
856- .attachmentCount = 1,
857- .pAttachments = (VkPipelineColorBlendAttachmentState []) {
858- { .colorWriteMask =
859- VK_COLOR_COMPONENT_A_BIT |
860- VK_COLOR_COMPONENT_R_BIT |
861- VK_COLOR_COMPONENT_G_BIT |
862- VK_COLOR_COMPONENT_B_BIT },
852+ VkPipelineColorBlendStateCreateInfo color_blend_info = {
853+ .sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO,
854+ .attachmentCount = 1,
855+ .pAttachments = (VkPipelineColorBlendAttachmentState []) {
856+ {
857+ .colorWriteMask = VK_COLOR_COMPONENT_A_BIT |
858+ VK_COLOR_COMPONENT_R_BIT |
859+ VK_COLOR_COMPONENT_G_BIT |
860+ VK_COLOR_COMPONENT_B_BIT },
863861 }
864862 };
863+
864+ VkPipelineDepthStencilStateCreateInfo depth_info = {
865+ .sType = VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO,
866+ .depthTestEnable = true,
867+ .depthWriteEnable = true,
868+ .depthCompareOp = VK_COMPARE_OP_ALWAYS,
869+ };
870+
871+ VkPipelineDepthStencilStateCreateInfo stencil_info = {
872+ .sType = VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO,
873+ .depthTestEnable = false,
874+ .depthWriteEnable = false,
875+ .stencilTestEnable = true,
876+ .front = {
877+ .failOp = VK_STENCIL_OP_REPLACE,
878+ .passOp = VK_STENCIL_OP_REPLACE,
879+ .depthFailOp = VK_STENCIL_OP_REPLACE,
880+ .compareOp = VK_COMPARE_OP_ALWAYS,
881+ .compareMask = 0xff,
882+ .writeMask = 0xff,
883+ .reference = 0
884+ },
885+ .back = {
886+ .failOp = VK_STENCIL_OP_REPLACE,
887+ .passOp = VK_STENCIL_OP_REPLACE,
888+ .depthFailOp = VK_STENCIL_OP_REPLACE,
889+ .compareOp = VK_COMPARE_OP_ALWAYS,
890+ .compareMask = 0xff,
891+ .writeMask = 0xff,
892+ .reference = 0
893+ },
894+ .depthCompareOp = VK_COMPARE_OP_ALWAYS,
895+ };
896+
897+ switch(aspect) {
898+ case VK_IMAGE_ASPECT_COLOR_BIT:
899+ vk_pipeline_info.pColorBlendState = &color_blend_info;
865900 break;
866901 case VK_IMAGE_ASPECT_DEPTH_BIT:
867- vk_pipeline_info.pDepthStencilState = &(VkPipelineDepthStencilStateCreateInfo) {
868- .sType = VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO,
869- .depthTestEnable = true,
870- .depthWriteEnable = true,
871- .depthCompareOp = VK_COMPARE_OP_ALWAYS,
872- };
902+ vk_pipeline_info.pDepthStencilState = &depth_info;
873903 break;
874904 case VK_IMAGE_ASPECT_STENCIL_BIT:
875- vk_pipeline_info.pDepthStencilState = &(VkPipelineDepthStencilStateCreateInfo) {
876- .sType = VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO,
877- .depthTestEnable = false,
878- .depthWriteEnable = false,
879- .stencilTestEnable = true,
880- .front = {
881- .failOp = VK_STENCIL_OP_REPLACE,
882- .passOp = VK_STENCIL_OP_REPLACE,
883- .depthFailOp = VK_STENCIL_OP_REPLACE,
884- .compareOp = VK_COMPARE_OP_ALWAYS,
885- .compareMask = 0xff,
886- .writeMask = 0xff,
887- .reference = 0
888- },
889- .back = {
890- .failOp = VK_STENCIL_OP_REPLACE,
891- .passOp = VK_STENCIL_OP_REPLACE,
892- .depthFailOp = VK_STENCIL_OP_REPLACE,
893- .compareOp = VK_COMPARE_OP_ALWAYS,
894- .compareMask = 0xff,
895- .writeMask = 0xff,
896- .reference = 0
897- },
898- .depthCompareOp = VK_COMPARE_OP_ALWAYS,
899- };
905+ vk_pipeline_info.pDepthStencilState = &stencil_info;
900906 break;
901907 default:
902908 unreachable("Unhandled aspect");
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -3179,11 +3179,11 @@ radv_compute_db_shader_control(const struct radv_device *device,
31793179 bool disable_rbplus = device->physical_device->has_rbplus &&
31803180 !device->physical_device->rbplus_allowed;
31813181
3182- /* Do not enable the gl_SampleMask fragment shader output if MSAA is
3183- * disabled.
3182+ /* It shouldn't be needed to export gl_SampleMask when MSAA is disabled
3183+ * but this appears to break Project Cars (DXVK). See
3184+ * https://bugs.freedesktop.org/show_bug.cgi?id=109401
31843185 */
3185- bool mask_export_enable = ms->num_samples > 1 &&
3186- ps->info.info.ps.writes_sample_mask;
3186+ bool mask_export_enable = ps->info.info.ps.writes_sample_mask;
31873187
31883188 return S_02880C_Z_EXPORT_ENABLE(ps->info.info.ps.writes_z) |
31893189 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps->info.info.ps.writes_stencil) |
--- a/src/compiler/nir/nir_deref.c
+++ b/src/compiler/nir/nir_deref.c
@@ -490,10 +490,9 @@ nir_rematerialize_derefs_in_use_blocks_impl(nir_function_impl *impl)
490490 _mesa_hash_table_clear(state.cache, NULL);
491491
492492 nir_foreach_instr_safe(instr, block) {
493- if (instr->type == nir_instr_type_deref) {
494- nir_deref_instr_remove_if_unused(nir_instr_as_deref(instr));
493+ if (instr->type == nir_instr_type_deref &&
494+ nir_deref_instr_remove_if_unused(nir_instr_as_deref(instr)))
495495 continue;
496- }
497496
498497 state.builder.cursor = nir_before_instr(instr);
499498 nir_foreach_src(instr, rematerialize_deref_src, &state);
--- a/src/egl/drivers/dri2/egl_dri2.c
+++ b/src/egl/drivers/dri2/egl_dri2.c
@@ -2819,7 +2819,8 @@ dri2_bind_wayland_display_wl(_EGLDriver *drv, _EGLDisplay *disp,
28192819 const struct wayland_drm_callbacks wl_drm_callbacks = {
28202820 .authenticate = (int(*)(void *, uint32_t)) dri2_dpy->vtbl->authenticate,
28212821 .reference_buffer = dri2_wl_reference_buffer,
2822- .release_buffer = dri2_wl_release_buffer
2822+ .release_buffer = dri2_wl_release_buffer,
2823+ .is_format_supported = dri2_wl_is_format_supported
28232824 };
28242825 int flags = 0;
28252826 uint64_t cap;
--- a/src/egl/drivers/dri2/egl_dri2.h
+++ b/src/egl/drivers/dri2/egl_dri2.h
@@ -457,6 +457,8 @@ EGLBoolean
457457 dri2_initialize_wayland(_EGLDriver *drv, _EGLDisplay *disp);
458458 void
459459 dri2_teardown_wayland(struct dri2_egl_display *dri2_dpy);
460+bool
461+dri2_wl_is_format_supported(void* user_data, uint32_t format);
460462 #else
461463 static inline EGLBoolean
462464 dri2_initialize_wayland(_EGLDriver *drv, _EGLDisplay *disp)
--- a/src/egl/drivers/dri2/platform_wayland.c
+++ b/src/egl/drivers/dri2/platform_wayland.c
@@ -59,49 +59,57 @@ static const struct dri2_wl_visual {
5959 uint32_t wl_drm_format;
6060 uint32_t wl_shm_format;
6161 int dri_image_format;
62+ /* alt_dri_image_format is a substitute wl_buffer format to use for a
63+ * wl-server unsupported dri_image_format, ie. some other dri_image_format in
64+ * the table, of the same precision but with different channel ordering, or
65+ * __DRI_IMAGE_FORMAT_NONE if an alternate format is not needed or supported.
66+ * The code checks if alt_dri_image_format can be used as a fallback for a
67+ * dri_image_format for a given wl-server implementation.
68+ */
69+ int alt_dri_image_format;
6270 int bpp;
6371 unsigned int rgba_masks[4];
6472 } dri2_wl_visuals[] = {
6573 {
6674 "XRGB2101010",
6775 WL_DRM_FORMAT_XRGB2101010, WL_SHM_FORMAT_XRGB2101010,
68- __DRI_IMAGE_FORMAT_XRGB2101010, 32,
76+ __DRI_IMAGE_FORMAT_XRGB2101010, __DRI_IMAGE_FORMAT_XBGR2101010, 32,
6977 { 0x3ff00000, 0x000ffc00, 0x000003ff, 0x00000000 }
7078 },
7179 {
7280 "ARGB2101010",
7381 WL_DRM_FORMAT_ARGB2101010, WL_SHM_FORMAT_ARGB2101010,
74- __DRI_IMAGE_FORMAT_ARGB2101010, 32,
82+ __DRI_IMAGE_FORMAT_ARGB2101010, __DRI_IMAGE_FORMAT_ABGR2101010, 32,
7583 { 0x3ff00000, 0x000ffc00, 0x000003ff, 0xc0000000 }
7684 },
7785 {
7886 "XBGR2101010",
7987 WL_DRM_FORMAT_XBGR2101010, WL_SHM_FORMAT_XBGR2101010,
80- __DRI_IMAGE_FORMAT_XBGR2101010, 32,
88+ __DRI_IMAGE_FORMAT_XBGR2101010, __DRI_IMAGE_FORMAT_XRGB2101010, 32,
8189 { 0x000003ff, 0x000ffc00, 0x3ff00000, 0x00000000 }
8290 },
8391 {
8492 "ABGR2101010",
8593 WL_DRM_FORMAT_ABGR2101010, WL_SHM_FORMAT_ABGR2101010,
86- __DRI_IMAGE_FORMAT_ABGR2101010, 32,
94+ __DRI_IMAGE_FORMAT_ABGR2101010, __DRI_IMAGE_FORMAT_ARGB2101010, 32,
8795 { 0x000003ff, 0x000ffc00, 0x3ff00000, 0xc0000000 }
8896 },
8997 {
9098 "XRGB8888",
9199 WL_DRM_FORMAT_XRGB8888, WL_SHM_FORMAT_XRGB8888,
92- __DRI_IMAGE_FORMAT_XRGB8888, 32,
100+ __DRI_IMAGE_FORMAT_XRGB8888, __DRI_IMAGE_FORMAT_NONE, 32,
93101 { 0x00ff0000, 0x0000ff00, 0x000000ff, 0x00000000 }
94102 },
95103 {
96104 "ARGB8888",
97105 WL_DRM_FORMAT_ARGB8888, WL_SHM_FORMAT_ARGB8888,
98- __DRI_IMAGE_FORMAT_ARGB8888, 32,
106+ __DRI_IMAGE_FORMAT_ARGB8888, __DRI_IMAGE_FORMAT_NONE, 32,
99107 { 0x00ff0000, 0x0000ff00, 0x000000ff, 0xff000000 }
100108 },
101109 {
102110 "RGB565",
103111 WL_DRM_FORMAT_RGB565, WL_SHM_FORMAT_RGB565,
104- __DRI_IMAGE_FORMAT_RGB565, 16,
112+ __DRI_IMAGE_FORMAT_RGB565, __DRI_IMAGE_FORMAT_NONE, 16,
105113 { 0xf800, 0x07e0, 0x001f, 0x0000 }
106114 },
107115 };
@@ -166,6 +174,24 @@ dri2_wl_visual_idx_from_shm_format(uint32_t shm_format)
166174 return -1;
167175 }
168176
177+bool
178+dri2_wl_is_format_supported(void* user_data, uint32_t format)
179+{
180+ _EGLDisplay *disp = (_EGLDisplay *) user_data;
181+ struct dri2_egl_display *dri2_dpy = dri2_egl_display(disp);
182+ int j = dri2_wl_visual_idx_from_fourcc(format);
183+
184+ if (j == -1)
185+ return false;
186+
187+ for (int i = 0; dri2_dpy->driver_configs[i]; i++)
188+ if (j == dri2_wl_visual_idx_from_config(dri2_dpy,
189+ dri2_dpy->driver_configs[i]))
190+ return true;
191+
192+ return false;
193+}
194+
169195 static int
170196 roundtrip(struct dri2_egl_display *dri2_dpy)
171197 {
@@ -461,15 +487,29 @@ get_back_bo(struct dri2_egl_surface *dri2_surf)
461487 int use_flags;
462488 int visual_idx;
463489 unsigned int dri_image_format;
490+ unsigned int linear_dri_image_format;
464491 uint64_t *modifiers;
465492 int num_modifiers;
466493
467494 visual_idx = dri2_wl_visual_idx_from_fourcc(dri2_surf->format);
468495 assert(visual_idx != -1);
469496 dri_image_format = dri2_wl_visuals[visual_idx].dri_image_format;
497+ linear_dri_image_format = dri_image_format;
470498 modifiers = u_vector_tail(&dri2_dpy->wl_modifiers[visual_idx]);
471499 num_modifiers = u_vector_length(&dri2_dpy->wl_modifiers[visual_idx]);
472500
501+ /* Substitute dri image format if server does not support original format */
502+ if (!(dri2_dpy->formats & (1 << visual_idx)))
503+ linear_dri_image_format = dri2_wl_visuals[visual_idx].alt_dri_image_format;
504+
505+ /* These asserts hold, as long as dri2_wl_visuals[] is self-consistent and
506+ * the PRIME substitution logic in dri2_wl_add_configs_for_visuals() is free
507+ * of bugs.
508+ */
509+ assert(linear_dri_image_format != __DRI_IMAGE_FORMAT_NONE);
510+ assert(dri2_dpy->formats &
511+ (1 << dri2_wl_visual_idx_from_dri_image_format(linear_dri_image_format)));
512+
473513 /* There might be a buffer release already queued that wasn't processed */
474514 wl_display_dispatch_queue_pending(dri2_dpy->wl_dpy, dri2_surf->wl_queue);
475515
@@ -516,7 +556,7 @@ get_back_bo(struct dri2_egl_surface *dri2_surf)
516556 dri2_dpy->image->createImageWithModifiers(dri2_dpy->dri_screen,
517557 dri2_surf->base.Width,
518558 dri2_surf->base.Height,
519- dri_image_format,
559+ linear_dri_image_format,
520560 &linear_mod,
521561 1,
522562 NULL);
@@ -525,7 +565,7 @@ get_back_bo(struct dri2_egl_surface *dri2_surf)
525565 dri2_dpy->image->createImage(dri2_dpy->dri_screen,
526566 dri2_surf->base.Width,
527567 dri2_surf->base.Height,
528- dri_image_format,
568+ linear_dri_image_format,
529569 use_flags |
530570 __DRI_IMAGE_USE_LINEAR,
531571 NULL);
@@ -1298,8 +1338,11 @@ dri2_wl_add_configs_for_visuals(_EGLDriver *drv, _EGLDisplay *disp)
12981338 struct dri2_egl_display *dri2_dpy = dri2_egl_display(disp);
12991339 unsigned int format_count[ARRAY_SIZE(dri2_wl_visuals)] = { 0 };
13001340 unsigned int count = 0;
1341+ bool assigned;
13011342
13021343 for (unsigned i = 0; dri2_dpy->driver_configs[i]; i++) {
1344+ assigned = false;
1345+
13031346 for (unsigned j = 0; j < ARRAY_SIZE(dri2_wl_visuals); j++) {
13041347 struct dri2_egl_config *dri2_conf;
13051348
@@ -1312,6 +1355,43 @@ dri2_wl_add_configs_for_visuals(_EGLDriver *drv, _EGLDisplay *disp)
13121355 if (dri2_conf->base.ConfigID == count + 1)
13131356 count++;
13141357 format_count[j]++;
1358+ assigned = true;
1359+ }
1360+ }
1361+
1362+ if (!assigned && dri2_dpy->is_different_gpu) {
1363+ struct dri2_egl_config *dri2_conf;
1364+ int alt_dri_image_format, c, s;
1365+
1366+ /* No match for config. Try if we can blitImage convert to a visual */
1367+ c = dri2_wl_visual_idx_from_config(dri2_dpy,
1368+ dri2_dpy->driver_configs[i]);
1369+
1370+ if (c == -1)
1371+ continue;
1372+
1373+ /* Find optimal target visual for blitImage conversion, if any. */
1374+ alt_dri_image_format = dri2_wl_visuals[c].alt_dri_image_format;
1375+ s = dri2_wl_visual_idx_from_dri_image_format(alt_dri_image_format);
1376+
1377+ if (s == -1 || !(dri2_dpy->formats & (1 << s)))
1378+ continue;
1379+
1380+ /* Visual s works for the Wayland server, and c can be converted into s
1381+ * by our client gpu during PRIME blitImage conversion to a linear
1382+ * wl_buffer, so add visual c as supported by the client renderer.
1383+ */
1384+ dri2_conf = dri2_add_config(disp, dri2_dpy->driver_configs[i],
1385+ count + 1, EGL_WINDOW_BIT, NULL,
1386+ dri2_wl_visuals[c].rgba_masks);
1387+ if (dri2_conf) {
1388+ if (dri2_conf->base.ConfigID == count + 1)
1389+ count++;
1390+ format_count[c]++;
1391+ if (format_count[c] == 1)
1392+ _eglLog(_EGL_DEBUG, "Client format %s to server format %s via "
1393+ "PRIME blitImage.", dri2_wl_visuals[c].format_name,
1394+ dri2_wl_visuals[s].format_name);
13151395 }
13161396 }
13171397 }
--- a/src/egl/wayland/wayland-drm/wayland-drm.c
+++ b/src/egl/wayland/wayland-drm/wayland-drm.c
@@ -111,6 +111,8 @@ drm_create_buffer(struct wl_client *client, struct wl_resource *resource,
111111 uint32_t stride, uint32_t format)
112112 {
113113 switch (format) {
114+ case WL_DRM_FORMAT_ABGR2101010:
115+ case WL_DRM_FORMAT_XBGR2101010:
114116 case WL_DRM_FORMAT_ARGB2101010:
115117 case WL_DRM_FORMAT_XRGB2101010:
116118 case WL_DRM_FORMAT_ARGB8888:
@@ -210,10 +212,31 @@ bind_drm(struct wl_client *client, void *data, uint32_t version, uint32_t id)
210212 wl_resource_set_implementation(resource, &drm_interface, data, NULL);
211213
212214 wl_resource_post_event(resource, WL_DRM_DEVICE, drm->device_name);
213- wl_resource_post_event(resource, WL_DRM_FORMAT,
214- WL_DRM_FORMAT_ARGB2101010);
215- wl_resource_post_event(resource, WL_DRM_FORMAT,
216- WL_DRM_FORMAT_XRGB2101010);
215+
216+ if (drm->callbacks.is_format_supported(drm->user_data,
217+ WL_DRM_FORMAT_ARGB2101010)) {
218+ wl_resource_post_event(resource, WL_DRM_FORMAT,
219+ WL_DRM_FORMAT_ARGB2101010);
220+ }
221+
222+ if (drm->callbacks.is_format_supported(drm->user_data,
223+ WL_DRM_FORMAT_XRGB2101010)) {
224+ wl_resource_post_event(resource, WL_DRM_FORMAT,
225+ WL_DRM_FORMAT_XRGB2101010);
226+ }
227+
228+ if (drm->callbacks.is_format_supported(drm->user_data,
229+ WL_DRM_FORMAT_ABGR2101010)) {
230+ wl_resource_post_event(resource, WL_DRM_FORMAT,
231+ WL_DRM_FORMAT_ABGR2101010);
232+ }
233+
234+ if (drm->callbacks.is_format_supported(drm->user_data,
235+ WL_DRM_FORMAT_XBGR2101010)) {
236+ wl_resource_post_event(resource, WL_DRM_FORMAT,
237+ WL_DRM_FORMAT_XBGR2101010);
238+ }
239+
217240 wl_resource_post_event(resource, WL_DRM_FORMAT,
218241 WL_DRM_FORMAT_ARGB8888);
219242 wl_resource_post_event(resource, WL_DRM_FORMAT,
--- a/src/egl/wayland/wayland-drm/wayland-drm.h
+++ b/src/egl/wayland/wayland-drm/wayland-drm.h
@@ -14,6 +14,8 @@ struct wayland_drm_callbacks {
1414 struct wl_drm_buffer *buffer);
1515
1616 void (*release_buffer)(void *user_data, struct wl_drm_buffer *buffer);
17+
18+ bool (*is_format_supported)(void *user_data, uint32_t format);
1719 };
1820
1921
--- a/src/gallium/auxiliary/util/u_threaded_context.c
+++ b/src/gallium/auxiliary/util/u_threaded_context.c
@@ -1524,7 +1524,8 @@ tc_buffer_do_flush_region(struct threaded_context *tc,
15241524 if (ttrans->staging) {
15251525 struct pipe_box src_box;
15261526
1527- u_box_1d(ttrans->offset + box->x % tc->map_buffer_alignment,
1527+ u_box_1d(ttrans->offset + ttrans->b.box.x % tc->map_buffer_alignment +
1528+ (box->x - ttrans->b.box.x),
15281529 box->width, &src_box);
15291530
15301531 /* Copy the staging buffer into the original one. */
--- a/src/gallium/drivers/freedreno/a6xx/fd6_blitter.c
+++ b/src/gallium/drivers/freedreno/a6xx/fd6_blitter.c
@@ -430,7 +430,7 @@ emit_blit_texture(struct fd_ringbuffer *ring, const struct pipe_blit_info *info)
430430 OUT_RING(ring, A6XX_RB_2D_DST_INFO_COLOR_FORMAT(dfmt) |
431431 A6XX_RB_2D_DST_INFO_TILE_MODE(dtile) |
432432 A6XX_RB_2D_DST_INFO_COLOR_SWAP(dswap));
433- OUT_RELOC(ring, dst->bo, doff, 0, 0); /* RB_2D_DST_LO/HI */
433+ OUT_RELOCW(ring, dst->bo, doff, 0, 0); /* RB_2D_DST_LO/HI */
434434 OUT_RING(ring, A6XX_RB_2D_DST_SIZE_PITCH(dpitch));
435435 OUT_RING(ring, 0x00000000);
436436 OUT_RING(ring, 0x00000000);
--- a/src/gallium/drivers/freedreno/freedreno_resource.c
+++ b/src/gallium/drivers/freedreno/freedreno_resource.c
@@ -839,8 +839,7 @@ fd_resource_create(struct pipe_screen *pscreen,
839839
840840 rsc->internal_format = format;
841841 rsc->cpp = util_format_get_blocksize(format);
842- prsc->nr_samples = MAX2(1, prsc->nr_samples);
843- rsc->cpp *= prsc->nr_samples;
842+ rsc->cpp *= fd_resource_nr_samples(prsc);
844843
845844 assert(rsc->cpp);
846845
@@ -924,9 +923,9 @@ fd_resource_from_handle(struct pipe_screen *pscreen,
924923 if (!rsc->bo)
925924 goto fail;
926925
927- prsc->nr_samples = MAX2(1, prsc->nr_samples);
928926 rsc->internal_format = tmpl->format;
929- rsc->cpp = prsc->nr_samples * util_format_get_blocksize(tmpl->format);
927+ rsc->cpp = util_format_get_blocksize(tmpl->format);
928+ rsc->cpp *= fd_resource_nr_samples(prsc);
930929 slice->pitch = handle->stride / rsc->cpp;
931930 slice->offset = handle->offset;
932931 slice->size0 = handle->stride * prsc->height0;
--- a/src/gallium/drivers/freedreno/freedreno_resource.h
+++ b/src/gallium/drivers/freedreno/freedreno_resource.h
@@ -178,6 +178,15 @@ fd_resource_level_linear(struct pipe_resource *prsc, int level)
178178 return false;
179179 }
180180
181+/* access # of samples, with 0 normalized to 1 (which is what we care about
182+ * most of the time)
183+ */
184+static inline unsigned
185+fd_resource_nr_samples(struct pipe_resource *prsc)
186+{
187+ return MAX2(1, prsc->nr_samples);
188+}
189+
181190 void fd_blitter_pipe_begin(struct fd_context *ctx, bool render_cond, bool discard,
182191 enum fd_render_stage stage);
183192 void fd_blitter_pipe_end(struct fd_context *ctx);
--- a/src/gallium/drivers/freedreno/freedreno_texture.c
+++ b/src/gallium/drivers/freedreno/freedreno_texture.c
@@ -31,6 +31,7 @@
3131
3232 #include "freedreno_texture.h"
3333 #include "freedreno_context.h"
34+#include "freedreno_resource.h"
3435 #include "freedreno_util.h"
3536
3637 static void
@@ -83,7 +84,7 @@ static void set_sampler_views(struct fd_texture_stateobj *tex,
8384 tex->num_textures = util_last_bit(tex->valid_textures);
8485
8586 for (i = 0; i < tex->num_textures; i++) {
86- uint nr_samples = tex->textures[i]->texture->nr_samples;
87+ uint nr_samples = fd_resource_nr_samples(tex->textures[i]->texture);
8788 samplers |= (nr_samples >> 1) << (i * 2);
8889 }
8990
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
@@ -1278,8 +1278,8 @@ nvc0_screen_create(struct nouveau_device *dev)
12781278 for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
12791279 BEGIN_NVC0(push, NVC0_3D(SCISSOR_ENABLE(i)), 3);
12801280 PUSH_DATA (push, 1);
1281- PUSH_DATA (push, 8192 << 16);
1282- PUSH_DATA (push, 8192 << 16);
1281+ PUSH_DATA (push, 16384 << 16);
1282+ PUSH_DATA (push, 16384 << 16);
12831283 }
12841284
12851285 #define MK_MACRO(m, n) i = nvc0_graph_set_macro(screen, m, i, sizeof(n), n);
--- a/src/gallium/drivers/radeonsi/si_buffer.c
+++ b/src/gallium/drivers/radeonsi/si_buffer.c
@@ -521,10 +521,13 @@ static void si_buffer_do_flush_region(struct pipe_context *ctx,
521521 struct r600_resource *rbuffer = r600_resource(transfer->resource);
522522
523523 if (stransfer->staging) {
524+ unsigned src_offset = stransfer->offset +
525+ transfer->box.x % SI_MAP_BUFFER_ALIGNMENT +
526+ (box->x - transfer->box.x);
527+
524528 /* Copy the staging buffer into the original one. */
525529 si_copy_buffer((struct si_context*)ctx, transfer->resource,
526- &stransfer->staging->b.b, box->x,
527- stransfer->offset + box->x % SI_MAP_BUFFER_ALIGNMENT,
530+ &stransfer->staging->b.b, box->x, src_offset,
528531 box->width);
529532 }
530533
--- a/src/gallium/drivers/radeonsi/si_state_viewport.c
+++ b/src/gallium/drivers/radeonsi/si_state_viewport.c
@@ -185,6 +185,16 @@ static void si_emit_guardband(struct si_context *ctx)
185185 const unsigned hw_screen_offset_alignment =
186186 ctx->chip_class >= VI ? 16 : MAX2(ctx->screen->se_tile_repeat, 16);
187187
188+ /* Indexed by quantization modes */
189+ static unsigned max_viewport_size[] = {65535, 16383, 4095};
190+
191+ /* Ensure that the whole viewport stays representable in
192+ * absolute coordinates.
193+ * See comment in si_set_viewport_states.
194+ */
195+ assert(vp_as_scissor.maxx <= max_viewport_size[vp_as_scissor.quant_mode] &&
196+ vp_as_scissor.maxy <= max_viewport_size[vp_as_scissor.quant_mode]);
197+
188198 hw_screen_offset_x = CLAMP(hw_screen_offset_x, 0, MAX_PA_SU_HARDWARE_SCREEN_OFFSET);
189199 hw_screen_offset_y = CLAMP(hw_screen_offset_y, 0, MAX_PA_SU_HARDWARE_SCREEN_OFFSET);
190200
@@ -219,7 +229,6 @@ static void si_emit_guardband(struct si_context *ctx)
219229 *
220230 * The viewport range is [-max_viewport_size/2, max_viewport_size/2].
221231 */
222- static unsigned max_viewport_size[] = {65535, 16383, 4095};
223232 assert(vp_as_scissor.quant_mode < ARRAY_SIZE(max_viewport_size));
224233 max_range = max_viewport_size[vp_as_scissor.quant_mode] / 2;
225234 left = (-max_range - vp.translate[0]) / vp.scale[0];
@@ -333,6 +342,8 @@ static void si_set_viewport_states(struct pipe_context *pctx,
333342 unsigned h = scissor->maxy - scissor->miny;
334343 unsigned max_extent = MAX2(w, h);
335344
345+ int max_corner = MAX2(scissor->maxx, scissor->maxy);
346+
336347 unsigned center_x = (scissor->maxx + scissor->minx) / 2;
337348 unsigned center_y = (scissor->maxy + scissor->miny) / 2;
338349 unsigned max_center = MAX2(center_x, center_y);
@@ -358,7 +369,22 @@ static void si_set_viewport_states(struct pipe_context *pctx,
358369 if (ctx->family == CHIP_RAVEN)
359370 max_extent = 16384; /* Use QUANT_MODE == 16_8. */
360371
361- if (max_extent <= 1024) /* 4K scanline area for guardband */
372+ /* Another constraint is that all coordinates in the viewport
373+ * are representable in fixed point with respect to the
374+ * surface origin.
375+ *
376+ * It means that PA_SU_HARDWARE_SCREEN_OFFSET can't be given
377+ * an offset that would make the upper corner of the viewport
378+ * greater than the maximum representable number post
379+ * quantization, ie 2^quant_bits.
380+ *
381+ * This does not matter for 14.10 and 16.8 formats since the
382+ * offset is already limited at 8k, but it means we can't use
383+ * 12.12 if we are drawing to some pixels outside the lower
384+ * 4k x 4k of the render target.
385+ */
386+
387+ if (max_extent <= 1024 && max_corner < 4096) /* 4K scanline area for guardband */
362388 scissor->quant_mode = SI_QUANT_MODE_12_12_FIXED_POINT_1_4096TH;
363389 else if (max_extent <= 4096) /* 16K scanline area for guardband */
364390 scissor->quant_mode = SI_QUANT_MODE_14_10_FIXED_POINT_1_1024TH;
--- a/src/gallium/drivers/v3d/v3d_resource.c
+++ b/src/gallium/drivers/v3d/v3d_resource.c
@@ -669,7 +669,7 @@ v3d_resource_create_with_modifiers(struct pipe_screen *pscreen,
669669 rsc->tiled = false;
670670 } else {
671671 fprintf(stderr, "Unsupported modifier requested\n");
672- return NULL;
672+ goto fail;
673673 }
674674
675675 rsc->internal_format = prsc->format;
--- a/src/gallium/drivers/vc4/vc4_query.c
+++ b/src/gallium/drivers/vc4/vc4_query.c
@@ -132,7 +132,7 @@ vc4_create_batch_query(struct pipe_context *pctx, unsigned num_queries,
132132
133133 /* We can't mix HW and non-HW queries. */
134134 if (nhwqueries && nhwqueries != num_queries)
135- return NULL;
135+ goto err_free_query;
136136
137137 if (!nhwqueries)
138138 return (struct pipe_query *)query;
--- a/src/gallium/drivers/vc4/vc4_tiling_lt.c
+++ b/src/gallium/drivers/vc4/vc4_tiling_lt.c
@@ -194,7 +194,7 @@ vc4_store_utile(void *gpu, void *cpu, uint32_t cpu_stride, uint32_t cpp)
194194 * d0-d7.
195195 */
196196 "vstm %[gpu], {q0, q1, q2, q3}\n"
197- : [cpu] "r"(cpu)
197+ : [cpu] "+r"(cpu)
198198 : [gpu] "r"(gpu),
199199 [cpu_stride] "r"(cpu_stride)
200200 : "q0", "q1", "q2", "q3");
--- a/src/gallium/include/pipe/p_video_enums.h
+++ b/src/gallium/include/pipe/p_video_enums.h
@@ -70,7 +70,8 @@ enum pipe_video_profile
7070 PIPE_VIDEO_PROFILE_HEVC_MAIN_444,
7171 PIPE_VIDEO_PROFILE_JPEG_BASELINE,
7272 PIPE_VIDEO_PROFILE_VP9_PROFILE0,
73- PIPE_VIDEO_PROFILE_VP9_PROFILE2
73+ PIPE_VIDEO_PROFILE_VP9_PROFILE2,
74+ PIPE_VIDEO_PROFILE_MAX
7475 };
7576
7677 /* Video caps, can be different for each codec/profile */
--- a/src/gallium/state_trackers/va/context.c
+++ b/src/gallium/state_trackers/va/context.c
@@ -175,7 +175,7 @@ VA_DRIVER_INIT_FUNC(VADriverContextP ctx)
175175 ctx->version_minor = 1;
176176 *ctx->vtable = vtable;
177177 *ctx->vtable_vpp = vtable_vpp;
178- ctx->max_profiles = PIPE_VIDEO_PROFILE_MPEG4_AVC_HIGH - PIPE_VIDEO_PROFILE_UNKNOWN;
178+ ctx->max_profiles = PIPE_VIDEO_PROFILE_MAX - PIPE_VIDEO_PROFILE_UNKNOWN - 1;
179179 ctx->max_entrypoints = 2;
180180 ctx->max_attributes = 1;
181181 ctx->max_image_formats = VL_VA_MAX_IMAGE_FORMATS;
--- a/src/gallium/state_trackers/va/picture_vp9.c
+++ b/src/gallium/state_trackers/va/picture_vp9.c
@@ -28,6 +28,8 @@
2828 #include "vl/vl_vlc.h"
2929 #include "va_private.h"
3030
31+#define NUM_VP9_REFS 8
32+
3133 void vlVaHandlePictureParameterBufferVP9(vlVaDriver *drv, vlVaContext *context, vlVaBuffer *buf)
3234 {
3335 VADecPictureParameterBufferVP9 *vp9 = buf->data;
@@ -79,8 +81,11 @@ void vlVaHandlePictureParameterBufferVP9(vlVaDriver *drv, vlVaContext *context,
7981
8082 context->desc.vp9.picture_parameter.bit_depth = vp9->bit_depth;
8183
82- for (i = 0 ; i < 8 ; i++)
84+ for (i = 0 ; i < NUM_VP9_REFS ; i++)
8385 vlVaGetReferenceFrame(drv, vp9->reference_frames[i], &context->desc.vp9.ref[i]);
86+
87+ if (!context->decoder && !context->templat.max_references)
88+ context->templat.max_references = NUM_VP9_REFS;
8489 }
8590
8691 void vlVaHandleSliceParameterBufferVP9(vlVaContext *context, vlVaBuffer *buf)
--- a/src/gallium/state_trackers/xvmc/attributes.c
+++ b/src/gallium/state_trackers/xvmc/attributes.c
@@ -90,15 +90,15 @@ Status XvMCSetAttribute(Display *dpy, XvMCContext *context, Atom attribute, int
9090 if (!attr)
9191 return XvMCBadContext;
9292
93- if (strcmp(attr, XV_BRIGHTNESS))
93+ if (strcmp(attr, XV_BRIGHTNESS) == 0)
9494 context_priv->procamp.brightness = value / 1000.0f;
95- else if (strcmp(attr, XV_CONTRAST))
95+ else if (strcmp(attr, XV_CONTRAST) == 0)
9696 context_priv->procamp.contrast = value / 1000.0f + 1.0f;
97- else if (strcmp(attr, XV_SATURATION))
97+ else if (strcmp(attr, XV_SATURATION) == 0)
9898 context_priv->procamp.saturation = value / 1000.0f + 1.0f;
99- else if (strcmp(attr, XV_HUE))
99+ else if (strcmp(attr, XV_HUE) == 0)
100100 context_priv->procamp.hue = value / 1000.0f;
101- else if (strcmp(attr, XV_COLORSPACE))
101+ else if (strcmp(attr, XV_COLORSPACE) == 0)
102102 context_priv->color_standard = value ?
103103 VL_CSC_COLOR_STANDARD_BT_601 :
104104 VL_CSC_COLOR_STANDARD_BT_709;
@@ -134,15 +134,15 @@ Status XvMCGetAttribute(Display *dpy, XvMCContext *context, Atom attribute, int
134134 if (!attr)
135135 return XvMCBadContext;
136136
137- if (strcmp(attr, XV_BRIGHTNESS))
137+ if (strcmp(attr, XV_BRIGHTNESS) == 0)
138138 *value = context_priv->procamp.brightness * 1000;
139- else if (strcmp(attr, XV_CONTRAST))
139+ else if (strcmp(attr, XV_CONTRAST) == 0)
140140 *value = context_priv->procamp.contrast * 1000 - 1000;
141- else if (strcmp(attr, XV_SATURATION))
141+ else if (strcmp(attr, XV_SATURATION) == 0)
142142 *value = context_priv->procamp.saturation * 1000 + 1000;
143- else if (strcmp(attr, XV_HUE))
143+ else if (strcmp(attr, XV_HUE) == 0)
144144 *value = context_priv->procamp.hue * 1000;
145- else if (strcmp(attr, XV_COLORSPACE))
145+ else if (strcmp(attr, XV_COLORSPACE) == 0)
146146 *value = context_priv->color_standard == VL_CSC_COLOR_STANDARD_BT_709;
147147 else
148148 return BadName;
--- a/src/gallium/state_trackers/xvmc/tests/xvmc_bench.c
+++ b/src/gallium/state_trackers/xvmc/tests/xvmc_bench.c
@@ -123,11 +123,11 @@ void ParseArgs(int argc, char **argv, struct Config *config)
123123
124124 while (token && !fail)
125125 {
126- if (strcmp(token, "i"))
126+ if (strcmp(token, "i") == 0)
127127 config->mb_types |= MB_TYPE_I;
128- else if (strcmp(token, "p"))
128+ else if (strcmp(token, "p") == 0)
129129 config->mb_types |= MB_TYPE_P;
130- else if (strcmp(token, "b"))
130+ else if (strcmp(token, "b") == 0)
131131 config->mb_types |= MB_TYPE_B;
132132 else
133133 fail = 1;
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
@@ -1217,8 +1217,6 @@ static void amdgpu_add_fence_dependencies_bo_lists(struct amdgpu_cs *acs)
12171217 {
12181218 struct amdgpu_cs_context *cs = acs->csc;
12191219
1220- cs->num_fence_dependencies = 0;
1221-
12221220 amdgpu_add_fence_dependencies_bo_list(acs, cs->fence, cs->num_real_buffers, cs->real_buffers);
12231221 amdgpu_add_fence_dependencies_bo_list(acs, cs->fence, cs->num_slab_buffers, cs->slab_buffers);
12241222 amdgpu_add_fence_dependencies_bo_list(acs, cs->fence, cs->num_sparse_buffers, cs->sparse_buffers);
--- a/src/gallium/winsys/sw/xlib/xlib_sw_winsys.c
+++ b/src/gallium/winsys/sw/xlib/xlib_sw_winsys.c
@@ -396,6 +396,7 @@ xlib_displaytarget_create(struct sw_winsys *winsys,
396396 {
397397 struct xlib_displaytarget *xlib_dt;
398398 unsigned nblocksy, size;
399+ int ignore;
399400
400401 xlib_dt = CALLOC_STRUCT(xlib_displaytarget);
401402 if (!xlib_dt)
@@ -410,7 +411,8 @@ xlib_displaytarget_create(struct sw_winsys *winsys,
410411 xlib_dt->stride = align(util_format_get_stride(format, width), alignment);
411412 size = xlib_dt->stride * nblocksy;
412413
413- if (!debug_get_option_xlib_no_shm()) {
414+ if (!debug_get_option_xlib_no_shm() &&
415+ XQueryExtension(xlib_dt->display, "MIT-SHM", &ignore, &ignore, &ignore)) {
414416 xlib_dt->data = alloc_shm(xlib_dt, size);
415417 if (xlib_dt->data) {
416418 xlib_dt->shm = True;
--- a/src/intel/compiler/brw_fs.cpp
+++ b/src/intel/compiler/brw_fs.cpp
@@ -251,6 +251,7 @@ fs_inst::is_send_from_grf() const
251251 case SHADER_OPCODE_TYPED_ATOMIC:
252252 case SHADER_OPCODE_TYPED_SURFACE_READ:
253253 case SHADER_OPCODE_TYPED_SURFACE_WRITE:
254+ case SHADER_OPCODE_IMAGE_SIZE:
254255 case SHADER_OPCODE_URB_WRITE_SIMD8:
255256 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
256257 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
@@ -892,6 +893,7 @@ fs_inst::size_read(int arg) const
892893 case SHADER_OPCODE_TYPED_ATOMIC:
893894 case SHADER_OPCODE_TYPED_SURFACE_READ:
894895 case SHADER_OPCODE_TYPED_SURFACE_WRITE:
896+ case SHADER_OPCODE_IMAGE_SIZE:
895897 case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
896898 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
897899 case SHADER_OPCODE_BYTE_SCATTERED_WRITE:
--- a/src/intel/compiler/brw_fs_copy_propagation.cpp
+++ b/src/intel/compiler/brw_fs_copy_propagation.cpp
@@ -371,6 +371,20 @@ can_take_stride(fs_inst *inst, unsigned arg, unsigned stride,
371371 return true;
372372 }
373373
374+static bool
375+instruction_requires_packed_data(fs_inst *inst)
376+{
377+ switch (inst->opcode) {
378+ case FS_OPCODE_DDX_FINE:
379+ case FS_OPCODE_DDX_COARSE:
380+ case FS_OPCODE_DDY_FINE:
381+ case FS_OPCODE_DDY_COARSE:
382+ return true;
383+ default:
384+ return false;
385+ }
386+}
387+
374388 bool
375389 fs_visitor::try_copy_propagate(fs_inst *inst, int arg, acp_entry *entry)
376390 {
@@ -417,6 +431,13 @@ fs_visitor::try_copy_propagate(fs_inst *inst, int arg, acp_entry *entry)
417431 inst->opcode == SHADER_OPCODE_GEN4_SCRATCH_WRITE)
418432 return false;
419433
434+ /* Some instructions implemented in the generator backend, such as
435+ * derivatives, assume that their operands are packed so we can't
436+ * generally propagate strided regions to them.
437+ */
438+ if (instruction_requires_packed_data(inst) && entry->src.stride > 1)
439+ return false;
440+
420441 /* Bail if the result of composing both strides would exceed the
421442 * hardware limit.
422443 */
--- a/src/intel/compiler/brw_fs_reg_allocate.cpp
+++ b/src/intel/compiler/brw_fs_reg_allocate.cpp
@@ -667,15 +667,14 @@ fs_visitor::assign_regs(bool allow_spilling, bool spill_all)
667667 * messages adding a node interference to the grf127_send_hack_node.
668668 * This node has a fixed asignment to grf127.
669669 *
670- * We don't apply it to SIMD16 because previous code avoids any register
671- * overlap between sources and destination.
670+ * We don't apply it to SIMD16 instructions because previous code avoids
671+ * any register overlap between sources and destination.
672672 */
673673 ra_set_node_reg(g, grf127_send_hack_node, 127);
674- if (dispatch_width == 8) {
675- foreach_block_and_inst(block, fs_inst, inst, cfg) {
676- if (inst->is_send_from_grf() && inst->dst.file == VGRF)
677- ra_add_node_interference(g, inst->dst.nr, grf127_send_hack_node);
678- }
674+ foreach_block_and_inst(block, fs_inst, inst, cfg) {
675+ if (inst->exec_size < 16 && inst->is_send_from_grf() &&
676+ inst->dst.file == VGRF)
677+ ra_add_node_interference(g, inst->dst.nr, grf127_send_hack_node);
679678 }
680679
681680 if (spilled_any_registers) {
--- a/src/intel/vulkan/gen7_cmd_buffer.c
+++ b/src/intel/vulkan/gen7_cmd_buffer.c
@@ -70,12 +70,36 @@ gen7_cmd_buffer_emit_scissor(struct anv_cmd_buffer *cmd_buffer)
7070 };
7171
7272 const int max = 0xffff;
73+
74+ uint32_t y_min = s->offset.y;
75+ uint32_t x_min = s->offset.x;
76+ uint32_t y_max = s->offset.y + s->extent.height - 1;
77+ uint32_t x_max = s->offset.x + s->extent.width - 1;
78+
79+ /* Do this math using int64_t so overflow gets clamped correctly. */
80+ if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) {
81+ y_min = clamp_int64((uint64_t) y_min,
82+ cmd_buffer->state.render_area.offset.y, max);
83+ x_min = clamp_int64((uint64_t) x_min,
84+ cmd_buffer->state.render_area.offset.x, max);
85+ y_max = clamp_int64((uint64_t) y_max, 0,
86+ cmd_buffer->state.render_area.offset.y +
87+ cmd_buffer->state.render_area.extent.height - 1);
88+ x_max = clamp_int64((uint64_t) x_max, 0,
89+ cmd_buffer->state.render_area.offset.x +
90+ cmd_buffer->state.render_area.extent.width - 1);
91+ } else if (fb) {
92+ y_min = clamp_int64((uint64_t) y_min, 0, max);
93+ x_min = clamp_int64((uint64_t) x_min, 0, max);
94+ y_max = clamp_int64((uint64_t) y_max, 0, fb->height - 1);
95+ x_max = clamp_int64((uint64_t) x_max, 0, fb->width - 1);
96+ }
97+
7398 struct GEN7_SCISSOR_RECT scissor = {
74- /* Do this math using int64_t so overflow gets clamped correctly. */
75- .ScissorRectangleYMin = clamp_int64(s->offset.y, 0, max),
76- .ScissorRectangleXMin = clamp_int64(s->offset.x, 0, max),
77- .ScissorRectangleYMax = clamp_int64((uint64_t) s->offset.y + s->extent.height - 1, 0, fb->height - 1),
78- .ScissorRectangleXMax = clamp_int64((uint64_t) s->offset.x + s->extent.width - 1, 0, fb->width - 1)
99+ .ScissorRectangleYMin = y_min,
100+ .ScissorRectangleXMin = x_min,
101+ .ScissorRectangleYMax = y_max,
102+ .ScissorRectangleXMax = x_max
79103 };
80104
81105 if (s->extent.width <= 0 || s->extent.height <= 0) {
--- a/src/intel/vulkan/meson.build
+++ b/src/intel/vulkan/meson.build
@@ -1,4 +1,4 @@
1-# Copyright © 2017-2018 Intel Corporation
1+# Copyright © 2017-2019 Intel Corporation
22
33 # Permission is hereby granted, free of charge, to any person obtaining a copy
44 # of this software and associated documentation files (the "Software"), to deal
@@ -176,7 +176,10 @@ endif
176176
177177 libanv_common = static_library(
178178 'anv_common',
179- [libanv_files, anv_entrypoints, anv_extensions_c, anv_extensions_h, sha1_h],
179+ [
180+ libanv_files, anv_entrypoints, anv_extensions_c, anv_extensions_h, sha1_h,
181+ gen_xml_pack,
182+ ],
180183 include_directories : [
181184 inc_common, inc_intel, inc_compiler, inc_drm_uapi, inc_vulkan_util,
182185 inc_vulkan_wsi,
--- a/src/mesa/state_tracker/st_extensions.c
+++ b/src/mesa/state_tracker/st_extensions.c
@@ -222,8 +222,13 @@ void st_init_limits(struct pipe_screen *screen,
222222 pc->MaxUniformComponents = MIN2(pc->MaxUniformComponents,
223223 MAX_UNIFORMS * 4);
224224
225+ /* For ARB programs, prog_src_register::Index is a signed 13-bit number.
226+ * This gives us a limit of 4096 values - but we may need to generate
227+ * internal values in addition to what the source program uses. So, we
228+ * drop the limit one step lower, to 2048, to be safe.
229+ */
225230 pc->MaxParameters =
226- pc->MaxNativeParameters = pc->MaxUniformComponents / 4;
231+ pc->MaxNativeParameters = MIN2(pc->MaxUniformComponents / 4, 2048);
227232 pc->MaxInputComponents =
228233 screen->get_shader_param(screen, sh, PIPE_SHADER_CAP_MAX_INPUTS) * 4;
229234 pc->MaxOutputComponents =
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