| Revision | f19afaa519c2aa51d8449168fa83a98f2f04e0e5 (tree) |
|---|---|
| Time | 2019-01-17 06:39:25 |
| Author | Marek Olšák <marek.olsak@amd....> |
| Commiter | Marek Olšák |
amdgpu: add a faster BO list API
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
amdgpu/amdgpu-symbol-check (diff)
amdgpu/amdgpu.h (diff)
amdgpu/amdgpu_bo.c (diff) amdgpu/amdgpu_cs.c (diff)| @@ -19,6 +19,8 @@ amdgpu_bo_export | ||
| 19 | 19 | amdgpu_bo_free |
| 20 | 20 | amdgpu_bo_import |
| 21 | 21 | amdgpu_bo_inc_ref |
| 22 | +amdgpu_bo_list_create_raw | |
| 23 | +amdgpu_bo_list_destroy_raw | |
| 22 | 24 | amdgpu_bo_list_create |
| 23 | 25 | amdgpu_bo_list_destroy |
| 24 | 26 | amdgpu_bo_list_update |
| @@ -47,6 +49,7 @@ amdgpu_query_sw_info | ||
| 47 | 49 | amdgpu_cs_signal_semaphore |
| 48 | 50 | amdgpu_cs_submit |
| 49 | 51 | amdgpu_cs_submit_raw |
| 52 | +amdgpu_cs_submit_raw2 | |
| 50 | 53 | amdgpu_cs_syncobj_export_sync_file |
| 51 | 54 | amdgpu_cs_syncobj_import_sync_file |
| 52 | 55 | amdgpu_cs_syncobj_reset |
| @@ -42,6 +42,7 @@ extern "C" { | ||
| 42 | 42 | #endif |
| 43 | 43 | |
| 44 | 44 | struct drm_amdgpu_info_hw_ip; |
| 45 | +struct drm_amdgpu_bo_list_entry; | |
| 45 | 46 | |
| 46 | 47 | /*--------------------------------------------------------------------------*/ |
| 47 | 48 | /* --------------------------- Defines ------------------------------------ */ |
| @@ -779,6 +780,37 @@ int amdgpu_bo_wait_for_idle(amdgpu_bo_handle buf_handle, | ||
| 779 | 780 | * |
| 780 | 781 | * \param dev - \c [in] Device handle. |
| 781 | 782 | * See #amdgpu_device_initialize() |
| 783 | + * \param number_of_buffers - \c [in] Number of BOs in the list | |
| 784 | + * \param buffers - \c [in] List of BO handles | |
| 785 | + * \param result - \c [out] Created BO list handle | |
| 786 | + * | |
| 787 | + * \return 0 on success\n | |
| 788 | + * <0 - Negative POSIX Error code | |
| 789 | + * | |
| 790 | + * \sa amdgpu_bo_list_destroy_raw(), amdgpu_cs_submit_raw2() | |
| 791 | +*/ | |
| 792 | +int amdgpu_bo_list_create_raw(amdgpu_device_handle dev, | |
| 793 | + uint32_t number_of_buffers, | |
| 794 | + struct drm_amdgpu_bo_list_entry *buffers, | |
| 795 | + uint32_t *result); | |
| 796 | + | |
| 797 | +/** | |
| 798 | + * Destroys a BO list handle. | |
| 799 | + * | |
| 800 | + * \param bo_list - \c [in] BO list handle. | |
| 801 | + * | |
| 802 | + * \return 0 on success\n | |
| 803 | + * <0 - Negative POSIX Error code | |
| 804 | + * | |
| 805 | + * \sa amdgpu_bo_list_create_raw(), amdgpu_cs_submit_raw2() | |
| 806 | +*/ | |
| 807 | +int amdgpu_bo_list_destroy_raw(amdgpu_device_handle dev, uint32_t bo_list); | |
| 808 | + | |
| 809 | +/** | |
| 810 | + * Creates a BO list handle for command submission. | |
| 811 | + * | |
| 812 | + * \param dev - \c [in] Device handle. | |
| 813 | + * See #amdgpu_device_initialize() | |
| 782 | 814 | * \param number_of_resources - \c [in] Number of BOs in the list |
| 783 | 815 | * \param resources - \c [in] List of BO handles |
| 784 | 816 | * \param resource_prios - \c [in] Optional priority for each handle |
| @@ -1587,6 +1619,28 @@ int amdgpu_cs_submit_raw(amdgpu_device_handle dev, | ||
| 1587 | 1619 | struct drm_amdgpu_cs_chunk *chunks, |
| 1588 | 1620 | uint64_t *seq_no); |
| 1589 | 1621 | |
| 1622 | +/** | |
| 1623 | + * Submit raw command submission to the kernel with a raw BO list handle. | |
| 1624 | + * | |
| 1625 | + * \param dev - \c [in] device handle | |
| 1626 | + * \param context - \c [in] context handle for context id | |
| 1627 | + * \param bo_list_handle - \c [in] raw bo list handle (0 for none) | |
| 1628 | + * \param num_chunks - \c [in] number of CS chunks to submit | |
| 1629 | + * \param chunks - \c [in] array of CS chunks | |
| 1630 | + * \param seq_no - \c [out] output sequence number for submission. | |
| 1631 | + * | |
| 1632 | + * \return 0 on success\n | |
| 1633 | + * <0 - Negative POSIX Error code | |
| 1634 | + * | |
| 1635 | + * \sa amdgpu_bo_list_create_raw(), amdgpu_bo_list_destroy_raw() | |
| 1636 | + */ | |
| 1637 | +int amdgpu_cs_submit_raw2(amdgpu_device_handle dev, | |
| 1638 | + amdgpu_context_handle context, | |
| 1639 | + uint32_t bo_list_handle, | |
| 1640 | + int num_chunks, | |
| 1641 | + struct drm_amdgpu_cs_chunk *chunks, | |
| 1642 | + uint64_t *seq_no); | |
| 1643 | + | |
| 1590 | 1644 | void amdgpu_cs_chunk_fence_to_dep(struct amdgpu_cs_fence *fence, |
| 1591 | 1645 | struct drm_amdgpu_cs_chunk_dep *dep); |
| 1592 | 1646 | void amdgpu_cs_chunk_fence_info_to_data(struct amdgpu_cs_fence_info *fence_info, |
| @@ -618,6 +618,40 @@ out: | ||
| 618 | 618 | return r; |
| 619 | 619 | } |
| 620 | 620 | |
| 621 | +drm_public int amdgpu_bo_list_create_raw(amdgpu_device_handle dev, | |
| 622 | + uint32_t number_of_buffers, | |
| 623 | + struct drm_amdgpu_bo_list_entry *buffers, | |
| 624 | + uint32_t *result) | |
| 625 | +{ | |
| 626 | + union drm_amdgpu_bo_list args; | |
| 627 | + int r; | |
| 628 | + | |
| 629 | + memset(&args, 0, sizeof(args)); | |
| 630 | + args.in.operation = AMDGPU_BO_LIST_OP_CREATE; | |
| 631 | + args.in.bo_number = number_of_buffers; | |
| 632 | + args.in.bo_info_size = sizeof(struct drm_amdgpu_bo_list_entry); | |
| 633 | + args.in.bo_info_ptr = (uint64_t)(uintptr_t)buffers; | |
| 634 | + | |
| 635 | + r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_BO_LIST, | |
| 636 | + &args, sizeof(args)); | |
| 637 | + if (!r) | |
| 638 | + *result = args.out.list_handle; | |
| 639 | + return r; | |
| 640 | +} | |
| 641 | + | |
| 642 | +drm_public int amdgpu_bo_list_destroy_raw(amdgpu_device_handle dev, | |
| 643 | + uint32_t bo_list) | |
| 644 | +{ | |
| 645 | + union drm_amdgpu_bo_list args; | |
| 646 | + | |
| 647 | + memset(&args, 0, sizeof(args)); | |
| 648 | + args.in.operation = AMDGPU_BO_LIST_OP_DESTROY; | |
| 649 | + args.in.list_handle = bo_list; | |
| 650 | + | |
| 651 | + return drmCommandWriteRead(dev->fd, DRM_AMDGPU_BO_LIST, | |
| 652 | + &args, sizeof(args)); | |
| 653 | +} | |
| 654 | + | |
| 621 | 655 | drm_public int amdgpu_bo_list_create(amdgpu_device_handle dev, |
| 622 | 656 | uint32_t number_of_resources, |
| 623 | 657 | amdgpu_bo_handle *resources, |
| @@ -731,6 +731,31 @@ drm_public int amdgpu_cs_submit_raw(amdgpu_device_handle dev, | ||
| 731 | 731 | return 0; |
| 732 | 732 | } |
| 733 | 733 | |
| 734 | +drm_public int amdgpu_cs_submit_raw2(amdgpu_device_handle dev, | |
| 735 | + amdgpu_context_handle context, | |
| 736 | + uint32_t bo_list_handle, | |
| 737 | + int num_chunks, | |
| 738 | + struct drm_amdgpu_cs_chunk *chunks, | |
| 739 | + uint64_t *seq_no) | |
| 740 | +{ | |
| 741 | + union drm_amdgpu_cs cs = {0}; | |
| 742 | + uint64_t *chunk_array; | |
| 743 | + int i, r; | |
| 744 | + | |
| 745 | + chunk_array = alloca(sizeof(uint64_t) * num_chunks); | |
| 746 | + for (i = 0; i < num_chunks; i++) | |
| 747 | + chunk_array[i] = (uint64_t)(uintptr_t)&chunks[i]; | |
| 748 | + cs.in.chunks = (uint64_t)(uintptr_t)chunk_array; | |
| 749 | + cs.in.ctx_id = context->id; | |
| 750 | + cs.in.bo_list_handle = bo_list_handle; | |
| 751 | + cs.in.num_chunks = num_chunks; | |
| 752 | + r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_CS, | |
| 753 | + &cs, sizeof(cs)); | |
| 754 | + if (!r && seq_no) | |
| 755 | + *seq_no = cs.out.handle; | |
| 756 | + return r; | |
| 757 | +} | |
| 758 | + | |
| 734 | 759 | drm_public void amdgpu_cs_chunk_fence_info_to_data(struct amdgpu_cs_fence_info *fence_info, |
| 735 | 760 | struct drm_amdgpu_cs_chunk_data *data) |
| 736 | 761 | { |
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